CN101458294B - Method for downloading user code in chip when multi-chip test by tester - Google Patents
Method for downloading user code in chip when multi-chip test by tester Download PDFInfo
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- CN101458294B CN101458294B CN2007100944130A CN200710094413A CN101458294B CN 101458294 B CN101458294 B CN 101458294B CN 2007100944130 A CN2007100944130 A CN 2007100944130A CN 200710094413 A CN200710094413 A CN 200710094413A CN 101458294 B CN101458294 B CN 101458294B
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Abstract
The invention discloses a method for downloading user codes in a chip when adopting a tester to test a plurality of chips. Aiming at the situation that the user code data written in each chip are required to be different when a plurality of chips are determined simultaneously, when the data is downloaded, the data required to be downloaded are stored in a digital waveform generator of the tester and are linked with different chip test channels via the digital waveform generator, the code data of connected resources are written into a storage unit of a designated chip by transferring SQPG test vector, ensuring that different chips have different data when being tested simultaneously. In the method of the invention, by specially using the simulation test unit hardware of the tester, the tester can write any data to the storage unit in the chip more rapidly.
Description
Technical field
The invention belongs to the semiconductor production technical field of measurement and test, relate to the back road test of integrated circuit, particularly a kind of tester user code method for down loading in the chip during a plurality of chip testing.
Background technology
In the chip to be tested storage unit is arranged, tester generally includes unit of testing and controlling, hard disk, register, algorithm pattern generator (ALPG), sequence pattern generator (SQPG), digital waveform generator, digital waveform generator is arranged in the tester simulation test unit, is generally used for carrying out simulation test.As shown in Figure 1, tester is during at the same time to a plurality of chip testing, the user generally requires the user code in the storage unit of each chip different, when the data of carrying out user code are downloaded, existing method is to want the first user code data that read from the hard disk of tester in the file to pass to the register of tester, import the user code in the register into ALPG again, by operation ALPG pattern (test vector of algorithm pattern generator), user code is write the storage unit of corresponding chip to be measured by a plurality of chip testing passages then.But because the restriction of the figure place of the register of tester, can only pass 64 bits once general at most, can consume a large amount of test durations.
Summary of the invention
The technical problem to be solved in the present invention provides a kind of user code method for down loading in the chip during to a plurality of chip testing when tester simultaneous, adopts this method to make the different user code data accomplish to download fast at each chip.
For solving the problems of the technologies described above, the tester of the present invention technical scheme that the user code method for down loading adopts in the chip during to a plurality of chip testing is, tester comprises unit of testing and controlling, hard disk, sequence pattern generator, digital waveform generator, it is characterized in that, may further comprise the steps:
(1). set up the data file number of the user code of corresponding each piece chip of array;
(2). read array, which data file decision calls;
(3). convert described data file to 2 system forms and deposit in the digital waveform generator;
(4). the setting digital waveform generator links with a plurality of chip testing passages, and described digital waveform generator is the storer of many bits, the test channel of different chips is linked to the different bits of digital waveform generator;
(5). be written in the storage unit of each corresponding chip to be measured by the write order form of calling sequence graph generator testing vector the storage unit of the data based chip in the digital waveform generator.
Tester of the present invention user code method for down loading in the chip during to a plurality of chip testing, to need data downloaded to be read in the digital waveform generator of tester as array file earlier, after this each data write as long as directly call from digital waveform generator, read a secondary data and the form that takes a turn for the better when promptly only need pack wafer (wafer) into deposits in the digital waveform generator and gets final product at every turn, allow tester write arbitrary data to the storage unit in the chip faster by uniqueness utilization, accelerated the speed of the download of different user code data when the multicore sheet is tested simultaneously the tester simulation test unit hardware.
Description of drawings
Below in conjunction with the drawings and the specific embodiments the present invention is described in further detail.
Fig. 1 is a common tester user code method for down loading synoptic diagram in the chip during to a plurality of chip testing;
Fig. 2 is tester of the present invention user code method for down loading one in the chip during to a plurality of chip testing
The embodiment synoptic diagram.
Embodiment
Tester of the present invention during to a plurality of chip testing in the chip embodiment of user code method for down loading may further comprise the steps as shown in Figure 2:
1. in the storer of the unit of testing and controlling of tester, set up 1 array A, the data file of user code in the tester hard disk of corresponding each piece chip number;
2. when each test, read array A, which data file decision calls;
3. the data in this data file are carried out format conversion and deposit in the digital waveform generator.Data file generally is the number of 16 systems, and digital waveform generator can only be accepted the data of 2 system forms.Therefore this data file to be converted to 2 system forms, and then correspond on each bit of digital waveform generator.
4. set the link (link) of digital waveform generator and a plurality of chip testing passages, digital waveform generator is the storer of individual many bits, the test channel of different chips is linked to the different bits of digital waveform generator.
5. by calling SQPG pattern (sequence pattern generator test vector) the write order form of the storage unit of the data based chip in the digital waveform generator is written in the storage unit of each corresponding chip to be measured again.
The present invention at first needs the user downloaded files to be put in the hard disk of tester, by programmed control this file is read in certain array then, to be used for the digital waveform generator of simulation test in the tester then as an intermediate store, data in the array are deposited in the digital waveform generator, again by the code data in the SQPG pattern call number waveform generator and write in the storage unit of chip to be measured.
When this patent is measured simultaneously at the multicore sheet, require all different situation of user code data that writes in each chip.When carrying out the data download, to need data downloaded to store into earlier in the digital waveform generator of tester, by the link (link) of digital waveform generator with different chip testing passages, call SQPG pattern with link to resource in these code datas write in the storage unit of specifying chip, different chips has different data in the time of guaranteeing same survey.A large amount of different user code data to customer requirements can be accomplished to download fast at each chip, and saves the test duration.
Data when the method that the user code data are downloaded during to a plurality of chip testing of the present invention is mainly used in the multicore sheet with test are downloaded, and can allow tester faster the storage unit in the chip be write arbitrary data by the uniqueness utilization to the tester simulation test unit hardware.The present invention will need data downloaded to be read in the digital waveform generator of tester as array file earlier, after this each data write as long as directly call from digital waveform generator, read a secondary data and the form that takes a turn for the better at every turn when promptly only need pack wafer (wafer) into and deposit in the digital waveform generator and get final product, can make test convenient quick.The download of different user code data in the time of can solving the multicore sheet and test simultaneously by method of the present invention, and save the test duration.
Claims (3)
1. user code method for down loading in a chip when tester is to a plurality of chip testing, tester comprises unit of testing and controlling, hard disk, sequence pattern generator, digital waveform generator, it is characterized in that, may further comprise the steps:
(1). set up the data file number of the user code of corresponding each piece chip of array;
(2). read array, which data file decision calls;
(3). convert described data file to 2 system forms and deposit in the digital waveform generator;
(4). the setting digital waveform generator links with a plurality of chip testing passages, and described digital waveform generator is the storer of many bits, the test channel of different chips is linked to the different bits of digital waveform generator;
(5). be written in the storage unit of each corresponding chip to be measured by the write order form of calling sequence graph generator testing vector the storage unit of the data based chip in the digital waveform generator.
2. tester according to claim 1 user code method for down loading in the chip during to a plurality of chip testing is characterized in that, sets up an array in the storer of the unit of testing and controlling of tester.
3. tester according to claim 1 user code method for down loading in the chip during to a plurality of chip testing is characterized in that the user code data file of each piece chip is stored in the hard disk of tester.
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| Application Number | Priority Date | Filing Date | Title |
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| CN2007100944130A CN101458294B (en) | 2007-12-10 | 2007-12-10 | Method for downloading user code in chip when multi-chip test by tester |
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| CN2007100944130A CN101458294B (en) | 2007-12-10 | 2007-12-10 | Method for downloading user code in chip when multi-chip test by tester |
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| CN101458294A CN101458294A (en) | 2009-06-17 |
| CN101458294B true CN101458294B (en) | 2011-05-04 |
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| CN104347120B (en) * | 2013-08-07 | 2017-06-06 | 上海华虹宏力半导体制造有限公司 | Realize that memory test instrument improves the method with number is surveyed |
| CN114646867B (en) * | 2022-05-18 | 2022-10-28 | 南京宏泰半导体科技有限公司 | Integrated circuit concurrent testing device and method |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1979200A (en) * | 2005-12-08 | 2007-06-13 | 上海华虹Nec电子有限公司 | Method for parallelly detecting multiple chips of synchronous communication |
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Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1979200A (en) * | 2005-12-08 | 2007-06-13 | 上海华虹Nec电子有限公司 | Method for parallelly detecting multiple chips of synchronous communication |
Non-Patent Citations (3)
| Title |
|---|
| JP平1-180471A 1989.07.18 |
| JP昭63-73636A 1988.04.04 |
| JP特开平10-73637A 1998.03.17 |
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Owner name: SHANGHAI HUAHONG GRACE SEMICONDUCTOR MANUFACTURING Free format text: FORMER OWNER: HUAHONG NEC ELECTRONICS CO LTD, SHANGHAI Effective date: 20131218 |
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Effective date of registration: 20131218 Address after: 201203 Shanghai city Zuchongzhi road Pudong New Area Zhangjiang hi tech Park No. 1399 Patentee after: Shanghai Huahong Grace Semiconductor Manufacturing Corporation Address before: 201206, Shanghai, Pudong New Area, Sichuan Road, No. 1188 Bridge Patentee before: Shanghai Huahong NEC Electronics Co., Ltd. |