CN101452303A

CN101452303A - Method for preventing over-fast electrification and circuit thereof

Info

Publication number: CN101452303A
Application number: CNA2007101716095A
Authority: CN
Inventors: 俞大立; 程惠娟; 崔杰; 李怀兆
Original assignee: Semiconductor Manufacturing International Shanghai Corp
Current assignee: Semiconductor Manufacturing International Shanghai Corp
Priority date: 2007-11-30
Filing date: 2007-11-30
Publication date: 2009-06-10
Anticipated expiration: 2027-11-30
Also published as: CN101452303B

Abstract

The invention relates to a circuit for solving too quick electrification, which comprises a band gap reference source, an amplifier, a PMOS tube, input voltage, output voltage, a voltage divider, a lifting transistor and a PUDC circuit, wherein the band gap reference source is connected with the amplifier; one end of the amplifier is connected with the PMOS tube, and the other end of the amplifier is connected with the voltage divider; one end of the lifting transistor is connected between the amplifier and the PMOS tube, and the other end of the lifting transistor is connected with the input voltage; one end of the PMOS tube is connected with the input voltage, and the other end of the PMOS tube is connected with the voltage divider; and the output voltage is connected with the middle of the PMOS tube and the voltage divider. The output voltage of the circuit is more stable, and the circuit can ensure safety of a chip.

Description

A kind of solution power on too fast method and circuit thereof

Technical field

The present invention relates to the fast powering-up field, relate in particular to a kind of solution too fast Method and circuits that powers on.

Background technology

In hot-swap system, all utilize voltage stabilizer to solve the too fast voltage fluctuation that brings that powers on, adjust output voltage, make it stable as much as possible, but its effect is often very undesirable.

With the most frequently used voltage stabilizer is example, in the circuit module as shown in Figure 2, if it is too fast that input voltage rises, and band gap reference and amplifier also are not in normal duty, the door of PMOS pipe this moment (P raceway groove isolated gate FET) is in a unsure state, output voltage is also unstable accordingly, even the door of PMOS pipe can be in the state of " 0 ", this moment, the PMOS pipe was equivalent to disconnect, output voltage will produce a very big spike, cause chip by permanent damage, the synoptic diagram of its input voltage and output voltage as shown in Figure 1.

Under the common situation, we can increase electric capacity and resistance between the power supply of this circuit and input voltage, solve the problems referred to above, and as shown in Figure 3, the circuit that utilizes resistance and electric capacity to form makes output suitably postpone.But clearly, when on this circuit, increasing a little resistance, when powering on when too fast, because the voltage pole instability is so electric current is also very unstable in the circuit, when big electric current passes through, easily resistance is burnt out, entire circuit will be scrapped so, increases extra element equally, can cause cost to increase.

Summary of the invention

The present invention is in order to make output voltage more stable, and guarantees from power on to be output as 0 in the stable process of power supply, and a kind of solution of knowing clearly power on too fast method and circuit are provided.

A kind of solution too fast circuit that powers on comprises band gap reference, amplifier, PMOS pipe, input voltage, output voltage and voltage divider, comprises also promoting transistor and PUDC circuit that wherein band gap reference is connected with amplifier; One end of amplifier connects the PMOS pipe, and the other end is connected with voltage divider; Can promote a transistorized end and be connected between amplifier and the PMOS pipe, the other end is connected with input voltage; One end of PMOS pipe is connected with input voltage, and the other end is connected with voltage divider; Output voltage is connected the centre of PMOS pipe and voltage divider.

Wherein the PUDC circuit is to constitute the loop with resistance and capacitances in series after three transistor parallel connections, utilize the self-characteristic of resistance and electric capacity to produce the PUDC signal, the delay of realization system can promote transistor controls the PMOS pipe under the control of PUDC signal disconnection and be connected.

A kind of this circuit that utilizes solves the too fast method that powers on, and may further comprise the steps:

1, in the process that input voltage rises, because the delay of PUDC signal self, this moment, the voltage of PUDC signal output still was 0, make that the transistor gate input voltage is 0, this moment, transistor was drawn high, be in connection status, then Dui Ying PMOS pipe is in normal duty, and this moment, the output voltage of entire circuit was approximately 0;

2, when output voltage tends towards stability, this moment, the PUDC signal was a high level, and the transistor that promote this moment is disconnected, and corresponding PMOS pipe is in the state that is forced closed, and entire circuit is output as normal value.

The present invention makes it compared with prior art owing to adopted said method, has the following advantages and good effect:

1, the present invention has adopted the PUDC circuit, can realize effective delay, guarantees the stable output of input voltage;

2, the present invention has increased by one and can promote transistor, under the effect of PUDC signal, realizes the control to the PMOS pipe.

Description of drawings

Fig. 1 is input voltage and output voltage synoptic diagram in the hot-swap system before improving;

Fig. 2 is the voltage stabilizer work synoptic diagram of hot-swap system before improving;

Fig. 3 is delay circuit figure commonly used;

Fig. 4 is the voltage regulator circuit figure after improving;

Fig. 5 is the PUDC signal circuit diagram;

Fig. 6 is for improving input voltage, PUDC signal and the output voltage synoptic diagram of back voltage stabilizer.

Embodiment

The invention provides a kind of solution powered on fast-circuit and method, with the voltage stabilizer is example, but the invention is not restricted to voltage stabilizer, as shown in Figure 4, comprise band gap reference, amplifier, PMOS pipe, input voltage, output voltage and voltage divider, also comprise promoting transistor and PUDC circuit, wherein band gap reference is connected with amplifier; One end of amplifier connects the PMOS pipe, and the other end is connected with voltage divider; Can promote a transistorized end and be connected between amplifier and the PMOS pipe, the other end is connected with input voltage; One end of PMOS pipe is connected with input voltage, and the other end is connected with voltage divider; Output voltage is connected the centre of PMOS pipe and voltage divider.

This voltage stabilizer mainly utilizes PUDC (Power-up Detect Circuit, circuit for detecting powers on) signal to come connection and the disconnection of oxide-semiconductor control transistors M1, thereby realizes the pipe to control PMOS, and then realizes that its concrete method step is to the control of output:

1, in the process that input voltage rises, because the delay of PUDC signal self, this moment, the voltage of PUDC signal output still was 0, make that transistor M1 grid voltage is 0, transistor is in the state that is drawn high, and this moment, transistor M1 disconnected, and then the grid voltage of Dui Ying PMOS pipe is greater than its threshold voltage, then the PMOS pipe is in normal duty, guarantees that the output voltage of entire circuit is approximately 0;

2, when output voltage tends towards stability gradually, the PUDC circuit is output as high level, the grid voltage of M1 is greater than its threshold voltage at this moment, transistor M1 is in the state of operate as normal, then the grid voltage of Dui Ying PMOS pipe is less than threshold voltage, the PMOS pipe is in the state of disconnection, and entire circuit is output as normal value.

The circuit that wherein produces the PUDC signal as shown in Figure 5, constitute the loop with resistance and capacitances in series after three transistor parallel connections, it is exactly the delay that utilizes itself characteristic of resistance and electric capacity to produce in essence, control the output of PUDC signal, the time of the output delay that it is concrete, can design according to different chips, different chips its time delay that needs is different, and the numerical value that only need to adjust resistance R and capacitor C this moment just can be realized.

In the fast powering-up process, when input voltage when zero arrives stationary value, often have bigger fluctuation, then Dui Ying output voltage often also has bigger fluctuation from zero before the stationary value, sometimes even can produce a very big peak current, if directly provide output voltage to chip, the risk that can have defective chip is so must guarantee that it is " 0 " that voltage stabilizer is output as before input voltage arrival is stable.Because the lag characteristic of transmission system self, after input voltage arrived stationary value, output voltage also can tend towards stability after a less delay, and could export to chip this moment with stable voltage.

As shown in Figure 6, the PUDC signal has a delay with respect to input voltage, promptly at input voltage when 0 rises to stationary value, the PUDC voltage of signals under the effect that self postpones, a suitable delay after just from 0 arrival stationary value; And guarantee in the process that input voltage rises, to be output as 0, output voltage also has the delay of a start-up time with respect to the PUDC signal, ensures that when output stablize voltage stabilizer ability output voltage is protected chip.

Use this voltage stabilizer can guarantee the stable of output voltage, what energy was stable provides input voltage to chip, the protection chip.

The voltage stabilizer of being mentioned in the present embodiment is a power on specific embodiment of too fast method and circuit of a kind of solution of the present invention; invention which is intended to be protected is not limited to voltage stabilizer, and all can solve and power on too fast circuit and method thereof all within the scope of the invention.

Claims

1, a kind of solution too fast circuit that powers on, comprise band gap reference, amplifier, PMOS pipe, input voltage, output voltage and voltage divider, it is characterized in that this voltage stabilizer also comprises can promote transistor and PUDC circuit, and wherein band gap reference is connected with amplifier; One end of amplifier connects the PMOS pipe, and the other end is connected with voltage divider; Can promote a transistorized end and be connected between amplifier and the PMOS pipe, the other end is connected with input voltage; One end of PMOS pipe is connected with input voltage, and the other end is connected with voltage divider; Output voltage is connected the centre of PMOS pipe and voltage divider.

2, a kind of solution as claimed in claim 1 too fast circuit that powers on, it is characterized in that described PUDC circuit is to constitute the loop with resistance and capacitances in series after three transistor parallel connections, utilize the self-characteristic of resistance and electric capacity to produce the PUDC signal, realize the delay of system.

3, a kind of solution as claimed in claim 1 too fast circuit that powers on is characterized in that describedly promoting transistor controls the PMOS pipe under the control of PUDC signal disconnection and being connected.

4, a kind of described solution of claim 1 too fast circuit that powers on that utilizes solves the too fast method that powers on, and it is characterized in that this method comprises:

1), in the process that input voltage rises, because the delay of PUDC signal self, this moment, the voltage of PUDC signal output still was 0, make that the transistor gate input voltage is 0, this moment, transistor was drawn high, be in connection status, then Dui Ying PMOS pipe is in normal duty, and this moment, the output voltage of entire circuit was approximately 0;

2), when output voltage tends towards stability, this moment, the PUDC signal was a high level, the transistor that promote this moment is disconnected, and the PMOS pipe is in the state that is forced closed, entire circuit is output as normal value.