CN101452166B - Lcd - Google Patents

Abstract

The present invention provides a liquid crystal display. According to the invention, a pixel is divided into two sub-pixels. Each sub-pixel comprises a thin film transistor, a liquid crystal capacitorand a storing capacitor. Furthermore at least one storing capacitor therein adopts a variable capacitor, wherein, the variable capacitor comprises a first conductive layer, an insulating layer, a semiconductor layer with area of Asem and a second conductive layer. The second conductive layer is provided with a first area with area of Acon. The first area is superposed with the semiconductor layer, and furthermore the following relationship is satisfied: Acon<Asem.

Description

LCD

Technical field

The present invention relates to a kind of LCD, particularly a kind of LCD and the pixel cell that can promote the wide viewing angle quality.

Background technology

LCD has been widely used in various electronic products, for example: computer screen or TV or the like.For wide viewing angle is provided, company of Fujitsu (Fujitsu) proposed a kind of multiregional vertical align (Multi-Domain Vertical Alignment, MVA) technology in 1997.The MVA technology can obtain the visual angle of 160 degree, and high contrast and the outstanding performance of response fast can be provided.Yet the MVA technology has a great shortcoming, promptly is skin color, especially the Asian's skin color to the people when when stravismus, can produce colour cast (color shift) phenomenon of color desalination.

Fig. 1 shows the gray scale voltage of the display panel that uses the MVA technology and the graph of a relation of transmissivity, and wherein transverse axis is represented gray scale voltage, and unit is a volt (V), and the longitudinal axis is represented transmissivity (transmittance).When human eye was faced this LCD, the relation curve of its transmissivity and voltage was that when the gray scale voltage that is applied increased, its transmissivity changed thereupon with dotted line 101 expressions.Look side ways this LCD and work as human eye with an angle of inclination, the relation curve of its transmissivity and voltage is with dotted line 102 expressions, increase the also change thereupon of its transmissivity though apply voltage, but in zone 100, the variation of its transmissivity does not increase along with the increase that applies voltage, and this is the main cause that causes colour cast.

Solution to the problems described above traditionally is to compensate the transmissivity when looking side ways and the relation curve of gray scale voltage by form two groups of sub-pixels that can produce different transmissivities and gray scale voltage relation curve in pixel.Consult shown in Figure 2ly, dotted line 201 wherein is the transmissivity and the relation curve of gray scale voltage originally, and another dotted line 202 then is the transmissivity that another sub-pixel produced in the same pixel and the relation curve of gray scale voltage.By a dotted line 201 with the mixing of dotted line 202 optical characteristics between the two, can obtain to a more level and smooth transmissivity and the relation curve of gray scale voltage, shown in the solid line among Fig. 2 203.

Yet above-mentioned by form the method that a plurality of sub-pixels come the compensate for optical characteristic in pixel cell, the phenomenon of image residue takes place in regular meeting in consecutive frame.This is because each pixel has a plurality of sub-pixels, and each sub-pixel is in the moment that corresponding thin film transistor (TFT) cuts out, and its stored data voltage can produce change in voltage in various degree, compensates transmissivity and gray scale voltage relation curve thus.But, this change in voltage in various degree can make the data voltage of each sub-pixel in the pixel, when corresponding identical common electric voltage, can produce different data voltage sizes at adjacent two frames, thereby cause the problem of image residue (image sticking).

Therefore, how in a pixel, produce two sub-pixels, and do not have between image residue and inscribe, promptly become the target that the present invention pursues.

Summary of the invention

The invention provides a kind of LCD, wherein, a pixel cell is separated into two sub-pixels, and each sub-pixel comprises: thin film transistor (TFT) is disposed on the substrate; Liquid crystal capacitance is disposed on the described substrate; And storage capacitors.Wherein, at least one described storage capacitors adopts variable capacitance, and described variable capacitance is A by first conductive layer, insulation course, area in regular turn _SemThe semiconductor layer and second conductive layer stack on described substrate and form, and described variable capacitance is coupled to described thin film transistor (TFT).Wherein, to have area be A to described second conductive layer _ConThe first area, described first area and described semiconductor layer overlap, and A _Con＜A _Sem

The present invention also provides a kind of described operation of LCD method, comprises: apply first voltage on described first conductive layer; Apply second voltage on described second conductive layer; And, determine the capacitance of described electric capacity according to the relation of described first voltage, described second voltage and critical voltage.

Description of drawings

Fig. 1 is the penetrance-voltage curve of homeotropic alignment nematic colour liquid crystal display device;

Fig. 2 is the penetrance-voltage curve that comprises the homeotropic alignment nematic colour liquid crystal display device of two sub-pixels;

Fig. 3 A is depicted as the diagrammatic cross-section of metal-insulator semiconductor (MIS) electric capacity according to the embodiment of the invention;

Fig. 3 B is depicted as according to the sectional view of the MIS electric capacity of Fig. 3 A and the corresponding relation between its vertical view;

Fig. 3 C is depicted as according to the sectional view of the MIS electric capacity of Fig. 3 A and another corresponding relation between its vertical view;

Fig. 3 D is depicted as the end face synoptic diagram according to the MIS electric capacity of Fig. 3 A;

Fig. 3 E is depicted as another end face synoptic diagram according to the MIS electric capacity of Fig. 3 A; And

Fig. 4 is according to pixel cell schematic diagram of the present invention.

[main element symbol description]

100 regional 306 sweep traces

101,102,201 and 202 dotted lines, 308 data lines

203 solid lines, 401 first conductive layers

300 pixel cells, 401 insulation courses

3021 and 3041 thin film transistor (TFT)s, 402 second conductive layers

3022 and 3042 pixel electrodes, 4021 first areas

3023 and 3043 storage capacitors, 4022 second areas

3024 and 3044 liquid crystal capacitance 402a firsts

3025 and 3045 stray capacitance 402b second portions

302 and 304 sub-pixels, 404 semiconductor layers

405 high doping semiconductor layer d _InsThe thickness of insulation course

A _ConThe area d of first area _SemThe thickness of semiconductor layer

A _SemThe area V of semiconductor layer _BiasBias voltage

d ₁First apart from V _ComCommon electrode

d ₂Second distance

Embodiment

Under the situation that does not limit spirit of the present invention and range of application, below promptly introduce enforcement of the present invention with a plurality of embodiment; Those skilled in the art should be applied to liquid crystal display device structure of the present invention in the various LCD after understanding spirit of the present invention.

Consult Fig. 3 A and be depicted as the capacitance structure diagrammatic cross-section of metal-insulator semiconductor-metal (MIS).402 of first conductive layer 401 and second conductive layers, accompany insulation course 403 and semiconductor layer 404, high doping semiconductor layer 405, wherein semiconductor layer 404 can be amorphous silicon layer, and 405 on high doping semiconductor layer can be N type doped amorphous silicon layer.It is that with the difference of general electric capacity its capacitance is not constant, and usually and be applied to the voltage difference (V of 402 of first conductive layer 401 and second conductive layers _M1-V _M2) relevant, therefore be also referred to as Control of Voltage electric capacity.In addition, MIS capacitance structure in the present embodiment, the area of its first conductive layer 401 is greater than the area of semiconductor layer 404, the area of second conductive layer 402 is equivalent to the area of high doping semiconductor layer 405, the area that first conductive layer 401, second conductive layer 402, insulation course 403 and semiconductor layer are 404 is then differing from each other, can increase the variation range of MIS capacitance C thus, and then obtain preferable color bias improvement effect.In addition, those skilled in the art still can be according to the actual requirements, adjusts the relation between the area of the area of first conductive layer 401 and semiconductor layer 404, such as: the area of first conductive layer 401 is less than the area of semiconductor layer 404.

Fig. 3 B is depicted as the sectional view of MIS electric capacity of Fig. 3 A and the corresponding relation between its vertical view.Wherein, as the voltage (V that puts on first conductive layer 401 _M1), greater than the voltage (V that puts on second conductive layer 402 _M2) and a critical voltage (V _Th) during sum, can improve the conducting state of second conductive layer 402 and semiconductor layer 404, make semiconductor layer 404 be the ON state, thereby as the electrode of MIS electric capacity.Therefore, interelectrode distance is the thickness of insulating layer d between first conductive layer 401 and the semiconductor layer 404 _Ins, the area of MIS electric capacity is then by the area A of semiconductor layer 404 _SemDetermine its capacitance C _OnFor:

$C_{\mathrm{on}}={\mathrm{\&epsiv;}}_{\mathrm{ins}}\frac{A_{\mathrm{sem}}}{d_{\mathrm{ins}}}$

Wherein, ε _InsSpecific inductive capacity for insulation course 403.

Fig. 3 C is depicted as the sectional view of MIS electric capacity and the corresponding relation between its vertical view.Wherein, second conductive layer 402 has first area 4021 and second area 4022, and first area 4021 overlaps with semiconductor layer 404, and 4022 of second areas do not overlap with semiconductor layer 404.As the voltage (V that puts on first conductive layer 401 _M1), less than the voltage (V that puts on second conductive layer 402 _M2) and critical voltage (V _Th) during sum, can reduce the conducting state of second conductive layer 402 and semiconductor layer 404, make semiconductor layer 404 be the OFF state.Therefore, the electrode of MIS electric capacity changes second conductive layer 402 and high doping semiconductor layer 405 into, and interelectrode distance then is the spacing of first conductive layer 401 and high doping semiconductor layer 405, i.e. thickness of insulating layer d _IsWith the semiconductor layer thickness d _SemSum, and the area of MIS electric capacity is by the area A of first area 4021 _ConDetermine its capacitance C _OffFor:

Wherein, ε _SemBe the specific inductive capacity of semiconductor layer 404, and A _SemGreater than A _Con

In other words, MIS capacitance structure of the present invention is according to putting on first conductive layer 401, the voltage of second conductive layer 402 and the relation of critical voltage, change the useful area and the distance of MIS capacitance structure, with the capacitance of definition MIS electric capacity, and the variation range of scalable capacitance C is as follows;

C _Off≤ C≤C _On, promptly

Fig. 3 D is depicted as the vertical view of MIS electric capacity according to one embodiment of present invention, first conductive layer 401, second conductive layer 402 and semiconductor layer 404 shown in it, second conductive layer 402 is positioned on the semiconductor layer 404, wherein, second conductive layer 402 has first edge, semiconductor layer 404 has second edge, and first edge is adjacent with second edge, and has first apart from d ₁Wherein, when semiconductor layer 404 was made of amorphous silicon layer, preferred design parameter was d ₁≤ 10 μ m; Only when this semiconductor layer 404 is monocrystalline silicon layer or polysilicon layer, this is first apart from d ₁Might be greater than 10 μ m.

According to another embodiment of the present invention, second conductive layer 402 also can be connected to form by 402a of first and second portion 402b, shown in Fig. 3 E.Wherein, 402a of first and second portion 402b and semiconductor layer 404 overlap part area and, area less than semiconductor layer 404, and 402a of first and second portion 402b are electrically connected to each other, and lay respectively at both sides on the semiconductor layer 404, promptly 402a of first and second portion 402b are at a distance of second distance d ₂, and d ₂≤ 20 μ m.According to the structure of present embodiment, owing to use the cause of 402a of first and second portion 402b, so in operating process, but the speed reversal of accelerated semiconductor layer 404, that is the switch speed of accelerated semiconductor layer 404 between ON state and OFF state.

Consult Fig. 4, it is pixel cell schematic diagram according to an embodiment of the invention.Pixel cell 300 comprises two sub-pixels 302 and 304.

Wherein sub-pixel 302 comprises thin film transistor (TFT) 3021, and its grid is connected in sweep trace 306, and drain electrode is connected in data line 308, and source electrode then is connected in pixel electrode 3022, wherein pixel electrode 3022 and bias voltage V _BiasConstitute storage capacitors 3023, pixel electrode 3022 and common electrode V _ComConstitute liquid crystal capacitance 3024.Then has stray capacitance 3025 between the source electrode of thin film transistor (TFT) 3021 and the grid.And sub-pixel 304 comprises thin film transistor (TFT) 3041, and its grid is connected in sweep trace 306, and drain electrode is connected in data line 308, and source electrode then is connected in pixel electrode 3042, wherein pixel electrode 3042 and bias voltage V _BiasConstitute storage capacitors 3043, pixel electrode 3042 and common electrode V _ComConstitute liquid crystal capacitance 3044.Then has stray capacitance 3045 between the source electrode of thin film transistor (TFT) 3041 and the grid.In the present embodiment, storage capacitors 3023 adopts the capacitance structure of metal-insulator semiconductor-metal, promptly so-called MIS capacitance structure, and storage capacitors 3043 then adopts the capacitance structure of metal-insulator-metal type, promptly so-called mim capacitor structure.Right in other embodiment, storage capacitors 3043 also can be the MIS capacitance structure.

In addition, according to Fig. 4 embodiment, the structure of storage capacitors 3023 can be the MIS capacitance structure shown in Fig. 3 D or Fig. 3 E.Below only explain in conjunction with Fig. 4 and Fig. 3 D, surplus person repeats no more.First conductive layer 401 of storage capacitors 3023 is to couple via the source electrode of through hole (through hole) with thin film transistor (TFT) 3021, and second conductive layer 402 of storage capacitors 3023 is via another through hole and bias voltage V _BiasCouple.Yet those skilled in the art still can make first conductive layer 401 and bias voltage V of storage capacitors 3023 according to the actual requirements _BiasCouple, second conductive layer of storage capacitors 3023 then couples with the source electrode of thin film transistor (TFT) 3021.

In addition, according to the present invention, can be unequal by the area that makes pixel electrode 3022,3042 among Fig. 4, improve colour cast.

Comprehensive above-mentioned institute says, the present invention is by being divided into two sub-pixels with a pixel unit area, and comprise thin film transistor (TFT), liquid crystal capacitance and storage capacitors in each sub-pixel, and wherein at least one storage capacitors adopts variable capacitance, change the structure of variable capacitance thus, can amplify the capacitance scope of variable capacitance, and then improve the image quality of display device.

Though disclose the present invention by a plurality of embodiment; so be not to be to be used to limit the present invention; those skilled in the art are not or not under the situation that does not break away from the spirit and scope of the present invention; can make various changes and retouching, so protection scope of the present invention should be as the criterion with subsidiary claim.

Claims (10)

1. LCD, wherein, a pixel cell is separated into two sub-pixels, and each sub-pixel comprises:

Thin film transistor (TFT) is disposed on the substrate;

Liquid crystal capacitance is disposed on the described substrate; And

Storage capacitors,

Wherein, at least one described storage capacitors adopts variable capacitance, and described variable capacitance is A by first conductive layer, insulation course, area in regular turn _ScmThe semiconductor layer and second conductive layer stack on described substrate and form, and described variable capacitance is coupled to described thin film transistor (TFT);

Wherein, to have area be A to described second conductive layer _ConThe first area, described first area and described semiconductor layer overlap, and A _Con＜A _Sem

2. LCD as claimed in claim 1, wherein:

The area A of described semiconductor layer _SemArea less than described first conductive layer;

The specific inductive capacity of described insulation course is ε _Ins, thickness is d _Ins

The specific inductive capacity of described semiconductor layer is ε _Sem, thickness is d _SemAnd

The capacitance of described electric capacity is C, and

3. LCD as claimed in claim 1 also comprises the high doping semiconductor layer, is disposed between described second conductive layer and the described semiconductor layer, and wherein, described second conductive layer overlaps with described high doping semiconductor layer.

4. LCD as claimed in claim 1, wherein, described second conductive layer has first edge, described semiconductor layer has second edge, described first edge is adjacent to described second edge, and described first edge and described second edge at a distance of first apart from d ₁, and d ₁≤ 10 μ m.

5. LCD as claimed in claim 1, wherein, described second conductive layer has first and second portion, and described first and described second portion are at a distance of second distance d ₂, and d ₂≤ 20 μ m.

6. LCD as claimed in claim 5, wherein, described first and described second portion electrically connect.

7. operation of LCD method as claimed in claim 1 comprises:

Apply first voltage on described first conductive layer;

Apply second voltage on described second conductive layer; And

According to the relation of described first voltage, described second voltage and critical voltage, determine the capacitance of described electric capacity.

8. operation of LCD method as claimed in claim 7, wherein:

The specific inductive capacity of described insulation course is ε _Ins, thickness is d _InsAnd

The specific inductive capacity of described semiconductor layer is ε _Sem, thickness is d _Sem

9. operation of LCD method as claimed in claim 8 also comprises:

Adjust described first voltage and described second voltage, make described first voltage greater than described second voltage and described critical voltage sum; And

Improve the conducting state of described second conductive layer and described semiconductor layer,

Wherein, the capacitance of described electric capacity is C _On, and

10. operation of LCD method as claimed in claim 8 also comprises:

Adjust described first voltage and described second voltage, make described first voltage less than described second voltage and described critical voltage sum; And

Reduce the conducting state of described second conductive layer and described semiconductor layer, wherein, the capacitance of described electric capacity is C _Off, and

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