CN101452019A - Clocking frequency comparing unit and method - Google Patents
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- CN101452019A CN101452019A CNA2007101967055A CN200710196705A CN101452019A CN 101452019 A CN101452019 A CN 101452019A CN A2007101967055 A CNA2007101967055 A CN A2007101967055A CN 200710196705 A CN200710196705 A CN 200710196705A CN 101452019 A CN101452019 A CN 101452019A
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Abstract
The invention relates to a clock frequency comparing element, comprising a first counter, a second counter, a comparator, and a third counter, wherein the first counter and the second counter start counting using a first clock frequency and a second clock frequency when receiving a control signal. The comparator outputs an enabling signal when one of the first counter and the second counter counts till given times, and stops outputting the enabling signal when both the first counter and the second counter count till the given times. The third counter starts counting in the first clock frequency when receiving the enabling signal, and stops counting when the enabling signal stops. The inventive clock frequency comparing element and the method can be used for compare two clock frequencies in reasonable short time to output frequency errors.
Description
Technical field
The present invention is about a kind of clocking frequency comparing unit, particularly test voltage-controlled quartz (controlled) oscillator (voltage controlled crystal oscillator, whether clock frequency VCXO) standard compliant clocking frequency comparing unit and method of testing about a kind of.
Background technology
Voltage-controlled quartz (controlled) oscillator is the clock signal generator with high accurancy and precision and high stability, be widely used in all kinds of oscillatory circuits such as color TV, counter, telepilot, and be used as frequency generator in the communication system, or be the digital processing unit clocking, and provide reference signal for particular system.
Voltage-controlled quartz (controlled) oscillator utilizes the piezoelectric effect of quartz crystal and produces the clock signal of different clock frequencies.Generally speaking, voltage-controlled quartz (controlled) oscillator with the frequency offset (frequencydeviation) of control change in voltage be about the quartz crystal resonant frequency tens of to millions of/one times, that is tens of to hundreds of PPM (parts per million).For example, if the quartz crystal resonant frequency is 27 megahertzes, and the frequency offset specification of voltage-controlled quartz (controlled) oscillator be+/-120PPM, then the oscillation frequency of quartz crystal is to be offset with+/-3240 hertz frequency interval working frequency.(digitally-controlled crystal oscillator then is to utilize digital signal to produce corresponding different frequency offsets DCXO) to digital voltage-controlled quartz (controlled) oscillator, produces different clock frequencies with the piezoelectric effect of control quartz crystal.
Along with system increases the frequency offset precision and the resolution requirement of voltage-controlled quartz (controlled) oscillator, in be built in voltage-controlled quartz (controlled) oscillator in the chip and just be not suitable for the test of board volume production, because except the external spectrum analyzer of need, the measurement that finish a frequency more needs the several seconds consuming time.For example, the resonant frequency of quartz crystal is 27 megahertzes (27MHz), and promptly the frequency offset of every PPM is 27 hertz, if spectrum analyzer analysis bandwidth (resolution bandwidth, RBW) be 3 hertz, when then every measurement one class frequency side-play amount costs six to seven seconds.Therefore, can be used for the test of board volume production in order to make voltage-controlled quartz (controlled) oscillator chip, (built-in self-test, BIST) circuit has its necessity to an effective built-in self-test.
Yet technology there is no the circuit engineering in response to above-mentioned reason now, only No. 6965224 (applying date: on May 16th, 2003) have the metering circuit of pair frequency error or frequency offset to have mentioned of United States Patent (USP).This patent proposes a kind ofly to measure the tool correlativity but the circuit of frequency error and frequency offset between the clock of different frequency, as shown in Figure 1.Counter 102 is the counter of a modulus-80 (modulo 80), and Ref_in counts with clock signal, and flip-flop (flip flop) 104 and 106 carries out in order to output and the clock signal clk _ 32M with counter 102 synchronously.Flip-flop 108 and constitute a forward edge (positive edge) detecting devices with door (and gate) 110, when detecting a forward edge, remove the content of working storage 114, the value of establishing counter 104 of laying equal stress on is 0 x 80, and working storage 114 output valves of this moment can be represented the frequency offset of clock signal clk _ 32M and Ref_in.
Summary of the invention
In view of above problem, the present invention proposes a kind of clocking frequency comparing unit and method.
The invention provides a kind of clocking frequency comparing unit, comprise one first counter, one second counter, a comparer, and one the 3rd counter.First counter is in order to receive one first clock signal of a control signal and tool one first clock frequency.Second counter is in order to receive a second clock signal of control signal and tool one second clock frequency.Comparer receives the count value of above-mentioned first and second counters, to produce activation signal output.The 3rd counter begins counting with first clock frequency in order to receive the enable signal and first clock signal when receiving enable signal.When first counter and second counter receive above-mentioned control signal simultaneously, begin counting with above-mentioned first clock frequency and above-mentioned second clock frequency respectively.When first counter and second counter wherein one when counting up to a set number of times, above-mentioned comparer export above-mentioned enable signal to above-mentioned the 3rd counter to begin counting.When above-mentioned both when all counting up to above-mentioned set number of times, above-mentioned comparer stops to export above-mentioned enable signal to stop the 3rd rolling counters forward.
The present invention also provides a kind of integrated circuit (IC) chip, comprises an oscillator and a clocking frequency comparing unit.Above-mentioned oscillator is in order to export one first clock signal.Above-mentioned clocking frequency comparing unit is in order to receive a control signal, above-mentioned first clock signal and a second clock signal,, and export one and judge that signal points out whether one first clock frequency of above-mentioned first clock signal meets an error range with relatively this first clock signal and this second clock signal according to above-mentioned control signal.
The present invention more provides a kind of clock frequency comparison method.The count value of initialization one first counter, one second counter and one the 3rd counter at first; First counter and this second counter begin counting to one first clock signal and a second clock signal that receives separately simultaneously; When first and second counters, one count value wherein equals a set value, above-mentioned the 3rd counter is begun counting to first clock signal; And when the count value of first and second counters all equals set value, stop the 3rd counter and export the count value of the 3rd counter.
A purpose of the present invention is to provide a kind of clocking frequency comparing unit and method, can compare two clock frequencies in the rational short time and exports its frequency error value.Above-mentioned clocking frequency comparing unit can in be built in the integrated circuit (IC) chip, in order to the frequency offset of an oscillator in the test said integrated circuit chip.
Description of drawings
Fig. 1 is the circuit diagram of a clock frequency error comparator circuit in the prior art;
Fig. 2 represents the synoptic diagram of one embodiment of the invention clocking frequency comparing unit;
Fig. 3 represents that clocking frequency comparing unit of the present invention is applied to the synoptic diagram in the chip; And
Fig. 4 represents the process flow diagram of clocking frequency comparing unit one method of testing of the present invention.
Drawing reference numeral:
110 with the door
114 working storages
200 clocking frequency comparing units
208 comparers
210 decision circuitry
304 clocking frequency comparing units
302 voltages/numerically-controlled oscillator
306 controllers
312 test circuits
308,310 bond pads
104,106,108 flip-flops
102,112,202,204,206 counters
Embodiment
Please refer to Fig. 2, Fig. 2 is that one embodiment of the invention one clock frequency ratio is than schematic representation of apparatus.Clocking frequency comparing unit 200 can compare the frequency difference of two input clock signals; Clocking frequency comparing unit 200 comprises first counter 202, second counter 204, the 3rd counter 206, comparer 208 and decision circuitry 210.
Wherein, first counter 202 can receive one first clock signal clk _ 1 and a control signal CS, and when receiving control signal CS, first counter 202 just begins counting with the clock frequency of first clock signal clk _ 1; Second counter 204 can receive a second clock signal CLK_2 and control signal CS, and when receiving control signal CS, second counter 204 just begins counting with the clock frequency of second clock signal CLK_2.
Comparer 208 can be a digital comparator, receive signal simultaneously from first counter 202 and second counter 204, result after will comparing again is sent to the 3rd comparer 206, the three counters 206 and according to the data that comparer 208 is transmitted a counting is made in first clock signal clk _ 1; And decision circuitry 210 can be a DLC (digital logic circuit), receives from the signal of the 3rd counter 206 to judge signal to export one.
In one embodiment, first counter 202 and second counter 204 count from zero simultaneously separately.When first counter 202 and second counter 204 wherein one when counting up to a set value M (M is a non-zero positive integer), comparer 208 is output signal START to the three counters 206 just, allow the 3rd counter 206 begin counting with the clock frequency of first clock signal clk _ 1.On the other hand, when first counter 202 and second counter 204 all count down to set value M, comparer 208 just stopped output signal START to the three counters 206, made the 3rd counter 206 stop counting.Therefore, the count value of the 3rd counter 206 is first clock signal clk _ 1 and second clock signal CLK_2 and accumulates the required mistiming separately M time.
In another embodiment, each begins inverse since above-mentioned set value M simultaneously for first counter 202 and second counter 204.When wherein one reciprocal to zero time of first counter 202 and second counter 204, comparer 208 is output signal START to the three counters 206 just, allow the 3rd counter 206 begin counting with the clock frequency of first clock signal clk _ 1.On the other hand, all reciprocal to zero the time when first counter 202 and second counter 204, comparer 208 just stops output signal START to the three counters 206, makes the 3rd counter 206 stop counting.Therefore, the value of the 3rd counter 206 countings also is that first clock signal clk _ 1 is accumulated the required mistiming M time separately with second clock signal CLK_2.
No matter first counter 202 and second counter 204 are with normal counting mode or use mode reciprocal, and the 3rd counter 206 measured frequency offsets are all on the occasion of not having negative value, and therefore the count value of the 3rd counter 206 is all positive number.Decision circuitry 210 can receive the count value of the 3rd counter 206 to judge whether first clock signal clk _ 1 and the difference on the frequency of second clock signal CLK_2 meet an error range, and export one and judge signal (PASS or FAIL), meet or do not meet above-mentioned error range to represent this difference on the frequency.
For example, if the difference on the frequency of first clock signal clk _ 1 and second clock signal CLK_2 is expected to be 120PPM, and error range is set at+/-1PPM in, then can be whether between 119PPM and 121PPM and signal is judged in output by the anti-difference on the frequency that pushes away actual first clock signal clk _ 1 and second clock signal CLK_2 of the count value of the 3rd counter 206.
It should be noted that, can make the 3rd counter 206 begin counting by first trigger comparator 208 output signal START owing to count faster counter (that is clock frequency the higher person), thus comparer 208 can't go to differentiate first clock signal clk _ 1 and second clock signal CLK_2 clock frequency who fast who is slow.In addition, if first counter 202 and second counter 204 count up to set value M (or counting up to zero simultaneously) simultaneously, then comparer 208 can not make counter 206 begin counting by output signal START, therefore the count value of counter 206 is zero, and this represents first clock signal clk _ 1 identical with the clock frequency of second clock signal CLK_2.Moreover, if the clock frequency of first clock signal clk _ 1 and second clock signal CLK_2 very near the time, above-mentioned set value M can set bigger numerical value for, to improve the count value precision of the 3rd counter 206.
In one embodiment of this invention, clocking frequency comparing unit 200 can be applicable to the built-in self-test circuit, in order to test the frequency error of voltage-controlled quartz (controlled) oscillator.
Fig. 3 is another system embodiment synoptic diagram of the present invention.Integrated circuit (IC) chip 300 has a built-in self-test circuit, can test the frequency offset of voltage-controlled quartz (controlled) oscillator by an external test circuit 312, integrated circuit (IC) chip 300 comprises one voltage/numerically-controlled oscillator 302, a clocking frequency comparing unit 304, a controller 306 and bond pad 308 and 310.Wherein, voltage/numerically-controlled oscillator 302 and clocking frequency comparing unit 304 are positioned at same module.
Being familiar with this area person again ought be as can be known, test circuit 312 also can in be built in this integrated circuit (IC) chip and the also outside supplied with digital signal FC of integrated circuit (IC) chip from then on of controller 306.
In this embodiment, the internal structure of clocking frequency comparing unit 304 is same as Fig. 2, and dissimilarity is that first clock signal clk _ 1 and second clock signal CLK_2 among Fig. 2 are replaced by clock signal clk _ VCXO and the CLK_REF of Fig. 3 respectively.Therefore, the reference clock signal CLK_REF that clock signal clk _ VCXO that clocking frequency comparing unit 304 can be produced voltage/numerically-controlled oscillator 302 and test circuit 312 are provided makes comparisons, judge whether its frequency difference meets an error range, and export one and judge that signal (PASS or FAIL) is to represent this difference on the frequency and meet or not meet above-mentioned error range.
Compared to traditional clock frequency error measuring technique, the foregoing description has following several advantages.The first, the foregoing description can provide the voltage-controlled quartz (controlled) oscillator test circuit of board volume production test.The second, the foregoing description is digital running, and framework simply is difficult for influenced by processing procedure.The 3rd, the area of above-mentioned clocking frequency comparing unit (built-in self-test circuit) is little, the relevance grade height.The 4th, above-mentioned clocking frequency comparing unit (built-in self-test circuit) is than conventional art, and the required times of every class frequency side-play amount are measured in a large amount of minimizings.
Fig. 4 is the process flow diagram of one embodiment of the invention method of testing.In order to the frequency difference of two clock signals relatively, at the beginning earlier respectively the count value of initialization one first counter, one second counter and one the 3rd counter be zero (step S402).Behind step S402, first and second counters count from zero (step S404) to first clock signal and the second clock signal that receives separately simultaneously, and wherein first clock signal and second clock signal have first clock frequency and second clock frequency respectively.In addition, first and second counters can begin counting or stop counting according to control signal decision.
During the counting of first and second counters, judge whether first or second counter, one count value wherein equals a set value M (step S406), and M is a non-zero positive integer.If step 406 judged result is for being, then the 3rd counter begins to count (step S408) to first clock signal, again to step S410; If not, then jump directly to step S410.Step S410 judges whether the count value of first and second counters has counted up to above-mentioned set value M all.If step 410 judged result is for being, then the 3rd counter stop counting and relatively its count value whether meet an error range (step S412), comparative result output one judgement this comparative result of signal indication (step S414) according to this again; If not, then skip back to step S406.
In one embodiment, the counting of the 3rd counter can be controlled by an activation signal.For example, when first and second counters, one count value wherein equals set value M, can produce above-mentioned enable signal and begin counting to control the 3rd counter.On the other hand, when the count value of first and second counters all arrives above-mentioned set value M, can stop to produce above-mentioned enable signal to allow the 3rd counter stop counting.
In another embodiment, the method for Fig. 4 can be used for measuring whether conformance with standard of clock frequency that a voltage-controlled quartz (controlled) oscillator produced.Therefore, first clock signal of said method can obtain from a voltage-controlled quartz (controlled) oscillator, and the second clock signal can be a known reference clock signal.
Also have in another embodiment, above-mentioned first and second counters can be counted with the mode of inverse.For example, step S402 can be initialized as the count value of first and second counters above-mentioned set value M, and the count value of the 3rd counter still is initialized as zero.In step S404, first and second counters can be begun reciprocal respectively to zero simultaneously by set value M.And in step S406, can judge whether first or second counter, one count value wherein is reciprocal to zero, if, then skip to step S408, if not, then skip to step S410.In step S410, can judge whether the count value of first and second counters is reciprocal all to zero, if, then skip to step S412, if not, then skip to step S406.
Though the present invention discloses as above with several embodiment; right its is not in order to limiting the present invention, anyly is familiar with this operator, without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention is as the criterion when looking the claim scope person of defining.
Claims (18)
1. a clocking frequency comparing unit is characterized in that, described clocking frequency comparing unit comprises:
One first counter is in order to receive one first clock signal of a control signal and tool one first clock frequency;
One second counter is in order to receive a second clock signal of above-mentioned control signal and tool one second clock frequency;
One comparer receives the count value of above-mentioned first counter and above-mentioned second counter, to produce activation signal output; And
One the 3rd counter in order to receive above-mentioned enable signal and above-mentioned first clock signal, begins counting with above-mentioned first clock frequency when receiving above-mentioned enable signal,
Wherein, when above-mentioned first counter and above-mentioned second counter receive above-mentioned control signal simultaneously, promptly begin counting with above-mentioned first clock frequency and above-mentioned second clock frequency respectively, when wherein one when counting up to a set number of times, above-mentioned comparer is exported above-mentioned enable signal to above-mentioned the 3rd counter and is begun counting, when above-mentioned both all count up to above-mentioned set number of times, make above-mentioned comparer stop to export above-mentioned enable signal, to stop above-mentioned the 3rd rolling counters forward.
2. clocking frequency comparing unit as claimed in claim 1 is characterized in that, above-mentioned first clock signal produces from an oscillator.
3. clocking frequency comparing unit as claimed in claim 1, it is characterized in that, described clocking frequency comparing unit more comprises a decision circuitry, in order to receiving a count value of above-mentioned the 3rd counter, and judges according to above-mentioned count value whether above-mentioned first clock frequency meets an error range.
4. clocking frequency comparing unit as claimed in claim 1 is characterized in that, above-mentioned first and second counters stop counting from a set value of the above-mentioned set number of times of correspondence is reciprocal respectively more in order to when receiving above-mentioned control signal after zero.
5. clocking frequency comparing unit as claimed in claim 1 is characterized in that, above-mentioned first and second counters count from zero separately to a set value of the above-mentioned set number of times of correspondence, promptly stops counting.
6. an integrated circuit (IC) chip is characterized in that, described integrated circuit (IC) chip comprises:
One oscillator is in order to export one first clock signal; And
One clocking frequency comparing unit, in order to receive a control signal, above-mentioned first clock signal and a second clock signal,, and export one and judge that signal points out whether above-mentioned first clock signal meets an error range with more described first clock signal and described second clock signal according to described control signal.
7. integrated circuit (IC) chip as claimed in claim 6, it is characterized in that, described integrated circuit (IC) chip comprises that more a controller is connected in described oscillator, and the clock frequency of described first clock signal of a digital signal to adjust described oscillator and exported is provided.
8. integrated circuit (IC) chip as claimed in claim 6 is characterized in that, described control signal and described second clock signal are provided by a test circuit, and described test circuit is external in described integrated circuit (IC) chip.
9. integrated circuit (IC) chip as claimed in claim 6 is characterized in that, above-mentioned clocking frequency comparing unit more comprises:
One first counter, in order to receive above-mentioned control signal and above-mentioned first clock signal, first clock frequency with above-mentioned first clock signal when receiving above-mentioned control signal begins counting;
One second counter, in order to receive above-mentioned control signal and above-mentioned second clock signal, the second clock frequency with above-mentioned second clock signal when receiving control signal begins counting;
One comparer, in order to when above-mentioned first and second counters wherein one export an activation signal when counting up to a set number of times, and when above-mentioned first and second counters all count up to above-mentioned set number of times, stop to export above-mentioned enable signal; And
One the 3rd counter in order to receive above-mentioned enable signal and above-mentioned first clock signal, begins counting with above-mentioned first clock frequency when receiving above-mentioned enable signal, and stops counting when above-mentioned enable signal stops.
10. integrated circuit (IC) chip as claimed in claim 9, it is characterized in that, above-mentioned clocking frequency comparing unit more comprises a decision circuitry in order to receiving a count value of above-mentioned the 3rd counter, and judges according to above-mentioned count value whether above-mentioned first clock frequency meets above-mentioned error range.
11. integrated circuit (IC) chip as claimed in claim 9, it is characterized in that, described integrated circuit (IC) chip more receives a digital signal, and to adjust the clock frequency of described first clock signal that described oscillator exported, described digital signal can be provided by an external controller.
12. a clock frequency comparison method, described method comprises:
The count value of initialization one first counter, one second counter and one the 3rd counter;
Described first counter and described second counter begin counting to one first clock signal and a second clock signal that receives separately simultaneously;
When above-mentioned first and second counters one count value wherein equals a set value, above-mentioned the 3rd counter is begun counting to above-mentioned first clock signal; And
When the count value of above-mentioned first and second counters all equals above-mentioned set value, stop described the 3rd counter and export the count value of above-mentioned the 3rd counter.
13. clock frequency comparison method as claimed in claim 12 more comprises count value according to the output of above-mentioned the 3rd counter and produces one and judge that signal points out whether the frequency of above-mentioned first clock signal meets an error range.
14. clock frequency comparison method as claimed in claim 12, wherein above-mentioned first clock signal obtains from an oscillator.
15. clock frequency comparison method as claimed in claim 12, the count value of wherein initial above-mentioned first, second and the 3rd counter comprises that more the count value of setting above-mentioned first, second and the 3rd counter is zero, and wherein above-mentioned set value is a non-zero positive integer value.
16. clock frequency comparison method as claimed in claim 12, the count value of wherein initial above-mentioned first, second and the 3rd counter comprises that more the count value of setting above-mentioned first, second counter is a non-zero positive integer value, and the count value of setting above-mentioned the 3rd counter is zero, and wherein above-mentioned be that definite value is zero.
17. more comprising according to a control signal, clock frequency comparison method as claimed in claim 12, described method determine above-mentioned first and second counters to begin to count or stop counting.
18. clock frequency comparison method as claimed in claim 12, described method comprises more whether generation one activation signal is to control above-mentioned the 3rd rolling counters forward, wherein produce above-mentioned enable signal more comprise when the count value of above-mentioned first and second counters wherein one when arriving a set value, produce above-mentioned enable signal, and when the count value of above-mentioned first and second counters all arrives above-mentioned set value, stop to produce above-mentioned enable signal.
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| US5483201A (en) * | 1993-09-30 | 1996-01-09 | At&T Corp. | Synchronization circuit using a high speed digital slip counter |
| JP3665512B2 (en) * | 1999-07-12 | 2005-06-29 | 株式会社東芝 | Binary signal comparison device and PLL circuit using the same |
| US6965224B1 (en) * | 2003-05-16 | 2005-11-15 | Cisco Technology, Inc. | Method and apparatus for testing synchronization circuitry |
| CN1642010B (en) * | 2004-01-01 | 2010-04-28 | 华为技术有限公司 | Clock-locked frequency deviation detecting device |
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| CN105738695A (en) * | 2016-04-14 | 2016-07-06 | 杭州中科微电子有限公司 | Clock frequency tracking measuring and error estimating method and module |
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