CN101447971B - Automatic frequency control method of digital audio broadcasting receiver and tuner and channel decoding chip - Google Patents
Automatic frequency control method of digital audio broadcasting receiver and tuner and channel decoding chip Download PDFInfo
- Publication number
- CN101447971B CN101447971B CN2007100942968A CN200710094296A CN101447971B CN 101447971 B CN101447971 B CN 101447971B CN 2007100942968 A CN2007100942968 A CN 2007100942968A CN 200710094296 A CN200710094296 A CN 200710094296A CN 101447971 B CN101447971 B CN 101447971B
- Authority
- CN
- China
- Prior art keywords
- frequency
- bias
- decimal
- phase
- digital audio
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Landscapes
- Circuits Of Receivers In General (AREA)
Abstract
The invention discloses an automatic frequency control method of digital audio broadcasting receivers, comprising the following steps: respectively calculating decimal frequency deviation, integral frequency deviation and residual frequency deviation by a channel decoding unit; correcting the decimal frequency deviation and integral frequency deviation by the phase-locked loop of a tuner; and correcting the residual frequency deviation by a digital frequency converter based on CORDIC arithmetic; the frequency correcting range and performance can be effectively enhanced. The invention further discloses a tuner and channel decoding chip which adopt the automatic frequency control method of digital audio broadcasting receivers; the tuner and channel decoding chip are integrated in a single chip, which is convenient for the implementing of the automatic frequency control method of digital audio broadcasting receivers and reduces the cost of the digital audio broadcasting receivers.
Description
Technical field
The present invention relates to a kind of wireless receiver auto frequency control method, especially a kind of automatic frequency control method of digital audio broadcasting receiver.The invention still further relates to a kind of tuner and channel decoding chip that adopts above-mentioned automatic frequency control method of digital audio broadcasting receiver.
Background technology
Digital audio broadcasting is an audio droadcasting system of new generation.It has adopted digital audio as source of sound, has adopted OFDM and DQPSK as modulation system, and utilizes convolutional encoding and frequency, time-interleaved, improves error-correcting performance, can allow the digital audio broadcasting of people's uppick CD Quality.Traditional digital audio broadcast receiver generally is made up of tuner, channel decoding chip and audio decoder chip, its structure as shown in Figure 1, there are deviation in the frequency of digital audio broadcasting transmitter and the frequency of local receiver, need the automatic frequency control unit that frequency deviation is calculated and proofreaied and correct on receiver.In traditional receiver structure, the calculating of frequency deviation and correction are generally all finished by the channel-decoding unit, if frequency deviation is bigger, the filter in the tuner can filter part signal, reduces signal to noise ratio, influences the performance of receiver.And on device, tuner and channel decoding chip are separate devices, therefore have shortcomings such as cost height, poor performance.
Summary of the invention
Technical problem to be solved by this invention provides a kind of automatic frequency control method of digital audio broadcasting receiver, and the deviation that can effectively adjust frequency improves the performance of digital audio broadcast receiver, and reduces the cost of digital audio broadcast receiver.
For solving the problems of the technologies described above, the technical scheme of automatic frequency control method of digital audio broadcasting receiver of the present invention is, comprises frequency deviation is proofreaied and correct that described frequency deviation is divided into integer frequency bias, decimal frequency bias and residual frequency deviation, wherein,
With the prefix d1 of an OFDM symbol, d2 ... dP, and the repeating part d (N+1) corresponding with the prefix of described OFDM symbol, d (N+2) ... d (N+P), wherein N represents the length of window of fast fourier transform among the OFDM, P represents the length of Cyclic Prefix, send into two CORDIC unit respectively, calculate phase angle separately, obtain the difference of each corresponding phase angle, P phase angle difference obtained mean value, and the ratio of this mean value and π is decimal frequency bias and sub-carrier frequencies ratio at interval;
The crystal oscillator frequency that the numerical value of frequency divider is multiplied by the phase-locked loop input obtains the frequency of local oscillator, described decimal frequency bias is converted to the numerical value that described frequency divider need be revised, with this numerical value described frequency divider is regulated, changed the local frequency of phase-locked loop output, finish the correction of decimal frequency bias;
Described integer frequency bias is the sub-carrier frequencies frequency departure at interval of integral multiple, the skew of the integral multiple subcarrier spacing frequency of reference symbol on frequency that receives, through after the fast fourier transform, show as the integer skew on the frequency axis, on frequency domain, the reference symbol that receives is made related operation through value after the fast fourier transform and known reference symbol, maximum place in the resulting sequence as a result on duty with sub-carrier frequencies at interval, obtain the value of integer frequency bias;
Described integer frequency bias is converted to the numerical value that described frequency divider need be revised, and with this numerical value described frequency divider is regulated, and changes the local frequency of phase-locked loop output, finishes the correction of integer frequency bias;
Described residual frequency deviation obtains with judgement signal afterwards by the signal that relatively receives, described residual frequency deviation is sent into an accumulator element, the accumulated value of frequency is the phase place that needs correction, this phase place by cordic algorithm, is utilized and proofreaied and correct residual frequency deviation based on the digital frequency converter of cordic algorithm.
The present invention also provides a kind of chip, and its technical scheme is that described chip comprises:
The channel-decoding unit calculates described integer frequency bias, decimal frequency bias and residual frequency deviation, and residual frequency deviation is proofreaied and correct;
Tuner, comprising phase-locked loop circuit, integer frequency bias, the decimal frequency bias that described channel-decoding unit calculates feeds back in the described phase-locked loop circuit, and described integer frequency bias and decimal frequency bias are proofreaied and correct.
The present invention is calculated frequency deviation by the channel-decoding unit, then result of calculation is fed back in the tuner frequency is regulated, and has improved the performance of digital audio receiver greatly; The present invention is integrated into described channel-decoding unit and tuner in the same chip, has reduced the cost of digital audio receiver.
Description of drawings
The present invention is further detailed explanation below in conjunction with drawings and Examples:
Fig. 1 is the structure of existing digital audio receiver;
Fig. 2 is for calculating the schematic diagram of decimal frequency bias among the present invention;
Fig. 3 is for calculating the schematic diagram of integer frequency bias among the present invention;
Fig. 4 is for proofreading and correct the schematic diagram of residual frequency deviation among the present invention;
The schematic diagram of Fig. 5 among the present invention phase-locked loop circuit being proofreaied and correct;
Fig. 6 is the schematic diagram of the receiver of employing digital audio receiver automatic frequency control chip of the present invention.
Embodiment
Automatic frequency control method of digital audio broadcasting receiver of the present invention comprises frequency deviation is proofreaied and correct that described frequency deviation is divided into integer frequency bias, decimal frequency bias and residual frequency deviation, wherein,
Modulate the sub-carriers frequency interval as base unit with OFDM, decimal frequency bias is meant the frequency departure less than sub-carrier frequencies interval 1/2, an OFDM symbol is designated as d1, d2 ... dN, d (N+1), d (N+P), wherein N represents the length of window of fast fourier transform among the OFDM, and P represents the length of Cyclic Prefix, as shown in Figure 2, prefix d1 with this OFDM symbol, d2 ... dP, and the repeating part d (N+1) corresponding with the prefix of described OFDM symbol, d (N+2), d (N+P) sends into two CORDIC unit respectively, and I is the real part of input signal among Fig. 2, and Q is the imaginary part of input signal, calculate two signals phase angle separately, obtain the difference of each corresponding phase angle, P phase angle difference obtained mean value, the ratio of this mean value and π is decimal frequency bias and sub-carrier frequencies ratio at interval; More accurate for calculating, also can obtain mean value to the phase angle difference of a plurality of OFDM symbols, then the mean value of a plurality of OFDM symbols is averaged again, with the ratio of this mean value of trying to achieve at last and π ratio as decimal frequency bias and sub-carrier frequencies interval.
As shown in Figure 5, phase-locked loop circuit comprises phase discriminator, loop filtering and voltage controlled oscillator, by frequency divider the frequency of described phase-locked loop circuit is controlled, the crystal oscillator frequency that the numerical value of frequency divider is multiplied by the phase-locked loop input obtains the frequency of local oscillator, described decimal frequency bias is converted to the numerical value that described frequency divider need be revised, with this numerical value described frequency divider is regulated, changed the local frequency of phase-locked loop output, finish the correction of decimal frequency bias;
Described integer frequency bias is the sub-carrier frequencies frequency departure at interval of integral multiple, as shown in Figure 3, the skew of the integral multiple subcarrier spacing frequency of reference symbol on frequency that receives, through after the fast fourier transform, show as the integer skew on the frequency axis, on frequency domain, the reference symbol that receives is made related operation through value after the fast fourier transform and known reference symbol, maximum place in the resulting sequence as a result on duty with sub-carrier frequencies at interval, obtain the value of integer frequency bias;
As shown in Figure 5, described integer frequency bias is converted to the numerical value that described frequency divider need be revised, and with this numerical value described frequency divider is regulated, and changes the local frequency of phase-locked loop output, finishes the correction of integer frequency bias;
Described residual frequency deviation is meant the remaining frequency departure that the error of calculation, time drift or temperature drift are introduced, and proofreaies and correct respectively after decimal and the integer, and remaining residual frequency deviation is enough little.Along with the conversion of time, temperature, certain conversion also can take place in residual frequency in addition, on one side need calculate residual frequency deviation, Yi Bian in time correct.As shown in Figure 4, described residual frequency deviation obtains with judgement signal afterwards by the signal that relatively receives, described residual frequency deviation is sent into an accumulator element, the accumulated value of frequency is the phase place that needs correction, this phase place by cordic algorithm, is utilized and proofreaied and correct residual frequency deviation based on the digital frequency converter of cordic algorithm.
The present invention also provides a kind of tuner and channel decoding chip that adopts above-mentioned automatic frequency control method of digital audio broadcasting receiver, as shown in Figure 6, comprises
The channel-decoding unit calculates described integer frequency bias, decimal frequency bias and residual frequency deviation, and residual frequency deviation is proofreaied and correct;
Tuner, comprising phase-locked loop circuit, integer frequency bias, the decimal frequency bias that described channel-decoding unit calculates feeds back in the described phase-locked loop circuit, and described integer frequency bias and decimal frequency bias are proofreaied and correct.
The present invention is calculated frequency deviation by the channel-decoding unit, then result of calculation is fed back in the tuner frequency is regulated, and has improved the performance of digital audio receiver greatly; The present invention is integrated into described channel-decoding unit and tuner in the same chip, has reduced the cost of digital audio receiver.
Claims (3)
1. an automatic frequency control method of digital audio broadcasting receiver is characterized in that, comprises frequency deviation is proofreaied and correct, and described frequency deviation is divided into integer frequency bias, decimal frequency bias and residual frequency deviation, wherein,
With the prefix d1 of an OFDM symbol, d2 ... dP, and the repeating part d (N+1) corresponding with the prefix of described OFDM symbol, d (N+2) ... d (N+P), wherein N represents the length of window of fast fourier transform among the OFDM, P represents the length of Cyclic Prefix, send into two CORDIC unit respectively, calculate phase angle separately, obtain the difference of each corresponding phase angle, P phase angle difference obtained mean value, and the ratio of this mean value and π is decimal frequency bias and sub-carrier frequencies ratio at interval;
The crystal oscillator frequency that the numerical value of frequency divider is multiplied by the phase-locked loop input obtains the frequency of local oscillator, described decimal frequency bias is converted to the numerical value that described frequency divider need be revised, with this numerical value described frequency divider is regulated, changed the local frequency of phase-locked loop output, finish the correction of decimal frequency bias;
Described integer frequency bias is the sub-carrier frequencies frequency departure at interval of integral multiple, the skew of the integral multiple subcarrier spacing frequency of reference symbol on frequency that receives, through after the fast fourier transform, show as the integer skew on the frequency axis, on frequency domain, the reference symbol that receives is made related operation through value after the fast fourier transform and known reference symbol, maximum place in the resulting sequence as a result on duty with sub-carrier frequencies at interval, obtain the value of integer frequency bias;
Described integer frequency bias is converted to the numerical value that described frequency divider need be revised, and with this numerical value described frequency divider is regulated, and changes the local frequency of phase-locked loop output, finishes the correction of integer frequency bias;
Described residual frequency deviation obtains with judgement signal afterwards by the signal that relatively receives, described residual frequency deviation is sent into an accumulator element, the accumulated value of frequency is the phase place that needs correction, this phase place by cordic algorithm, is utilized and proofreaied and correct residual frequency deviation based on the digital frequency converter of cordic algorithm.
2. automatic frequency control method of digital audio broadcasting receiver according to claim 1, it is characterized in that, phase angle difference to a plurality of OFDM symbols is obtained mean value, then the mean value of a plurality of OFDM symbols is averaged again, with the ratio of this mean value of trying to achieve at last and π as decimal frequency bias and sub-carrier frequencies ratio at interval.
3. chip that adopts claim 1 or 2 described automatic frequency control method of digital audio broadcasting receiver is characterized in that described chip comprises:
The channel-decoding unit calculates described integer frequency bias, decimal frequency bias and residual frequency deviation, and residual frequency deviation is proofreaied and correct;
Tuner, comprising phase-locked loop circuit, integer frequency bias, the decimal frequency bias that described channel-decoding unit calculates feeds back in the described phase-locked loop circuit, and described integer frequency bias and decimal frequency bias are proofreaied and correct.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2007100942968A CN101447971B (en) | 2007-11-27 | 2007-11-27 | Automatic frequency control method of digital audio broadcasting receiver and tuner and channel decoding chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2007100942968A CN101447971B (en) | 2007-11-27 | 2007-11-27 | Automatic frequency control method of digital audio broadcasting receiver and tuner and channel decoding chip |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101447971A CN101447971A (en) | 2009-06-03 |
| CN101447971B true CN101447971B (en) | 2011-12-28 |
Family
ID=40743374
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2007100942968A Expired - Fee Related CN101447971B (en) | 2007-11-27 | 2007-11-27 | Automatic frequency control method of digital audio broadcasting receiver and tuner and channel decoding chip |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101447971B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102006255A (en) * | 2009-09-03 | 2011-04-06 | 卓胜微电子（上海）有限公司 | Estimation method of frequency deviation of integral multiple of subcarriers in orthogonal frequency division multiplexing (OFDM) system |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1464708A (en) * | 2002-06-03 | 2003-12-31 | 矽统科技股份有限公司 | Carrier recovery equipment of digital QAM receiver |
| WO2004004270A1 (en) * | 2002-06-26 | 2004-01-08 | Matsushita Electric Industrial Co., Ltd. | Receiver device |
| WO2006083940A2 (en) * | 2005-01-31 | 2006-08-10 | Marvell World Trade Ltd. | Improved precision cordic processor |
-
2007
- 2007-11-27 CN CN2007100942968A patent/CN101447971B/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1464708A (en) * | 2002-06-03 | 2003-12-31 | 矽统科技股份有限公司 | Carrier recovery equipment of digital QAM receiver |
| WO2004004270A1 (en) * | 2002-06-26 | 2004-01-08 | Matsushita Electric Industrial Co., Ltd. | Receiver device |
| WO2006083940A2 (en) * | 2005-01-31 | 2006-08-10 | Marvell World Trade Ltd. | Improved precision cordic processor |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101447971A (en) | 2009-06-03 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6219333B1 (en) | Method and apparatus for synchronizing a carrier frequency of an orthogonal frequency division multiplexing transmission system | |
| US6744828B1 (en) | Receiving apparatus | |
| KR102552996B1 (en) | System and method for synchronous processing of analog and digital paths in a digital radio receiver | |
| JP5323291B2 (en) | Method and apparatus for estimating fine and coarse frequency offset in digital audio broadcasting | |
| TWI403135B (en) | Transmitter, receiver and method for detecting and compensating the carrier frequency offset | |
| CN1085922C (en) | Automatic gain control circuit and method therefor | |
| KR20060016580A (en) | Frequency recovery apparatus and dvb-h receiver | |
| US7305053B2 (en) | Dat-aided frequency offset detection using phase unwrapping | |
| US20090185630A1 (en) | Method and apparatus for estimating the channel impulse response of multi-carrier communicating systems | |
| US20080118006A1 (en) | Symbol synchronization using phase discontinuity for dvb-t systems in awgn channels | |
| US8213524B2 (en) | DTMB-based control system and receiving system having the same | |
| CN101447971B (en) | Automatic frequency control method of digital audio broadcasting receiver and tuner and channel decoding chip | |
| JP2002164866A (en) | Broadcasting device using ofdm modulation method | |
| US8817860B2 (en) | Systems and methods for performing phase tracking within an ADC-based tuner | |
| CN1347602A (en) | Method and apparatus for transmission, and medium | |
| US20090103667A1 (en) | Methods for Modified Signal Acquisition for OFDM Schemes | |
| US11343066B2 (en) | OFDMA baseband clock synchronization | |
| US7480350B2 (en) | Carrier recovery apparatus and broadcasting receiver using the same | |
| KR100697526B1 (en) | Tracking device for digital broadcast receiver | |
| KR100587279B1 (en) | apparatus and method for correcting timing in digital broadcasting receiver | |
| JP2000068974A (en) | Ofdm receiver | |
| WO2000008790A1 (en) | Clock generator, clock generating method, and signal receiver | |
| KR100710359B1 (en) | Carrier recovery apparatus and method thereof in digital broadcast receiver | |
| JP4894822B2 (en) | Frequency correction system and receiver | |
| EP0946010A2 (en) | Receiver for receiving digital broadcast programmes |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| ASS | Succession or assignment of patent right |
Owner name: RDA TECHNOLOGY CO., LTD. Free format text: FORMER OWNER: RDA MICROELECTRONICS (SHANGHAI) CO., LTD. Effective date: 20100427 |
|
| C41 | Transfer of patent application or patent right or utility model | ||
| COR | Change of bibliographic data |
Free format text: CORRECT: ADDRESS; FROM: 201203 ROOM 302, BUILDING 2, NO.690, BIBO ROAD, PUDONG NEW DISTRICT, SHANGHAI CITY TO: HOUSE 22, ZHONGYIN BUILDING, MIDDLE 1ST ROAD, HONG KONG GARDEN |
|
| TA01 | Transfer of patent application right |
Effective date of registration: 20100427 Address after: 22 floor, Bank of China Tower, 1 Garden Road, Hongkong Applicant after: RDA Microelectronics Co., Ltd. Address before: 201203, room 2, building 690, No. 302 blue wave road, Shanghai, Pudong New Area Applicant before: RDA Microelectronics (Shanghai) Corp. Ltd. |
|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C17 | Cessation of patent right | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20111228 Termination date: 20131127 |