CN101446891A - A method for achievement of structure register reservation recovery instruction of high-performance microprocessor - Google Patents
A method for achievement of structure register reservation recovery instruction of high-performance microprocessor Download PDFInfo
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- CN101446891A CN101446891A CNA2007100943015A CN200710094301A CN101446891A CN 101446891 A CN101446891 A CN 101446891A CN A2007100943015 A CNA2007100943015 A CN A2007100943015A CN 200710094301 A CN200710094301 A CN 200710094301A CN 101446891 A CN101446891 A CN 101446891A
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Abstract
The invention discloses a method for the achievement of structure register reservation recovery instruction of high-performance microprocessor, comprising a structure register reservation recovery instruction, a set of reservation recovery instruction transform logics, a structure register reservation cache storage, a data stream load queue and a data stream storage queue, wherein the structure register reservation recovery instruction is transformed into storage load instruction with special symbol by the reservation recovery instruction transform logics, and the structure register reservation cache storage is read by a storage access controller to finish the reservation and recovery of the structure register. The invention solves the problems of true relativity confliction and presumption recoding of reservation cache storage by the storage and load queue used by the storage load instruction, makes the reservation cache storage independent from the multilevel Cache structure of the current microprocessors, and guarantees the sameness of access delay of the reservation recovery cache storage and storage load instruction delay of hit L1 data Cache, to not only effectively shorten the reservation and recovery time of structure register, but effectively use existing storage access for the control of hardware logic without increasing excessive hardware design complexity and hardware cost.
Description
Technical field
The present invention relates to a kind of high-performance microprocessor structure register and keep the implementation method of recovering instruction, particularly relate to and a kind ofly instruct the implementation structure register to keep the method for recovering by the special storage class of packing into.
Background technology
In the present high-performance microprocessor, when reservation of Processing Structure register and recovery, adopt common storage instruction mostly, structure register is saved in the primary memory space (for example system stack) of software administration, and utilize common load with the content recovery that keeps in the primary memory space in structure register.Also there is segment processor that special-purpose stack operation instruction is provided, for example push in the x86 processor and pop instruction, but all be to utilize Cache and main memory the hierarchy type storage organization to keep the structure register content from essence.
There are two shortcomings in this method: the one, and it is longer to delay time.Though the Multi-Level Cache structure is arranged, because the Cache finite capacity must directly not visited main memory in case Cache is not hit in visit, time-delay increases considerably; The 2nd, when using data stream storage and load,, also to take the source address register of another structure register at least as the storage load except being retained register as one of source-register.
If adopt the compute classes of constant time lag to instruct the reservation of implementation structure register, then can become the difficult point of realization as the reservation memory buffer of reserve statement target or recovery command source.Because it is different with structure register to keep memory buffer, it does not have similar " rename register " or " register window " to handle like that to infer the fallback mechanism write, is not that the scoring plug mechanism of unit limits the out of order execution that reservation that truth closes recovers instruction with the physical register yet.If solve this problem, then can increase hardware complexity greatly by hardware.Yet, do not solve the detection of truth pass and the rollback problem that supposition writes, can increase the use restriction that keeps the recovery instruction again, be not easy to use, and reduce the efficient of reservation recovery operation.
The present invention has announced a kind of structure register reservation method of high-performance microprocessor.This method is utilized an on-chip memory that is independent of outside the hierarchy type storage organization---and structure register keeps memory buffer (being called for short structure register keeps buffering or keep buffering), this keeps buffering and adopts independent addressing mode, and its data width is identical with the data width of structure register.This method also provides a structure register reserve statement (abbreviation reserve statement) and a structure register to recover instruction (be called for short and recover instruction), the form of these two instructions is different with the generic storage load, its operand part only comprises the structure register that is saved number and structure register keeps the buffer index address, therefore reserve statement and recovery instruction, except use be retained or the structure register that recovers as source-register or the destination register, do not take other structure register.For under the situation that does not roll up hardware spending, the out of order execution of supporting reserve statement and recovering to instruct, when these two instructions of hardware actual treatment, be translated into special data stream storage load, and adopt the processing mode be similar to the storage load, utilize pack into formation and the data stream storage queue of data stream in the memory access control to handle and keep the problem that the out of order execution of instruction brings correlativity of recovering.But keep and to instruct the not storeies at different levels of access level formula storage organization, and visit keeps and cushions, and finishes reservation or recovery to structure register.
Description of drawings
Below in conjunction with accompanying drawing and embodiment the present invention is done explanation in further detail:
Fig. 1 is the present invention's one example, the treatment scheme of description architecture register reserve statement;
Fig. 2 is another example of the present invention, and the description architecture register recovers the treatment scheme of instruction.
Embodiment
The present invention is a kind of high-performance microprocessor structure register reservation method, adopts structure register reserve statement (abbreviation reserve statement) and structure register to recover instruction (be called for short and recover instruction), finishes quick reservation and recovery operation to structure register.Reserve statement and recovery instruction have independently order number, its operand part only comprises the index address that the structure register that is saved or recovers number and structure register keep buffering, but in the instruction decode stage, by hardware reserve statement is forced to be converted into the data stream storage instruction that has distinctive mark, force to be converted into the data stream load that has distinctive mark recovering instruction.The similar storage instruction of reserve statement after the conversion, the structure register of its source data register for needing to keep, the address register content is fixed as " complete 0 " (the unactual ordinary construction register that takies), and its address offset is partly for keeping the index address of buffering.Recovery instruction class after the conversion is like load, and its target data register is for needing the structure register of recovery, and the address register content is fixed as " complete 0 " (the unactual ordinary construction register that takies), and its address offset is partly for keeping the index address of buffering.Reserve statement is the same with common data stream storage load with the recovery instruction, all pass through address computation, the physical address that the index address that keeps buffering is converted to memory access is represented form, and this address does not participate in the actual situation address substitution, directly enters scu.
In scu, reserve statement is similar to the treatment scheme of data stream storage instruction, and inquiry keeps memory buffer, and with the relevant information of result and instruction, comprises data, in the storage queue of data-in stream.Difference is that the one-level Data Cache is not visited in reserve statement, but the access structure register keeps memory buffer, and Query Result must be to hit and have a write permission.After all instructions before this reserve statement had all normally been submitted to, this reserve statement stream just was allowed to submit to, data was write keep buffering.
In scu, it is similar to the treatment scheme of data stream load to recover instruction, inquiry keeps memory buffer, if hit then data read according to the address, write the corresponding structure register then, and will visit the relevant information of result and instruction, data-in stream is packed in the formation.Difference is that the one-level Data Cache is not visited in reserve statement, but the access structure register keeps memory buffer, and Query Result must be to hit.
If the recovery that same reservation memory buffer clauses and subclauses are conducted interviews instruction and when recovering instruction by out of order emission, the memory access control assembly can be as the storage and the load of two relevant out of order emissions of processing memory, handle these correlativity conflicts, do not need to increase new hardware spending.
The following stated example is understood the present invention in detail.
Example one
As Fig. 1, A is the structure register reserve statement, A is converted to the data stream storage instruction that has distinctive mark by instruction transform logic, the source-register of instruction A after the conversion is the structure register that will preserve, do not need address register, side-play amount is that structure register keeps the buffer index address.After the A transmitting instructions, will keep the index address and complete " 0 " value addition of buffering at the address computation parts, obtain effective memory access address.These address process address substitution parts, but do not replace direct physical address as memory access.
The A instruction uses its physical address inquiry to keep the corresponding entry state of memory buffer, but keep not state of buffering, hit and possess write permission but directly return, and will visit the relevant information of result and instruction, comprise data, in the storage queue of data-in stream.
The A instruction also utilizes its physical address when inquiry keeps the buffer entries state, the associative lookup data stream queue entries of packing into, if find that the address is identical with it, but the younger data stream load that has distinctive mark, then the conflict of write-then-read correlativity has taken place in explanation, this moment must be the same with the write-then-read correlativity conflict of handling the common data stream instruction, and generation is retransmitted self-trapping.
After all instructions before the A instruction have all normally been submitted to, if the correlativity conflict does not take place in this instruction, then be allowed to submit to, at this moment, could send write request to the read-write control assembly, the read-write control assembly finds it is the data stream storage instruction that has distinctive mark, then data based physical address is write to keep buffering, rather than writes the one-level Data Cache.
Example two
As Fig. 2, B is that structure register recovers instruction, B is converted to the data stream load that has distinctive mark by instruction transform logic, the destination register of instruction B after the conversion is the structure register that will recover, do not need address register, side-play amount is that structure register keeps the buffer index address.After the B transmitting instructions, will keep the index address and complete " 0 " value addition of buffering at the address computation parts, obtain effective memory access address.These address process address substitution parts, but do not replace direct physical address as memory access.
The B instruction uses its physical address inquiry to keep the corresponding entry state of memory buffer, keeps not state of buffering, but directly returns the data of hitting and reading respective entries, and will visit the relevant information of result and instruction, in the storage queue of data-in stream.
The B instruction also utilizes its physical address when inquiry keeps the buffer entries state, associative lookup data stream store queue entries, if find that the address is identical with it, but the more old data stream load that has distinctive mark, then explanation needs data recovered also not write and keeps buffering, this moment is necessary, and the address is identical with it with all, but in the more old data stream load that has distinctive mark, the data of selecting minimus data load preservation are as restore data.
The B instruction writes restore data in the physical register, and after waiting for that this reserve statement all instructions have before all normally been submitted to, this recovery instruction just is allowed to submit to, at this moment, physical register could be mapped as structure register.
Claims (3)
1, a kind of structure register of high-performance microprocessor keeps the implementation method of recovering instruction, comprise that a class formation register keeps the recovery instruction, one cover keep to recover instruction transform logic, and structure register keeps memory buffer, and data stream pack into formation and data stream storage queue; Described structure register keeps the recovery instruction, be converted into the storage load that has distinctive mark by keeping the recovery instruction transform logic, by the memory access control assembly structure register is kept memory buffer and carry out read-write operation, finish reservation and recovery operation, it is characterized in that described structure register keeps buffering and adopted and be independent of on-chip memory outside the hierarchy type storage organization, independent addressing and realize structure register.
2, a kind of high-performance microprocessor structure register as claimed in claim 1 keeps the implementation method of recovering instruction, it is characterized in that the structure register reserve statement is converted into special data stream storage instruction, structure register recovers instruction and is converted into special data stream load, realization keeps the accessing operation of memory buffer for the structure register of independent addressing, and the execution time-delay of stream storage instruction of the special data after transforming and data stream load, identical with the execution time-delay of hitting one-level Data Cache common data stream storage instruction and data stream load.
3, a kind of high-performance microprocessor structure register as claimed in claim 2 keeps the implementation method of recovering instruction, it is characterized in that the special data that is changed into by the structure register reserve statement flows storage instruction, and recover instruction by structure register and change into special data stream load, can be by the storage employed storage queue of load and the formation of packing into, the true correlativity conflict and the supposition that solve structure register reservation memory buffer data access write problem, thereby the implementation structure register keeps out of order emission and the out of order execution that recovers instruction.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109375950A (en) * | 2009-12-22 | 2019-02-22 | 英特尔公司 | Position range isolation instruction, method and apparatus |
| CN110377339A (en) * | 2019-08-17 | 2019-10-25 | 深圳芯英科技有限公司 | Long-latency instruction processing unit, method and equipment, readable storage medium storing program for executing |
| CN114168199A (en) * | 2022-02-11 | 2022-03-11 | 摩尔线程智能科技(北京)有限责任公司 | Read-write operation multi-data request decoupling circuit structure and read-write method |
| CN117289995A (en) * | 2023-10-11 | 2023-12-26 | 海光信息技术股份有限公司 | Instruction processing method and processor |
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2007
- 2007-11-27 CN CNA2007100943015A patent/CN101446891A/en active Pending
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109375950A (en) * | 2009-12-22 | 2019-02-22 | 英特尔公司 | Position range isolation instruction, method and apparatus |
| CN109375950B (en) * | 2009-12-22 | 2023-06-20 | 英特尔公司 | Bit range isolation instruction, method and apparatus |
| CN110377339A (en) * | 2019-08-17 | 2019-10-25 | 深圳芯英科技有限公司 | Long-latency instruction processing unit, method and equipment, readable storage medium storing program for executing |
| CN110377339B (en) * | 2019-08-17 | 2024-03-01 | 中昊芯英(杭州)科技有限公司 | Long-delay instruction processing apparatus, method, and device, and readable storage medium |
| CN114168199A (en) * | 2022-02-11 | 2022-03-11 | 摩尔线程智能科技(北京)有限责任公司 | Read-write operation multi-data request decoupling circuit structure and read-write method |
| CN114168199B (en) * | 2022-02-11 | 2022-04-15 | 摩尔线程智能科技(北京)有限责任公司 | Read-write operation multi-data request decoupling circuit structure and read-write method |
| CN117289995A (en) * | 2023-10-11 | 2023-12-26 | 海光信息技术股份有限公司 | Instruction processing method and processor |
| CN117289995B (en) * | 2023-10-11 | 2024-05-10 | 海光信息技术股份有限公司 | Instruction processing method and processor |
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