CN101436167B - Method for interpreting tandem transmitting signal - Google Patents
Method for interpreting tandem transmitting signal Download PDFInfo
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- CN101436167B CN101436167B CN200710188601XA CN200710188601A CN101436167B CN 101436167 B CN101436167 B CN 101436167B CN 200710188601X A CN200710188601X A CN 200710188601XA CN 200710188601 A CN200710188601 A CN 200710188601A CN 101436167 B CN101436167 B CN 101436167B
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- decipher
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Abstract
The invention relates to a method for interpreting a serial transmission signal. The method comprises the following steps: firstly, the serial transmission signal is received; and the serial transmission signal comprises a serial data signal or a serial pulse signal; secondly, according to the serial pulse signal, m bits are sequentially read from the serial data signal; thirdly, numerical values corresponding to the m bits are sequentially generated; and finally, each numerical value and a content value of a buffer are sequentially subjected to add operation; and a result after the add operation replaces the content value and is stored in the buffer.
Description
Technical field
The invention relates to a kind of method of decipher serial transmission signal, and particularly relevant for a kind of method of quick decipher serial transmission signal.
Background technology
The serial transmission technology is widely used between transmission end and the receiving end, and wherein, serial transmission signal between the two comprises serial data signal and serial clock signal.Please refer to the 1st figure, it illustrates is the synoptic diagram of conventional serial transmission signals.The serial transmission signal comprises serial data signal Data and serial clock signal SCK.Serial data signal Data comprises a plurality of bits, for example is instruction (command) bit, address (address) bit, data bit or particular bit.Particular bit is for example for initial (start) bit, response (ack) bit or stop (stop) and compare top grade.Serial clock signal SCK comprises a plurality of time sequential pulses, and each time sequential pulse is utilized and reads the bit of serial data signal Data in the mode that trigger edge-triggered or accurate position.
Please refer to the 2nd figure, it illustrates the process flow diagram of the method that is traditional decipher serial transmission signal.At first, in step 210, receive a serial transmission signals, this serial transmission signal comprises a serial datum signal and a serial clock signal, and the serial clock signal comprises a plurality of time sequential pulses.Then, in step 220, the mode of utilizing edge-triggered or accurate position to trigger triggers Interrupt Service Routine (interrupt service function) according to these a little time sequential pulses, to read corresponding bit from serial data signal.
Please refer to the 1st figure, one master routine of receiving end triggers Interrupt Service Routine in the positive edge (time t1) of the time sequential pulse of serial clock signal SCK, this moment, master routine can push storehouse (push) to the program address earlier, carry out Interrupt Service Routine and jump (jump) then, just entered to the action of a subroutine to read.Afterwards, read corresponding bit in the negative edge (time t2) of same time sequential pulse is preceding, pop-up a stack (pop) program address is with original master routine that jumps back again.
Then, in step 230, the bit that identification received belongs to command bit, address bit, data bit or particular bit, and utilizes the mode that screws in (rotate) with corresponding position in bit storage to a buffer that is received.Please refer to the 3rd figure, it illustrates is that tradition utilizes the mode of screw-in with the synoptic diagram of data storage to buffer.If it is a data byte that receiving end receives 13 data bits, then buffer 300 for example is that the buffer of one 13 bit sizes and the value in the buffer 300 were (0 0 0...0 0) originally
2
If this data byte for example is (b
12b
11b
10... b
1b
0)
2=(1 0 1...1 0)
2, then these 13 data bits can deposit corresponding position in the buffer 300 in regular turn by the mode that screws in.At first, bit b
12Be stored into mnemon a earlier
0Then, be stored in mnemon a
0Then moved to mnemon a
1To finish primary screw-in action.Afterwards, be stored in mnemon a
1Bit b
12Then moved to mnemon a
2To finish secondary screw-in action.After 12 times screw-in action, bit b
12(=1) can be stored in mnemon a
12Afterwards, utilize 11 screw-in instructions, bit b
11(=1) can be stored to mnemon a
10Afterwards, utilize 1 screw-in instruction, bit b
1(=1) is stored in mnemon a
1And bit b
0(=0) then is stored in mnemon a
0In.
Bit of every storage, in step 240, receiving end can judge whether that storage finishes.If storage does not finish, then get back to step 220 to continue to read follow-up bit.If storage finishes, then enter step 250.In step 250, receiving end meeting decipher is stored in the byte in the buffer, and carries out corresponding processing action.
The method of above-mentioned traditional decipher serial transmission signal needs to push storehouse to the program address and is just triggered Interrupt Service Routine and jump to subroutine in step 220, need again through the pop-up a stack master routine that just jumped back again.Therefore, the processor of receiving end often will be spent a lot of system frequency cycles, can finish the action that receives a bit.So if the bit number of serial transmission signal is many more, and the requirement of transmission speed is when fast more, can cause the computational burden of processor of receiving end high more, and has influence on the usefulness of processor.In addition, if the bit number of serial transmission signal is many more, then the screw-in instruction number of times in the required execution of step 230 is also many more, has improved the computational burden of processor equally.Simultaneously, also will make cost increase and the consumed power of the processor of receiving end rises.
Summary of the invention
The present invention is relevant for a kind of method of decipher serial transmission signal, must not use Interrupt Service Routine and be able in the one-period of serial clock signal, read a bit, and the bit that utilizes additive operation to be received with storage, event is decipher serial transmission signal apace, and the while can reduce the computational burden of processor and reduce the consumed power of processor.
A kind of method of decipher serial transmission signal is proposed according to a first aspect of the invention.The method comprises, at first, receives the serial transmission signal, and the serial transmission signal comprises a serial datum signal and a serial clock signal.Then, read m bit according to the serial clock signal in regular turn from serial data signal.Then, produce the numerical value that corresponds to m bit in regular turn.Afterwards, in regular turn the contents value in each numerical value and the buffer is done additive operation, and the result after the additive operation replaced contents value and be stored in the buffer.After this, judging whether this m bit is stored finishes.Then, when this m bit storage finishes, send one first Response field bit to a transmission end.After this, decipher is stored in m bit in the buffer, and carries out corresponding processing action.
According to a second aspect of the invention, propose a kind of method of decipher serial transmission signal, be applied to a receiving end.The method comprises, at first, receives the serial transmission signal, and the serial transmission signal comprises a serial datum signal and a serial clock signal.Then, whether the accurate position of logic of judging the serial clock signal equals a default value.Then, when the accurate position of the logic of serial clock signal is default value, in a serial clock pulse cycle of this serial clock signal, read a bit from serial data signal.Afterwards, store this bit in a buffer, wherein, buffer is in order to m bit of storage.After this, judging whether this m bit is stored finishes.Then, when this m bit storage finishes, send one first Response field bit to a transmission end.After this, decipher is stored in m bit in the buffer, and carries out corresponding processing action.Wherein, this method is not used Interrupt Service Routine.
For foregoing of the present invention can be become apparent, a preferred embodiment cited below particularly, and cooperate appended graphicly, be described in detail below:
Description of drawings
The 1st figure illustrates the synoptic diagram of conventional serial transmission signals.
The 2nd figure illustrates the process flow diagram of the method for traditional decipher serial transmission signal.
The 3rd figure illustrates tradition and utilizes the mode of screw-in with the synoptic diagram of data storage to buffer.
The 4th figure illustrates the process flow diagram according to the method for the decipher serial transmission signal of first embodiment of the invention.
The 5th figure illustrates the process flow diagram according to the method for the decipher serial transmission signal of second embodiment of the invention.
The 6th figure illustrates the process flow diagram according to the method for the decipher serial transmission signal of third embodiment of the invention.
Embodiment
The invention provides a kind of method of decipher serial transmission signal, must not use Interrupt Service Routine and be able in the cycle of serial clock signal, read bit, utilize additive operation that institute is received bit again and deposit corresponding position in the buffer in, can reduce the computational burden and the power consumption of receiving end, so the cost of quick decipher serial transmission signal of energy and reduction receiving end.
First embodiment
Please refer to the 4th figure, it illustrates is process flow diagram according to the method for the decipher serial transmission signal of first embodiment of the invention.The method is applied to a receiving end.Receiving end comes data in each field of decipher according to the agreement of this serial transmission signal.This agreement for example is SPI (Serial PeripheralInterface), I2C (Inter-Integrated Circuit), the agreement of UART serial transmission interfaces such as (universalasynchronous receiver/transmitter).
At first, in step 410, receive a serial transmission signals, this serial transmission signal comprises a serial datum signal and a serial clock signal.Then, in step 420, read m bit according to the serial clock signal in regular turn from serial data signal, m is a positive integer.This m bit for example is address byte or data byte.In addition, in step 420, the time sequential pulse that receiving end can be comprised according to the serial clock signal, the mode of utilizing edge-triggered or accurate position to trigger to read bit from serial data signal, so is not limited to this.
Then, in step 430, produce the numerical value correspond to m bit in regular turn, and the result that m numerical value is carried out after the additive operation is stored in the buffer.The practice of now m digital value being carried out additive operation is described further with following two examples.First example of the practice of additive operation supposes that for utilizing addition (ADD) computing that counts m bit of this first field is b in regular turn
m, b
M-1, b
M-2... b
1, b
0, when reading b
mValue when being logical one, with numerical value 2
mAdd in the contents value of buffer, when reading b
M-1, b
M-2... b
1, b
0Value when being logical one, then respectively with numerical value 2
M-1, 2
M-2..., 2
1, 2
0Add in the contents value of buffer.
In addition, except as the utilizing the numerical value addition of first example, can also utilize logical addition (AND) computing to store this m bit.Second example of the practice of additive operation is for utilizing logical addition (AND) computing, when reading b
mValue when being logical one, with (1 0 0...0 0)
2Add in the contents value of buffer, when reading b
M-1, b
M-2... b
1, b
0Value when being respectively logical one, then respectively with numerical value (0 1 0...0 0)
2, (0 0 1...0 0)
2... (0 0 0...1 0)
2, (0 0 0...0 1)
2Add in the contents value of buffer.Thus, must screw-in instruction repeatedly can not store this m bit in buffer, reduce the computational burden of receiving end.And the number of times of the additive operation that each bit is required all is the same, can not look like as the conventional practice, and the pairing screw-in number of times of the bit of diverse location is inequality.
Come again, in step 440, judge whether this m bit is stored to finish.If storage does not finish, then get back to step 420, to continue to read remaining bit.If storage finishes, then in step 450, send one first Response field bit to a transmission end.
Second embodiment
Please refer to the 5th figure, it illustrates is process flow diagram according to the method for the decipher serial transmission signal of second embodiment of the invention.The method is applied to a receiving end.Receiving end comes Bit data in each field of decipher according to the agreement of serial transmission signal.At first, in step 510, receive a serial transmission signals, this serial transmission signal comprises a serial datum signal and a serial clock signal.
Then, in step 515, judge whether the accurate position of logic of serial clock signal is " 1 ".Then, in step 520, when the accurate position of the logic of serial clock signal is this default value, read a bit from serial data signal.This bit for example is a bit of a bit address bit group or a bit of a data-bit-group.
In the present embodiment, the method does not use the mode of Interrupt Service Routine to read a bit from serial data signal in a serial clock pulse cycle in receiving end.That is, in the program code of the master routine of receiving end, promptly comprised from the program code of serial data signal reading of data bit.This master routine is for example carried out by a processor of receiving end, and the frequency of system's clock signal of processor is higher than the frequency of above-mentioned serial clock signal.Therefore, master routine can in a serial clock pulse cycle, directly be carried out the action of reading serial data signal under the control of system's clock signal.Processor need not carried out Interrupt Process, can finish the action of reading serial data signal.
With conventional practice need the call interruption service routine, the practice that makes processor carry out Interrupt Process is compared, present embodiment saved and traditional the program address pushed storehouse, jump, with actions such as program address pop-up a stack, handle the stand-by period that receives data so can reduce effectively, make the speed that receives data accelerate.
In addition, because in the conventional practice, the positive edge and the negative edge of serial clock signal all can trigger Interrupt Service Routine, so conventional practice must be finished the action of a bit of reading of data between positive edge of serial clock signal and an adjacent negative edge.Because present embodiment need not carried out Interrupt Service Routine, so do not need as tradition,, present embodiment gets final product so only needing in a serial clock pulse cycle data read with a bit to finish in the positive edge of a time sequential pulse of serial clock signal and the action that negative intermarginal (being generally the serial clock pulse cycle half) finishes the data that read a bit.Therefore, present embodiment has the time of the more abundant data that read a bit.And, in a serial clock pulse cycle of serial clock signal, reading the excess time after the data of a bit, master routine more can be carried out the relevant treatment action of the data that are relevant to the bit that is read, and has improved the usefulness of receiving end accordingly.
Afterwards, in step 530, store this bit in buffer.
The 3rd embodiment
Please refer to the 6th figure, it illustrates is process flow diagram according to the method for the decipher serial transmission signal of third embodiment of the invention.Present embodiment mainly is in conjunction with first embodiment and second embodiment and get.At first, in step 610, receive a serial transmission signals, this serial transmission signal comprises a serial datum signal and a serial clock signal.Then, in step 620, read m bit according to the accurate position of the logic of serial clock signal from serial data signal, m is a positive integer, and a serial clock pulse cycle corresponds to a bit.This m bit for example is address bit group or data-bit-group.In step 620, receiving end need not trigger Interrupt Service Routine promptly can read a bit from serial data signal in a serial clock pulse cycle data.
Then, in step 630, produce the numerical value correspond to m bit in regular turn, and the result that m numerical value is counted after additive operation (ADD) or logical addition computing (AND) processing is stored in the buffer.In step 640, judge whether this m bit is stored to finish.If storage does not finish, then get back to step 620, to continue to read remaining bit.If storage finishes, then in step 650, send one first Response field bit to a transmission end.
The method of the disclosed decipher serial transmission of the above embodiment of the present invention signal, because receiving end preestablishes the field of the bit of the serial data signal that will receive, so receiving end must not use Interrupt Service Routine, push instructions such as storehouse or jump, must not wait for the data that promptly are able to read a bit in the serial clock pulse cycle of serial clock signal.In addition, owing to do not need and to read in a positive edge of the time sequential pulse of serial clock signal and one of adjacent negative intermarginal finishing, so receiving end still can utilize the remaining time in the serial clock pulse cycle to carry out relevant processing action, improves the usefulness of receiving end accordingly.
In addition, the method of decipher serial transmission signal of the present invention also utilizes additive operation directly to deposit the Bit data that is received in the buffer corresponding position, omitted a large amount of screw-in instructions, reduce the computational burden and the power consumption of receiving end, so the cost and the power attenuation of quick decipher serial transmission signal of energy and reduction receiving end.
In sum, though the present invention discloses as above with a preferred embodiment, so it is not in order to limit the present invention.The ordinary technical staff in the technical field of the invention, without departing from the spirit and scope of the present invention, when being used for a variety of modifications and variations.Therefore, protection scope of the present invention is as the criterion when looking the accompanying Claim person of defining.
Claims (10)
1. the method for a decipher serial transmission signal comprises:
Receive this serial transmission signal, this serial transmission signal comprises a serial datum signal and a serial clock signal;
Read m bit according to this serial clock signal in regular turn from this serial data signal;
Produce the numerical value that corresponds to this m bit in regular turn;
In regular turn the contents value in each numerical value and the buffer is done additive operation, and the result after this additive operation replaced this contents value and be stored in this buffer;
Judging whether this m bit is stored finishes;
When this m bit storage finishes, send one first Response field bit to a transmission end; And
Decipher is stored in m bit in the buffer, and carries out corresponding processing action.
2. the method for decipher serial transmission signal as claimed in claim 1, wherein, this additive operation is addition (ADD) computing that counts, and this m bit is b in regular turn
m, b
M-1, b
M-2B
1, b
0, when reading b
mValue when being logical one, with numerical value 2
mAdd in the contents value of this buffer, when reading b
M-1, b
M-2B
1, b
0Value when being respectively logical one, then respectively with numerical value 2
M-1, 2
M-2..., 2
1, 2
0Add in the contents value of this buffer.
3. the method for decipher serial transmission signal as claimed in claim 1, wherein, this additive operation is a logical addition (AND) computing, and this m bit is b in regular turn
m, b
M-1B
1, b
0, when reading b
mValue when being logical one, with (1 0 0...0 0)
2Add in the contents value of this buffer, when reading b
M-1, b
M-2B
1, b
0Value when being respectively logical one, then respectively with numerical value (0 1 0...0 0)
2, (0 0 1...0 0)
2... (0 0 0...1 0)
2, (0 0 0...0 1)
2Add in the contents value of this buffer.
4. the method for decipher serial transmission signal as claimed in claim 1, wherein, the initial value of the contents value of this buffer is 0.
5. the method for decipher serial transmission signal as claimed in claim 1, wherein, this method is performed under the situation of not using Interrupt Service Routine by a receiving end, and a master routine of this receiving end reads a bit in a serial clock pulse cycle of this serial clock signal.
6. the method for decipher serial transmission signal as claimed in claim 1, wherein this m bit is an address byte.
7. the method for decipher serial transmission signal as claimed in claim 1, wherein this m bit is a data byte.
8. the method for a decipher serial transmission signal is applied to a receiving end, and this method comprises:
Receive this serial transmission signal, this serial transmission signal comprises a serial datum signal and a serial clock signal;
Whether the accurate position of logic of judging the serial clock signal equals a default value;
When the accurate position of the logic of serial clock signal is this default value, in a serial clock pulse cycle of this serial clock signal, read a bit from this serial data signal;
Store this bit in a buffer, wherein, buffer is in order to m bit of storage;
Judging whether this m bit is stored finishes;
When this m bit storage finishes, send one first Response field bit to a transmission end;
Decipher is stored in m bit in the buffer, and carries out corresponding processing action; And
Wherein, this method is not used Interrupt Service Routine.
9. the method for decipher serial transmission signal as claimed in claim 8, this storing step wherein also comprises:
Generation corresponds to a numerical value of this bit; And
Contents value in this numerical value and the buffer is done additive operation, and the result after this additive operation replaced this contents value and be stored in this buffer.
10. the method for decipher serial transmission signal as claimed in claim 8, wherein the cycle of this serial clock signal for this serial clock signal once enable during and sum during disable.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200710188601XA CN101436167B (en) | 2007-11-16 | 2007-11-16 | Method for interpreting tandem transmitting signal |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200710188601XA CN101436167B (en) | 2007-11-16 | 2007-11-16 | Method for interpreting tandem transmitting signal |
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| Publication Number | Publication Date |
|---|---|
| CN101436167A CN101436167A (en) | 2009-05-20 |
| CN101436167B true CN101436167B (en) | 2011-03-23 |
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| CN200710188601XA Expired - Fee Related CN101436167B (en) | 2007-11-16 | 2007-11-16 | Method for interpreting tandem transmitting signal |
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1622067A (en) * | 2003-11-26 | 2005-06-01 | 北京微辰信息技术有限公司 | Method for high speed SATA interface data recovery and serial-parallel conversion and circuit module |
| US7114093B2 (en) * | 2001-08-29 | 2006-09-26 | Analog Devices, Inc. | Generic architecture and system for a programmable serial port having a shift register and state machine therein |
-
2007
- 2007-11-16 CN CN200710188601XA patent/CN101436167B/en not_active Expired - Fee Related
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7114093B2 (en) * | 2001-08-29 | 2006-09-26 | Analog Devices, Inc. | Generic architecture and system for a programmable serial port having a shift register and state machine therein |
| CN1622067A (en) * | 2003-11-26 | 2005-06-01 | 北京微辰信息技术有限公司 | Method for high speed SATA interface data recovery and serial-parallel conversion and circuit module |
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| CN101436167A (en) | 2009-05-20 |
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