CN101430577B - Computer system capable of automatically regulating time pulse signal frequency - Google Patents

Computer system capable of automatically regulating time pulse signal frequency Download PDF

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Publication number
CN101430577B
CN101430577B CN2007101669677A CN200710166967A CN101430577B CN 101430577 B CN101430577 B CN 101430577B CN 2007101669677 A CN2007101669677 A CN 2007101669677A CN 200710166967 A CN200710166967 A CN 200710166967A CN 101430577 B CN101430577 B CN 101430577B
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frequency
door
control chip
bit
selection information
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CN2007101669677A
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CN101430577A (en
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王卫钢
刘士豪
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Fucheng International Machinery Co.,Ltd.
Jiangxi union Speed Technology Co.,Ltd.
Zhang Kaijun
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Inventec Corp
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Abstract

The invention discloses a computer system which comprises M microprocessors, a frequency control chip and a clock pulse generator. The M microprocessors can generate M pieces of frequency selecting information according to the working frequency. The frequency control chip can execute a succession of calculation processing on the M pieces of frequency selecting information to output one of the M pieces of frequency selecting information according to the calculation result. The clock pulse generator can regulate the frequency of the output clock pulse signals according to the output information of the frequency control chip. The frequency selecting information output by the frequency control chip is sent out by the microprocessor with the lowest working frequency, therefore, the clock pulse signals generated by the clock pulse generator can be applied to the M microprocessors.

Description

Can adjust the computer system of the frequency of clock signal automatically
Technical field
The invention relates to a kind of computer system, and particularly relevant for a kind of computer system that can adjust the frequency of clock signal automatically.
Background technology
In the age of science and technology prosperity now, unavoidable ground, computer has become people's indispensable information processing instrument in life.Microprocessor is one of member indispensable in the computer, and more tends to become strong greatly in response to the function of computer, only possesses the computer system of single microprocessor originally, to develop into the framework of dual micro processor.
Fig. 1 illustrates to having the traditional electrical brain system of dual micro processor.With reference to Fig. 1, traditional electrical brain system 100 comprises microprocessor 110 and 120, selects circuit 130 and clock pulse generator 140.Wherein, microprocessor 110 can produce frequency selection information SEL according to its frequency of operation 11Similarly, microprocessor 120 also can produce frequency selection information SEL according to its frequency of operation 12Afterwards, frequency selection information SEL 11With SEL 12Can be sent to and select circuit 130.
Moreover, select circuit 130 meetings according to switching signal SW 11Level, come output frequency to select information SEL 11With SEL 12One of them.Wherein, when microprocessor 110 is installed in traditional electrical brain system 100, switching signal SW 11Level can be switched to low level, make to select the output information SOUT of circuit 130 11With frequency selection information SEL 11Consistent.In other words, the clock pulse generator 140 of this moment meets generation the clock signal CLK1 of the frequency of operation of microprocessor 110, and is sent to microprocessor 110 and 120.
On the other hand, when 100 installation microprocessors 120 of traditional electrical brain system, switching signal SW 11Level can be switched to high level, make to select the output information SOUT of circuit 130 11With frequency selection information SEL 12Consistent.In other words, the clock pulse generator 140 of this moment meets generation the clock signal CLK1 of the frequency of operation of microprocessor 120, and is sent to microprocessor 120.
It should be noted that microprocessor 110 and 120 can only operate under the clock signal CLK1 that is equal to or less than frequency of operation own.Therefore, when microprocessor 110 and 120 all is installed in traditional electrical brain system 100, and the frequency of operation of microprocessor 110 is during greater than the frequency of operation of microprocessor 120, and the clock signal CLK1 that clock pulse generator 140 is produced can't make microprocessor 120 regular events.
In other words, at the computer system with a plurality of microprocessors, how providing corresponding clock signal to cause a plurality of microprocessors regular events simultaneously in the computer system, has been each manufacturer problem that institute's desire solves of racking one's brains.
Summary of the invention
The invention provides a kind of computer system, utilize the control of frequency control chip to clock pulse generator, the clock signal that causes clock pulse generator to produce can meet a plurality of microprocessors in the computer system.
The present invention proposes a kind of computer system that can adjust the frequency of clock signal automatically, comprises M microprocessor, frequency control chip and clock pulse generator.Wherein, M microprocessor can produce the 1st to M frequency selection information, and the 1st to M frequency selection information is corresponding one to one with M microprocessor respectively.The person, frequency control chip can be compared j frequency selection information with the 1st to N presupposed information in regular turn mutually, with when j frequency selection information is equal to i presupposed information, is i with the setting value of j frequency reference value.Wherein, M and N are the integer greater than 0, and j is integer and 1≤j≤M, and i is integer and 1≤i≤N.
In addition, can't be with the 1st to N presupposed information when one of them compares successfully when j frequency selection information, frequency control chip will produce an alarm signal.Otherwise when the 1st to M frequency selected money all one of them is compared successfully with the 1st to N presupposed information, frequency control chip will compare the 1st size to M frequency reference value, to export the pairing frequency selection information of minimum frequency reference value.
On the other hand, clock pulse generator can be compared the output information of frequency control chip with the 1st to N presupposed information in regular turn mutually, with the frequency with a clock pulse signal be adjusted to N predetermined frequency value one of them.Wherein, i corresponding i predetermined frequency value of presupposed information, (i-1) individual predetermined frequency value is less than i predetermined frequency value.By this, the frequency selection information that frequency control chip is exported will be from the minimum microprocessor of frequency of operation, so M microprocessor can be according to the clock signal normal running that clock pulse generator produced.
In one embodiment of this invention, above-mentioned frequency control chip can be utilized field programmable gate array (fieldprogrammable gate array, FPGA) system, complex programmable logic element (complex programmablelogic device, CPLD) system, baseboard management controller (baseboard management controller, BMC) or other circuit component realize.
The frequency selection information that the present invention utilizes frequency control chip to come each microprocessor is sent carries out a series of calculation process, makes that the minimum frequency selection information that microprocessor sent of frequency of operation can be intercepted out.By this, be controlled by the clock pulse generator of frequency control chip, generation be applicable to the clock signal of each microprocessor.
For above-mentioned feature and advantage of the present invention can be become apparent, preferred embodiment cited below particularly, and conjunction with figs. is described in detail below.
Description of drawings
Fig. 1 illustrates to having the traditional electrical brain system of dual micro processor.
Fig. 2 illustrates the circuit block diagram into the computer system of foundation one embodiment of the invention.
Fig. 3 illustrates and is the operational flowchart in order to key diagram 2 embodiment.
Fig. 4 illustrates the circuit diagram into the frequency control chip of foundation one embodiment of the invention.
Fig. 5 illustrates the circuit block diagram into the computer system of foundation another embodiment of the present invention.
Table 1 illustrates in order to the predetermined frequency value of key diagram 2 embodiment and the table of comparisons of presupposed information.
Table 2 illustrates and is the truth table in order to the frequency control chip of key diagram 4 embodiment.
Embodiment
Before spirit of the present invention being described, suppose that at first computer system of the present invention can dispose one or more microprocessor with embodiment.In addition, no matter be configuration one or a plurality of microprocessor, computer system of the present invention only need provide a clock signal.In other words, be configured in a plurality of microprocessors in the computer system of the present invention with shared same clock signal.As for computer system of the present invention is how to allow the shared same clock signal of microprocessor with different operating frequency, will do further explanation hereinafter.
Fig. 2 illustrates the circuit block diagram into the computer system of foundation one embodiment of the invention.Please refer to Fig. 2, computer system 200 comprises microprocessor 210～220, frequency control chip 230 and clock pulse generator 240.Wherein, frequency control chip 230 is coupled to microprocessor 210～220.Clock pulse generator 240 is coupled to frequency control chip 230 and microprocessor 210～220.
Please continue with reference to Fig. 2, microprocessor 210 produces frequency selection information SEL according to its frequency of operation 1Similarly, microprocessor 220 also can produce frequency selection information SEL according to its frequency of operation 2Then, frequency control chip 230 will be according to the operational flowchart that Fig. 3 illustrated, to frequency selection information SEL 1With frequency selection information SEL 2Advance a series of calculation process, come output frequency to select information SEL with the foundation operation result 1Or frequency selection information SEL 2
Before the principle of work that explains orally frequency control chip 230, suppose the frequency of the clock signal that computer system 200 is sent earlier at this, can only be at 4 predetermined frequency value VF 1～VF 4In select a switching.In addition, as shown in table 1,4 predetermined frequency value VF 1～VF 4Respectively with 4 presupposed information SDE 1～SDE 4Corresponding one to one, and 4 predetermined frequency value VF 1～VF 4Ascending arrangement in regular turn.For example, in the present embodiment, predetermined frequency value VF 1=133MHz, predetermined frequency value VF 2=166MHz, predetermined frequency value VF 3=266MHz, and predetermined frequency value VF 4=333MHz.
Please refer to the thin portion operating process of Fig. 2 and Fig. 3 frequency control chip 230.In step S310, frequency control chip 230 receive frequencies are selected information SEL 1In step S311～S314, frequency control chip 230 is with frequency selection information SEL 1In regular turn with presupposed information SDE 1～SDE 4Comparison mutually.As frequency selection information SEL 1With presupposed information SDE 1～SDE 4When one of them compares successfully, frequency control chip 230 will one of them produce frequency reference value FR through step S315～S318 1
It should be noted that frequency reference value FR 1Numerical value be different along with different comparison results.For example, as frequency selection information SEL 1Be equal to presupposed information SDE 1The time, frequency reference value FR 1Numerical value will be set to 1 (step S315).As frequency selection information SEL 1Be equal to presupposed information SDE 2The time, frequency reference value FR 1Numerical value will be set to 2 (step S316).By that analogy, step S317 and step S318.
Moreover, as frequency selection information SEL 1Can't with presupposed information SDE 1～SDE 4When one of them compares successfully, represent that then microprocessor 210 is not suitable for computer system 200.For example, the frequency of operation of microprocessor 210 is greater than predetermined frequency value VF 1(333MHz).Therefore, Ci Shi frequency control chip 230 will produce alarm signal (step S320).
On the other hand, in step S330, frequency control chip 230 receive frequencies are selected information SEL 2Similarly, in step S331～S334, frequency control chip 230 can be with frequency selection information SEL 2In regular turn with presupposed information SDE 1～SDE 4Comparison mutually.In addition, as frequency selection information SEL 2With presupposed information SDE 1～SDE 4When one of them compares successfully, frequency control chip 230 will one of them produce frequency reference value FR through step S335～S338 2Otherwise frequency control chip 230 will produce alarm signal (step S320).
Further, as frequency selection information SEL 1～SEL 2Separately with presupposed information SDE 1～SDE 4When one of them compares successfully, represent that then microprocessor 210 and 220 is applicable to computer system 200, so the time frequency control chip 230 with comparison frequency reference value FR 1With FR 2Size, with output minimum frequency reference value pairing frequency selection information.Numerical value that it should be noted that the frequency reference value is more little, represents that then the frequency of operation of microprocessor is low more.Change and know, the frequency selection information that frequency control chip 230 is exported is sent by the minimum microprocessor of frequency of operation.
For instance, in step S340, frequency control chip 230 will be differentiated frequency reference value FR 1Whether less than frequency reference value FR 2As frequency reference value FR 1Less than frequency reference value FR 2The time, frequency control chip 230 is with output frequency reference value FR 1Pairing frequency selection information SEL 1(step S341).Relatively, as frequency reference value FR 1Greater than frequency reference value FR 2The time, frequency control chip 230 is with output frequency reference value FR 2Pairing frequency selection information SEL 2(step S342).
Then, please continue with reference to Fig. 2, the output information SOUT of clock pulse generator 240 receive frequency control chips, and produce clock signal CLK according to its received information.For instance, if the output information SOUT of frequency control chip 230 is frequency selection information SEL 1At this moment, clock pulse generator 240 can be with frequency selection information SEL 1With presupposed information SDE 1～SDE 4Comparison mutually.When clock pulse generator 240 is compared out frequency selection information SEL 1Be equal to presupposed information SDE 1The time, it will be adjusted to predetermined frequency value VF to the frequency of clock signal CLK 1(133MHz).
What deserves to be mentioned is, because the frequency selection information that frequency control chip 230 is exported, the microprocessor minimum by frequency of operation sent, therefore clock pulse generator 240 is under the control of frequency control chip, and the clock signal CLK that it produced is with suitable configuration each microprocessor in computer system 200.
In addition, in the present embodiment, this field has knows that usually the knowledgeable can utilize field programmable gate array (fieldprogrammable gate array, FPGA) system, complex programmable logic element (complex programmablelogic device, CPLD) system, baseboard management controller (baseboard management controller, BMC) or other circuit component realize frequency control chip 230.
For instance, if frequency control chip 230 is to be combined by basic logic gate, and at this hypothesis frequency selection information SEL 1～SEL 2And the 1st to the 4th presupposed information SDE 1～SDE 4Comprise 3 bits separately, and the first presupposed information SDE 1Be set to 001, the second presupposed information SDE 2Be set to 011, the three presupposed information SDE 3Be set to 000, and the 4th presupposed information SDE 4Be set under 100 the situation frequency selection information SEL that 230 of frequency control chip can receive 1～SEL 2State, with and the state of corresponding output information SOUT will be shown in the truth table of table 2.By this, the inside structure of frequency control chip 230 can be followed the truth table of table 2, be designed to the circuit diagram that illustrates as Fig. 4.
Please refer to Fig. 4, frequency control chip 230 comprises and door AND 1～AND 6, XOR gate XOR 1～XOR 2, biconditional gate XNOR 1, or the door OR 1～OR 3And not gate NOT 1Wherein, b1[0,2] in order to expression frequency selection information SEL 1In the 1st to the 3rd bit, b2[0,2] in order to expression frequency selection information SEL 2In the 1st to the 3rd bit, and b3[0,2] in order to the 1st to the 3rd bit of the output information SOUT of expression frequency control chip 230.
At this, with door AND 1In order to receive bit b1[2] and bit b2[2].With door AND 2In order to receive bit b1[0] and bit b2[0].With door AND 3In order to receive bit b1[1] and bit b2[1].XOR gate XOR 1In order to receive bit b1[0] and bit b1[1].XOR gate XOR 2In order to receive bit b2[0] and bit b2[1].Or lock OR 2In order to receive bit b1[0] and bit b2[1].With door AND 5In order to receive bit b1[2] and bit b2[0].Not gate NOT 1In order to receive bit b2[1].
On the other hand, with door AND 4Be coupled to and door AND 2Output terminal with door AND 3Output terminal.Biconditional gate XNOR 1Be coupled to XOR gate XOR 1Output terminal and XOR gate XOR 2Output terminal.Or door OR 1Be coupled to and door AND 4Output terminal and biconditional gate XNOR 1Output terminal.With door AND 6Be coupled to and door AND 5The NOT of output terminal Sheffer stroke gate 1Output terminal.Or door OR 3Be coupled to or door OR 2Output terminal with door AND 6Output terminal.By this, frequency control chip 230 can see through and door AND 1Output terminal and or the door OR 1With OR 3Output terminal, produce the pairing frequency selection information of minimum frequency reference value, just the bit b3[0 among the output information SOUT]～b[2].
What deserves to be mentioned is that though computer system has been depicted a possible kenel in Fig. 2 embodiment, know this operator and should know, the number of the microprocessor that computer system disposed can be changed arbitrarily according to deviser's demand.In addition, the frequency of the clock signal that computer system is sent also can be changed the number and the corresponding presupposed information of predetermined frequency value according to deviser's demand.Therefore, the computer system of Fig. 2 embodiment can change the computer system that illustrates as Fig. 5 according to spirit of the present invention.
Please refer to Fig. 5, computer system 500 comprises M microprocessor 510-1～510-M, frequency control chip 530 and clock pulse generator 540.At this, the frequency of the clock signal that computer system 500 is sent can be selected a switching in N predetermined frequency value, and N predetermined frequency value is corresponding one to one with N presupposed information.Wherein, corresponding i the predetermined frequency value of i presupposed information, and (i-1) individual predetermined frequency value is less than i predetermined frequency value, and M and N are the integer greater than 0, and i is integer and 1≤i≤N.
In whole start, microprocessor 510-1～510-M can produce a frequency selection information according to its frequency of operation separately, makes M frequency selection information corresponding one to one with M microprocessor 510-1～510-M.On the other hand, frequency control chip 530 can be compared M frequency selection information with N presupposed information respectively mutually.In addition, when j frequency selection information was equal to i presupposed information, frequency control chip 530 will be the setting value of j frequency reference value i.In other words, when M frequency selected money all one of them is compared successfully with N presupposed information, frequency control chip 530 will produce M frequency reference value.Wherein, j is integer and 1≤j≤M.
On the other hand, selecting money when j frequency can't be with N presupposed information when one of them compares successfully, and frequency control chip 530 will produce an alarm signal, with learn have among microprocessor 510-1～510-M one a plurality ofly be not suitable for computer system 500.Otherwise, can both be with N presupposed information when one of them compares successfully when M frequency selection information, frequency control chip will compare the size of M frequency reference value, with the pairing frequency selection information of output minimum frequency reference value.
Moreover clock pulse generator 540 can be compared the output information of frequency control chip 530 with N presupposed information in regular turn mutually, with the frequency with its clock signal of being exported be adjusted to N predetermined frequency value one of them.By this, microprocessor 510-1～510-M will be respectively that benchmark is operated with the clock signal.Because the frequency selection information that frequency control chip 530 is exported be from the minimum microprocessor of frequency of operation, so the clock signal that clock pulse generator 540 is produced will be applicable to microprocessor 510-1～510-M.
In sum, the frequency selection information that the present invention utilizes frequency control chip to come each microprocessor is sent carries out a series of calculation process, makes that the minimum frequency selection information that microprocessor sent of frequency of operation can be intercepted out.Afterwards, clock pulse generator will receive the output information from frequency control chip, and produce the clock signal that is applicable to each microprocessor.By this, computer system of the present invention will be able to provide each microprocessor a required clock pulse signal to robotization, and then promotes the market competitiveness and the microminiaturized advantage of computer system effectively.
Though the present invention discloses as above with preferred embodiment; right its is not in order to limit the present invention; have in the technical field under any and know the knowledgeable usually; without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention is when with being as the criterion that claim was defined.

Claims (5)

1. the computer system that can adjust the frequency of clock signal automatically comprises:
M microprocessor produces the 1st to M frequency selection information, and corresponding one to one with those microprocessors respectively, M is the integer greater than 0;
One frequency control chip, j frequency selection information compared mutually with the 1st to N presupposed information in regular turn, with when j frequency selection information is equal to i presupposed information, with the setting value of j frequency reference value is i, wherein, when j frequency selection information can't be with the 1st to N presupposed information when one of them compares successfully, this frequency control chip produces an alarm signal, otherwise, this frequency control chip is the 1st size to M frequency reference value relatively, and with the pairing frequency selection information of output minimum frequency reference value, N is the integer greater than 0, j is integer and 1≤j≤M, and i is integer and 1≤i≤N; And
One clock pulse generator, the output information of this frequency control chip is compared mutually with the 1st to N presupposed information in regular turn, with the frequency with a clock pulse signal be adjusted to N predetermined frequency value one of them, wherein, those microprocessors are that benchmark is operated with this clock signal respectively, and i corresponding i predetermined frequency value of presupposed information, (i-1) individual predetermined frequency value is less than i predetermined frequency value.
2. computer system as claimed in claim 1 is characterized in that, this frequency control chip is a field programmable gate array system.
3. computer system as claimed in claim 1 is characterized in that, this frequency control chip is a complex programmable logic element system.
4. computer system as claimed in claim 1 is characterized in that, this frequency control chip is a baseboard management controller.
5. computer system as claimed in claim 1, it is characterized in that, as M=2, N=4, and when the 1st to the 2nd frequency selection information and the 1st to the 4th presupposed information comprise 3 bits separately, b1[x] in order to represent the x bit of the 1st frequency selection information, b2[x] in order to represent the x bit of the 2nd frequency selection information, this frequency control chip comprises:
One first with door, in order to receive bit b1[2] with bit b2[2];
One second with door, in order to receive bit b1[0] with bit b2[0];
One the 3rd with door, in order to receive bit b1[1] with bit b2[1];
One the 4th with the door, be coupled to this second with the door output terminal with the 4th with output terminal;
One first XOR gate is in order to receive bit b1[0] and bit b1[1];
One second XOR gate is in order to receive bit b2[0] and bit b2[1];
One first biconditional gate is coupled to the output terminal of this first XOR gate and the output terminal of this second XOR gate;
One first or the door, be coupled to the 4th with the door output terminal and the output terminal of this first biconditional gate;
One second or door, in order to receive bit b1[0] with bit b2[1];
One the 5th with door, in order to receive bit b1[2] with bit b2[0];
One not gate is in order to receive bit b2[1];
One the 6th with the door, be coupled to the 5th with the door output terminal and the output terminal of this not gate; And
One the 3rd or the door, be coupled to this second or the door output terminal with the 6th with output terminal,
Wherein, this frequency control chip see through this first with door, this first or door and the 3rd or the output terminal of door, produce the pairing frequency selection information of minimum frequency reference value, x is integer and 0≤x≤2.
CN2007101669677A 2007-11-08 2007-11-08 Computer system capable of automatically regulating time pulse signal frequency Expired - Fee Related CN101430577B (en)

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0130469A2 (en) * 1983-06-29 1985-01-09 International Business Machines Corporation Internally distributed monitoring system
CN1372189A (en) * 2001-02-26 2002-10-02 微星科技股份有限公司 Method for instant raising CPU frequency
CN1739080A (en) * 2001-09-28 2006-02-22 英特尔公司 Method and apparatus for adjusting the voltage and frequency to minimize power dissipation in a multiprocessor system

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0130469A2 (en) * 1983-06-29 1985-01-09 International Business Machines Corporation Internally distributed monitoring system
CN1372189A (en) * 2001-02-26 2002-10-02 微星科技股份有限公司 Method for instant raising CPU frequency
CN1739080A (en) * 2001-09-28 2006-02-22 英特尔公司 Method and apparatus for adjusting the voltage and frequency to minimize power dissipation in a multiprocessor system

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