CN101430577B - Computer system capable of automatically adjusting frequency of clock signal - Google Patents

Abstract

The invention discloses a computer system, which comprises M microprocessors, a frequency control chip and a clock generator. The M microprocessors generate M frequency selection messages according to the working frequencies of the microprocessors. The frequency control chip performs a series of operations on the M pieces of frequency selection information to output one of the M pieces of frequency selection information according to the operation result. The clock generator adjusts the frequency of the output clock signal according to the output information of the frequency control chip. The frequency selection information output by the frequency control chip is sent by the microprocessor with the lowest working frequency, and the clock pulse signal generated by the clock pulse generator is suitable for M microprocessors.

Description

A computer system that can automatically adjust the frequency of the clock signal

technical field

The present invention relates to a computer system, and in particular to a computer system capable of automatically adjusting the frequency of a clock signal.

Background technique

In today's era of advanced technology, it is inevitable that computers have become an indispensable information processing tool in people's lives. The microprocessor is one of the indispensable components in the computer, and as the functions of the computer become more and more powerful, the computer system originally only equipped with a single microprocessor has been developed into a dual-microprocessor architecture.

FIG. 1 shows a conventional computer system with dual microprocessors. Referring to FIG. 1 , a conventional computer system 100 includes microprocessors 110 and 120 , a selection circuit 130 and a clock generator 140 . Wherein, the microprocessor 110 generates frequency selection information SEL ₁₁ according to its operating frequency. Similarly, the microprocessor 120 will also generate frequency selection information SEL ₁₂ according to its operating frequency. Afterwards, the frequency selection information _SEL11 and _SEL12 are sent to the selection circuit 130 .

Furthermore, the selection circuit 130 outputs one of the frequency selection information SEL ₁₁ and SEL ₁₂ according to the level of the switching signal SW ₁₁ . Wherein, when the microprocessor 110 is installed in the conventional computer system 100 , the level of the switch signal SW ₁₁ will be switched to a low level, so that the output information SOUT ₁₁ of the selection circuit 130 is consistent with the frequency selection information SEL ₁₁ . In other words, the clock generator 140 at this time will generate the clock signal CLK1 conforming to the operating frequency of the microprocessor 110 and transmit it to the microprocessors 110 and 120 .

On the other hand, when only the microprocessor 120 is installed in the conventional computer system 100 , the switching signal SW ₁₁ is switched to a high level, so that the output information SOUT ₁₁ of the selection circuit 130 is consistent with the frequency selection information SEL ₁₂ . In other words, the clock generator 140 at this time will generate the clock signal CLK1 conforming to the operating frequency of the microprocessor 120 and transmit it to the microprocessor 120 .

It should be noted that the microprocessors 110 and 120 can only operate under the clock signal CLK1 whose operating frequency is equal to or lower than its own. Therefore, when the microprocessors 110 and 120 are installed in the conventional computer system 100, and the operating frequency of the microprocessor 110 is higher than the operating frequency of the microprocessor 120, the clock signal CLK1 generated by the clock generator 140 will not be able to use The microprocessor 120 operates normally.

In other words, for a computer system with multiple microprocessors, how to provide a corresponding clock signal to cause multiple microprocessors in the computer system to operate normally at the same time has been a problem that various manufacturers have racked their brains to solve. question.

Contents of the invention

The invention provides a computer system, which utilizes the frequency control chip to control the clock generator, so that the clock signal generated by the clock generator can match multiple microprocessors in the computer system.

The invention proposes a computer system capable of automatically adjusting the frequency of a clock signal, which includes M microprocessors, a frequency control chip and a clock generator. Wherein, the M microprocessors will generate the 1st to the Mth frequency selection information, and the 1st to the Mth frequency selection information are respectively one-to-one corresponding to the M microprocessors. In addition, the frequency control chip compares the j-th frequency selection information with the 1st to N-th preset information in sequence, so that when the j-th frequency selection information is equal to the i-th preset information, the The values of the j frequency reference values are set to i. Wherein, M and N are integers greater than 0, j is an integer and 1≤j≤M, and i is an integer and 1≤i≤N.

In addition, when the jth frequency selection information fails to be successfully compared with one of the 1st to Nth preset information, the frequency control chip will generate a warning signal. Conversely, when the 1st to Mth frequency selection information is successfully compared with one of the 1st to Nth preset information, the frequency control chip will compare the magnitude of the 1st to Mth frequency reference values to output Frequency selection information corresponding to the minimum frequency reference value.

On the other hand, the clock generator compares the output information of the frequency control chip with the 1st to Nth preset information in order to adjust the frequency of a clock signal to one of the N frequency preset values. . Wherein, the i-th preset information corresponds to the i-th frequency preset value, and the (i-1)th frequency preset value is smaller than the i-th frequency preset value. In this way, the frequency selection information output by the frequency control chip will come from the microprocessor with the lowest operating frequency, so the M microprocessors will be able to operate normally according to the clock signal generated by the clock generator.

In an embodiment of the present invention, the above-mentioned frequency control chip can utilize a field programmable gate array (fieldprogrammable gate array, FPGA) system, a complex programmable logic device (complex programmable logic device, CPLD) system, a baseboard management controller (baseboard) management controller, BMC) or other circuit components.

The invention utilizes the frequency control chip to perform a series of operations on the frequency selection information sent by each microprocessor, so that the frequency selection information sent by the microprocessor with the lowest operating frequency can be intercepted. In this way, the clock generator controlled by the frequency control chip will generate a clock signal suitable for each microprocessor.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, preferred embodiments are specifically cited below and described in detail with accompanying drawings.

Description of drawings

FIG. 1 shows a conventional computer system with dual microprocessors.

FIG. 2 is a circuit block diagram of a computer system according to an embodiment of the present invention.

FIG. 3 is a flowchart illustrating the operation of the embodiment shown in FIG. 2 .

FIG. 4 is a circuit diagram of a frequency control chip according to an embodiment of the invention.

FIG. 5 is a circuit block diagram of a computer system according to another embodiment of the present invention.

Table 1 is a comparison table for illustrating frequency preset values and preset information in the embodiment of FIG. 2 .

Table 2 is a truth table for illustrating the frequency control chip of the embodiment shown in FIG. 4 .

Detailed ways

Before describing the spirit of the present invention with an embodiment, it is first assumed that the computer system of the present invention can be configured with one or more microprocessors. In addition, no matter one or more microprocessors are configured, the computer system of the present invention only needs to provide one clock signal. In other words, multiple microprocessors configured in the computer system of the present invention share the same clock signal. As for how the computer system of the present invention allows microprocessors with different operating frequencies to share the same clock signal, it will be further described below.

FIG. 2 is a circuit block diagram of a computer system according to an embodiment of the present invention. Referring to FIG. 2 , the computer system 200 includes microprocessors 210 - 220 , a frequency control chip 230 and a clock generator 240 . Wherein, the frequency control chip 230 is coupled to the microprocessors 210-220. The clock generator 240 is coupled to the frequency control chip 230 and the microprocessors 210 - 220 .

Please continue to refer to FIG. 2 , the microprocessor 210 generates frequency selection information SEL ₁ according to its operating frequency. Similarly, the microprocessor 220 will also generate frequency selection information SEL ₂ according to its operating frequency. Next, the frequency control chip 230 will perform a series of operations _on the frequency selection information SEL ₁ and the frequency selection information SEL ₂ according to the operation flow chart shown in FIG. Information SEL ₂ .

Before explaining the working principle of the frequency control chip 230 , it is assumed that the frequency of the clock signal sent by the computer system 200 can only be switched among four preset frequency values VF ₁ -VF ₄ . In addition, as shown in Table 1, the four preset frequency values VF ₁ to VF ₄ correspond to the four preset information SDE ₁ to SDE ₄ respectively, and the four preset frequency values VF ₁ to VF ₄ are determined by Arranged from smallest to largest. For example, in this embodiment, the preset frequency value VF ₁ =133 MHz, the preset frequency value VF ₂ =166 MHz, the preset frequency value VF ₃ =266 MHz, and the preset frequency value VF ₄ =333 MHz.

Please refer to FIG. 2 and FIG. 3 to see the detailed operation flow of the frequency control chip 230 . In step S310 , the frequency control chip 230 receives the frequency selection information SEL ₁ . In steps S311-S314, the frequency control chip 230 compares the frequency selection information SEL ₁ with the preset information SDE ₁ -SDE ₄ in sequence. When the comparison between the frequency selection information SEL ₁ and one of the preset information SDE ₁ -SDE ₄ is successful, the frequency control chip 230 will generate a frequency reference value FR ₁ through one of steps S315 - S318.

It should be noted that the value of the frequency reference value FR ₁ varies with different comparison results. For example, when the frequency selection information SEL ₁ is equal to the preset information SDE ₁ , the value of the frequency reference FR ₁ is set to 1 (step S315 ). When the frequency selection information SEL ₁ is equal to the preset information SDE ₂ , the value of the frequency reference value FR ₁ is set to 2 (step S316). By analogy, step S317 and step S318.

Furthermore, when the frequency selection information SEL ₁ cannot be successfully compared with one of the preset information SDE ₁ -SDE ₄ , it means that the microprocessor 210 is not suitable for the computer system 200 . For example, the working frequency of the microprocessor 210 is higher than the preset frequency VF ₁ (333 MHz). Therefore, the frequency control chip 230 at this time will generate a warning signal (step S320).

On the other hand, in step S330, the frequency control chip 230 receives the frequency selection information SEL ₂ . Similarly, in steps S331-S334, the frequency control chip 230 compares the frequency selection information SEL ₂ with the preset information SDE ₁ -SDE ₄ in sequence. In addition, when the comparison between the frequency selection information SEL ₂ and one of the preset information SDE ₁ -SDE ₄ is successful, the frequency control chip 230 will generate a frequency reference value FR ₂ through one of steps S335 - S338. Otherwise, the frequency control chip 230 will generate a warning signal (step S320).

Further, when the frequency selection information SEL ₁ - SEL ₂ is compared with one of the preset information SDE ₁ - SDE ₄ successfully, it means that the microprocessors 210 and 220 are suitable for the computer system 200, so the frequency at this time The control chip 230 compares the frequency reference values FR ₁ and FR ₂ to output frequency selection information corresponding to the minimum frequency reference value. It should be noted that the smaller the value of the frequency reference value, the lower the operating frequency of the microprocessor. In other words, the frequency selection information output by the frequency control chip 230 is sent by the microprocessor with the lowest operating frequency.

For example, in step S340 , the frequency control chip 230 will determine whether the frequency reference value FR ₁ is smaller than the frequency reference value FR ₂ . When the frequency reference value _FR1 is smaller than the frequency reference value _FR2 , the frequency control chip 230 will output the frequency selection information _{SEL1 corresponding to the frequency reference value FR1 (} step S341). Relatively, when the frequency reference value _FR1 is greater than the frequency reference value _FR2 , the frequency control chip 230 will output the frequency selection information _{SEL2 corresponding to the frequency reference value FR2 (} step S342).

Next, please continue to refer to FIG. 2 , the clock generator 240 receives the output information SOUT of the frequency control chip, and generates the clock signal CLK according to the received information. For example, suppose the output information SOUT of the frequency control chip 230 is the frequency selection information SEL ₁ . At this time, the clock generator 240 compares the frequency selection information SEL ₁ with the preset information SDE ₁ -SDE ₄ . When the clock generator 240 compares that the frequency selection information SEL ₁ is equal to the preset information SDE ₁ , it adjusts the frequency of the clock signal CLK to a preset frequency VF ₁ (133 MHz).

It is worth mentioning that since the frequency selection information output by the frequency control chip 230 is sent by the microprocessor with the lowest operating frequency, the clock signal generated by the clock generator 240 under the control of the frequency control chip CLK will be applicable to each microprocessor configured in the computer system 200 .

In addition, in this embodiment, those with ordinary knowledge in this field can use field programmable gate array (fieldprogrammable gate array, FPGA) system, complex programmable logic device (complex programmable logic device, CPLD) system, baseboard management controller (baseboard management controller, BMC) or other circuit components to implement the frequency control chip 230.

For example, if the frequency control chip 230 is composed of basic logic gates, and it is assumed here that the frequency selection information SEL ₁ ˜ SEL ₂ and the first to fourth preset information SDE ₁ ˜ SDE ₄ each include 3 bit, and the first preset information SDE ₁ is set to 001, the second preset information SDE ₂ is set to 011, the third preset information SDE ₃ is set to 000, and the fourth preset information SDE When ₄ is set to 100, the state of the frequency selection information SEL ₁ -SEL ₂ received by the frequency control chip 230 and the state of the corresponding output information SOUT will be shown in the truth table of Table 2. Thus, the internal structure of the frequency control chip 230 can be designed as the circuit diagram shown in FIG. 4 according to the truth table in Table 2.

Referring to FIG. 4 , the frequency control chip 230 includes AND gates AND ₁ -AND ₆ , exclusive OR gates XOR ₁ -XOR ₂ , exclusive NOR gate XNOR ₁ , OR gates OR ₁ -OR ₃ and NOT gate NOT ₁ . Among them, b1[0,2] is used to represent the first to third bits in the frequency selection information SEL ₁ , b2[0,2] is used to represent the first to third bits in the frequency selection information SEL ₂ , And b3[0,2] is used to represent the first to third bits of the output information SOUT of the frequency control chip 230 .

Here, the AND gate AND ₁ is used to receive the bit b1[2] and the bit b2[2]. The AND gate AND ₂ is used to receive the bit b1[0] and the bit b2[0]. The AND gate AND ₃ is used to receive the bit b1[1] and the bit b2[1]. The XOR gate XOR ₁ is used to receive bit b1[0] and bit b1[1]. The XOR gate XOR ₂ is used to receive bit b2[0] and bit b2[1]. The OR gate OR ₂ is used to receive bit b1[0] and bit b2[1]. The AND gate AND ₅ is used to receive the bit b1[2] and the bit b2[0]. The NOT gate NOT ₁ is used to receive the bit b2[1].

On the other hand, the AND gate AND ₄ is coupled to the output terminal of the AND gate AND ₂ and the output terminal of the AND gate AND ₃ . The XNOR gate XNOR ₁ is coupled to the output end of the XOR gate XOR ₁ and the output end of the XOR gate XOR ₂ . The OR gate OR ₁ is coupled to the output terminal of the AND gate AND ₄ and the output terminal of the XNOR gate XNOR ₁ . The AND gate AND ₆ is coupled to the output terminal of the AND gate AND ₅ and the NOT ₁ output terminal of the NAND gate. The OR gate OR ₃ is coupled to the output terminal of the OR gate OR ₂ and the output terminal of the AND gate AND ₆ . In this way, the frequency control chip 230 can generate the frequency selection information corresponding to the minimum frequency reference value through the output terminal of the AND gate AND ₁ , and the output terminals of the OR gates OR ₁ and OR ₃ , that is, the output information SOUT The bits b3[0]~b[2] of the

It is worth mentioning that although a possible configuration of the computer system has been depicted in the embodiment of FIG. The demand can be replaced arbitrarily. In addition, the frequency of the clock signal sent by the computer system can also change the number of frequency presets and the corresponding preset information according to the needs of the designer. Therefore, the computer system in the embodiment shown in FIG. 2 can be changed into the computer system shown in FIG. 5 according to the spirit of the present invention.

Referring to FIG. 5 , the computer system 500 includes M microprocessors 510 - 1 - 510 -M, a frequency control chip 530 and a clock generator 540 . Here, the frequency of the clock signal sent by the computer system 500 can be switched among N frequency preset values, and the N frequency preset values correspond to the N preset information one-to-one. Wherein, the i-th preset information corresponds to the i-th frequency preset value, and the (i-1)th frequency preset value is smaller than the i-th frequency preset value, M and N are integers greater than 0, and i is an integer And 1≤i≤N.

In the overall operation, the microprocessors 510-1~510-M will each generate a frequency selection information according to their operating frequency, so that the M frequency selection information is one-to-one with the M microprocessors 510-1~510-M correspond. On the other hand, the frequency control chip 530 compares the M pieces of frequency selection information with the N pieces of preset information respectively. In addition, when the j th frequency selection information is equal to the i th preset information, the frequency control chip 530 will set the value of the j th frequency reference value as i. In other words, when the M frequency selection information is successfully compared with one of the N preset information, the frequency control chip 530 will generate M frequency reference values. Wherein, j is an integer and 1≤j≤M.

On the other hand, when the j-th frequency selection information cannot be successfully compared with one of the N preset information, the frequency control chip 530 will generate a warning signal to know the One or more are not applicable to the computer system 500 . Conversely, when all the M pieces of frequency selection information are successfully compared with one of the N pieces of preset information, the frequency control chip will compare the magnitudes of the M frequency reference values to output the frequency selection information corresponding to the minimum frequency reference value.

Furthermore, the clock generator 540 compares the output information of the frequency control chip 530 with the N preset information in order to adjust the frequency of the clock signal output by it to one of the N preset frequency values. one. In this way, the microprocessors 510-1˜510-M will respectively operate based on the clock signal. Since the frequency selection information output by the frequency control chip 530 comes from the microprocessor with the lowest operating frequency, the clock signal generated by the clock generator 540 is suitable for the microprocessors 510-1˜510-M.

To sum up, the present invention uses the frequency control chip to perform a series of operations on the frequency selection information sent by each microprocessor, so that the frequency selection information sent by the microprocessor with the lowest operating frequency can be intercepted. Afterwards, the clock generator will receive the output information from the frequency control chip and generate clock signals suitable for each microprocessor. Thereby, the computer system of the present invention can automatically provide a clock signal required by each microprocessor, thereby effectively enhancing the market competitiveness and miniaturization advantages of the computer system.

Although the present invention has been disclosed above with a preferred embodiment, it is not intended to limit the present invention. Anyone with ordinary knowledge in the art can make some modifications and changes without departing from the spirit and scope of the present invention. modification, so the protection scope of the present invention should be defined by the claims.

Claims (5)

1. the computer system that can adjust the frequency of clock signal automatically comprises:

M microprocessor produces the 1st to M frequency selection information, and corresponding one to one with those microprocessors respectively, M is the integer greater than 0;

One frequency control chip, j frequency selection information compared mutually with the 1st to N presupposed information in regular turn, with when j frequency selection information is equal to i presupposed information, with the setting value of j frequency reference value is i, wherein, when j frequency selection information can't be with the 1st to N presupposed information when one of them compares successfully, this frequency control chip produces an alarm signal, otherwise, this frequency control chip is the 1st size to M frequency reference value relatively, and with the pairing frequency selection information of output minimum frequency reference value, N is the integer greater than 0, j is integer and 1≤j≤M, and i is integer and 1≤i≤N; And

One clock pulse generator, the output information of this frequency control chip is compared mutually with the 1st to N presupposed information in regular turn, with the frequency with a clock pulse signal be adjusted to N predetermined frequency value one of them, wherein, those microprocessors are that benchmark is operated with this clock signal respectively, and i corresponding i predetermined frequency value of presupposed information, (i-1) individual predetermined frequency value is less than i predetermined frequency value.

2. computer system as claimed in claim 1 is characterized in that, this frequency control chip is a field programmable gate array system.

3. computer system as claimed in claim 1 is characterized in that, this frequency control chip is a complex programmable logic element system.

4. computer system as claimed in claim 1 is characterized in that, this frequency control chip is a baseboard management controller.

5. computer system as claimed in claim 1, it is characterized in that, as M=2, N=4, and when the 1st to the 2nd frequency selection information and the 1st to the 4th presupposed information comprise 3 bits separately, b1[x] in order to represent the x bit of the 1st frequency selection information, b2[x] in order to represent the x bit of the 2nd frequency selection information, this frequency control chip comprises:

One first with door, in order to receive bit b1[2] with bit b2[2];

One second with door, in order to receive bit b1[0] with bit b2[0];

One the 3rd with door, in order to receive bit b1[1] with bit b2[1];

One the 4th with the door, be coupled to this second with the door output terminal with the 4th with output terminal;

One first XOR gate is in order to receive bit b1[0] and bit b1[1];

One second XOR gate is in order to receive bit b2[0] and bit b2[1];

One first biconditional gate is coupled to the output terminal of this first XOR gate and the output terminal of this second XOR gate;

One first or the door, be coupled to the 4th with the door output terminal and the output terminal of this first biconditional gate;

One second or door, in order to receive bit b1[0] with bit b2[1];

One the 5th with door, in order to receive bit b1[2] with bit b2[0];

One not gate is in order to receive bit b2[1];

One the 6th with the door, be coupled to the 5th with the door output terminal and the output terminal of this not gate; And

One the 3rd or the door, be coupled to this second or the door output terminal with the 6th with output terminal,

Wherein, this frequency control chip see through this first with door, this first or door and the 3rd or the output terminal of door, produce the pairing frequency selection information of minimum frequency reference value, x is integer and 0≤x≤2.

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