CN101427318A - Method and system to increase the write cycle of solid state memory - Google Patents

Method and system to increase the write cycle of solid state memory Download PDF

Info

Publication number
CN101427318A
CN101427318A CNA2007800139474A CN200780013947A CN101427318A CN 101427318 A CN101427318 A CN 101427318A CN A2007800139474 A CNA2007800139474 A CN A2007800139474A CN 200780013947 A CN200780013947 A CN 200780013947A CN 101427318 A CN101427318 A CN 101427318A
Authority
CN
China
Prior art keywords
state
solid
file
volatile memory
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CNA2007800139474A
Other languages
Chinese (zh)
Inventor
符廷彬
陈胜利
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
TERCO 2000 INTERNATIONAL CO Ltd
Original Assignee
TERCO 2000 INTERNATIONAL CO Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by TERCO 2000 INTERNATIONAL CO Ltd filed Critical TERCO 2000 INTERNATIONAL CO Ltd
Publication of CN101427318A publication Critical patent/CN101427318A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/023—Free address space management
    • G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
    • G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1016—Performance improvement
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/72—Details relating to flash memory management
    • G06F2212/7203—Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/061—Improving I/O performance
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
    • G06F3/0656—Data buffering arrangements
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0673—Single storage device
    • G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]

Abstract

A method of reducing a number of write cycles to solid-state, non- volatile memory is disclosed. The method comprises uploading at least one file from the solid-state, non volatile memory to a memory buffer of a computer; processing the at least one file in the memory buffer using a processor of the computer; and, upon finalization of the processing, writing the processed at least one file to the solid-state, non-volatile memory.

Description

What increase solid-state memory writes the round-robin method and system
Technical field
What the present invention relates to increase solid-state memory writes the round-robin method and system, more specifically rather than removing property ground, relate to increase solid-state, non-volatile memory write the round-robin method and system.
Background technology
For many years, mass memory is used always by hard disk drive and tape storage medium monopolization.Now, they just are being subjected to challenge solid-state, nonvolatile memory.With regard to its processing that can carry out, it is advanced more that solid-state, non-volatile memory has become, has higher capacity and lower manufacturing cost.Use more application of sort memory to be discerned frequently.But there is restriction in sort memory.Write or program cycles number of times (cycle times) significantly reduces, and chip size (die size) is reduced to unit size (cell size), for example 50nm.This causes writing circulation and reduces.Like this, storer will break down quickly.Especially all the more so for the multilevel-cell in the nand flash memory.Like this, they reduce greatly for the applicability that for example requires frequently and in a large number to write the application of round-robin mass memory.This is for built-in and external memory storage.
Summary of the invention
According to illustrative aspects, a kind of round-robin method of writing that reduces a large amount of to solid-state, non-volatile memory is provided, described method comprises:
At least one file is uploaded to the memory buffer unit of computing machine from described solid-state, non-volatile memory;
Use the processor of described computing machine to handle described at least one file in the described memory buffer unit;
The described processing in case terminate, at least one file that just will handle writes described solid-state, non-volatile memory.
According to another illustrative aspects, a kind of a large amount of round-robin systems of writing to solid-state, non-volatile memory that are used to reduce are provided, described system comprises:
Can be uploaded at least one file the memory buffer unit of computing machine from described solid-state, non-volatile memory;
Described at least one file uses the processor of described computing machine to handle in described memory buffer unit;
The described processing in case terminate, at least one file of handling just is written into described solid-state, non-volatile memory.
For above-mentioned two aspects, finishing of processing can be following at least a kind of situation: when whole process is finished; When user's close file; Selected and when excitation when the Save icon; And, after the period predetermined or that the user selects.Before handling the termination back and writing at least one file of described processing, can carry out error correction.Error correction can be carried out in memory buffer unit and/or solid-state, non-volatile memory.Solid-state, non-volatile memory can in build in the computing machine and can be operatively coupled on the processor by microcontroller, perhaps can be external unit with microcontroller.External unit can be connected to computing machine in operation.Solid-state, non-volatile memory can be nand flash memory and can have the cellular construction of selecting from individual unit and/or multilevel-cell.Memory buffer unit can comprise at least one in RAM, nand flash memory and the hard disk drive.After at least one file of handling was written into solid-state, non-volatile memory, described file at least can be deleted from memory buffer unit.
According to another illustrative aspects of the present invention, the software setting that can operate on processor is provided, described software setting comprises processor is configured to carry out one or more functions to carry out the computer program of said method.
Description of drawings
To be described by some non-limiting examples now, this is described with reference to appended indicative icon.In the accompanying drawings:
Fig. 1 is the perspective schematic view that the part of exemplary embodiment is analysed and observe;
Fig. 2 is the block diagram that may be provided with that illustrates exemplary embodiment; And
Fig. 3 is the process flow diagram that is used for the operation of exemplary embodiment.
Embodiment
As shown in Figure 1, computing machine 100 has monitor 102, keyboard 104 and mouse 106.Can use other peripherals (not shown).As an alternative, computing machine 100 can be kneetop computer, notebook or flat computer, or PDA.Computing machine 100 can have built-in solid-state, non-volatile memory 108 and/or contain the external unit 200 of solid-state, non-volatile memory.Solid-state, non-volatile memory for example can be a nand flash memory.It can be individual unit structure and/or multilevel-cell structure.
Fig. 2 illustrates block diagram.Here, computing machine 100 has CPU (central processing unit) 110 and memory buffer unit 112.Memory buffer unit 112 can separate with CPU 110, but is operatively coupled to CPU 110; Perhaps can with 110 one-tenth integral body of CPU.
Solid-state, non-volatile memory 108,200 has microcontroller 202 and a plurality of memory chip 204 that is operatively coupled to microcontroller 202.The number and the size of memory chip 204 are unimportant.For built-in storage 108, microcontroller 202 will by any suitable interface operation be connected to CPU 110, described interface includes but not limited to: ATA, SATA or IDE.For External memory equipment 200, microcontroller 202 will be operatively coupled to connector 206 and connector driver (not shown), for example USB connector 206 and driver; And CPU 110 will be operatively coupled to port one 14, for example USB port.When connector 206 access interface 114, microcontroller 202 is operatively coupled to CPU 110.
When in the computing machine 100 processing memory chips 204 storage data the time, there are many circulations of writing in memory chip 204.This can shorten the cycle life of writing of memory chip 204 greatly.Therefore, during this was handled, all data were written into and store in the memory buffer unit 112.When finishing dealing with, the data of termination are downloaded to the memory chip 204 from memory buffer unit 112 via CPU 110 and microcontroller 202.Termination can be the one or more situations in following:
(a) when entire process is finished;
(b) when user's close file;
(c) selected and when excitation when the Save icon;
(d) after the period predetermined or that the user selects;
(e) when memory buffer unit 112 is in predetermined volumes (number percent of numeral or its total volume) (for example, 50% of the 10GB impact damper full or 5GB).
Memory buffer unit 112 can be any appropriate format that comprises PAM, nand flash memory, hard disk etc.The data of uploading from memory chip 204 when File Open can all store into the memory buffer unit 112, and perhaps only the change of data is stored in the memory buffer unit 112, then in download and the write store chip 204.
CPU 110 is preferably used in control and treatment, so does because it has better Functional Capability.Microcontroller 202 does not have the ability of carrying out necessary function usually.
In addition, before data are written into memory chip 204 from memory buffer unit 112, are preferably in when data still are arranged in memory buffer unit 112 and carry out error correction, so as data be downloaded/be correct during write store chip 204.In addition or as an alternative, error correction can be after with data download/write store chip 204 and data carry out when being arranged in memory chip 204.
As shown in Figure 3, when handling beginning (300) and file (one or more) selected (301), file (one or more) is uploaded to (302) the memory buffer unit 112 from memory chip 204.File (one or more) is handled (303) by CPU 110 in memory buffer unit 112.CPU 110 proposes a plurality of inquiries subsequently in succession.They can in any order or make up:
Handle and whether finish (304)?
Whether is file closed (305)?
Whether select " preservation " function (306)?
Scheduled time slot expire (307)?
Does is impact damper in it and preset capacity level (308)?
If each all be a "No" in (304) to (308), then short preset (309) after the time-delay, (304) are returned in processing.Yet,, carry out error correction (310) and with in the writing data into memory chip 202 (311) if any is a "Yes" in (304) to (308).If do not have further processing in the impact damper 112, then can from impact damper 112, clear data (312) to data.Processing subsequent finishes (313).
The present invention also expands to following software setting, and described software setting can be operated on processor 110 and comprise processor 110 is configured to carry out one or more functions so that the computer program that said method can be carried out.
Though described exemplary embodiment in the explanation in front, it should be appreciated by those skilled in the art that without departing from the invention, can make many design detailss, structure and/or operational change.

Claims (19)

1. a minimizing is in a large number to the round-robin method of writing of solid-state, non-volatile memory, and described method comprises:
At least one file is uploaded to the memory buffer unit of computing machine from described solid-state, non-volatile memory;
Use the processor of described computing machine to handle described at least one file in the described memory buffer unit;
The described processing in case terminate, at least one file that just will handle writes described solid-state, non-volatile memory.
2. the method for claim 1, the termination of wherein said processing are from by at least a situation of selecting the following set of forming:
(a) when entire process is finished;
(b) when user's close file;
(c) selected and when excitation when the Save icon; And
(d) after the period predetermined or that the user selects;
3. method as claimed in claim 1 or 2 wherein, in described processing termination back and before writing at least one file of described processing, is carried out error correction.
4. method as claimed in claim 3 is wherein carried out error correction: described memory buffer unit, and described solid-state, non-volatile memory at least one of selecting from the set of being made of the following.
5. as any described method in the claim 1 to 4, build in the described computing machine and in the wherein said solid-state, non-volatile memory and be operatively coupled on the described processor by microcontroller.
6. as any described method in the claim 1 to 4, wherein said solid-state, non-volatile memory is the external unit with microcontroller, and described external unit operatively can be connected on the described computing machine.
7. as any described method in the claim 1 to 6, wherein said solid-state, non-volatile memory is a nand flash memory, and described nand flash memory has the cellular construction of selecting from the set of being made up of the following: individual unit, and multilevel-cell.
8. as any described method in the claim 1 to 7, wherein said memory buffer unit comprises at least one that selects from the set of being made up of the following: RAM, nand flash memory, and hard disk drive.
9. as any described method in the claim 1 to 8, wherein after at least one file with described processing writes described solid-state, non-volatile memory, from described memory buffer unit, delete described at least one file.
10. one kind is used to reduce a large amount of round-robin systems of writing to solid-state, non-volatile memory, and described system comprises:
Can be uploaded at least one file the memory buffer unit of computing machine from described solid-state, non-volatile memory;
Described at least one file uses the processor of described computing machine to handle in described memory buffer unit; And
The described processing in case terminate, at least one file of handling just is written into described solid-state, non-volatile memory.
11. system as claimed in claim 10, the termination of wherein said processing are from by at least a situation of selecting the following set of forming:
(e) when entire process is finished;
(f) when user's close file;
(g) selected and when excitation when the Save icon; And
(h) after the period predetermined or that the user selects;
12., wherein, carry out error correction in described processing termination back and before writing at least one file of described processing as claim 10 or 11 described systems.
13. system as claimed in claim 12 wherein carries out error correction: described memory buffer unit, and described solid-state, non-volatile memory at least one of selecting from the set of being made of the following.
14., build in the described computing machine and in the wherein said solid-state, non-volatile memory and be operatively coupled on the described processor by microcontroller as any described system in the claim 10 to 13.
15. as any described system in the claim 10 to 13, wherein said solid-state, non-volatile memory is the external unit with microcontroller, described external unit operatively can be connected on the described computing machine.
16. as any described system in the claim 10 to 15, wherein said solid-state, non-volatile memory is a nand flash memory, described nand flash memory has the cellular construction of selecting from the set of being made up of the following: individual unit, and multilevel-cell.
17. as any described system in the claim 10 to 16, wherein said memory buffer unit comprises at least one that selects from the set of being made up of the following: RAM, nand flash memory, and hard disk drive.
18., wherein after at least one file with described processing writes described solid-state, non-volatile memory, from described memory buffer unit, delete described at least one file as any described system in the claim 10 to 17.
19. the software setting that can operate on processor, described software setting comprise and described processor is configured to carry out one or more functions requires any computer program of method of 1 to 9 with enforcement of rights.
CNA2007800139474A 2007-08-17 2007-08-17 Method and system to increase the write cycle of solid state memory Pending CN101427318A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/SG2007/000263 WO2008111912A1 (en) 2007-08-17 2007-08-17 Method and system to increase the write cycle of solid state memory

Publications (1)

Publication Number Publication Date
CN101427318A true CN101427318A (en) 2009-05-06

Family

ID=39759767

Family Applications (1)

Application Number Title Priority Date Filing Date
CNA2007800139474A Pending CN101427318A (en) 2007-08-17 2007-08-17 Method and system to increase the write cycle of solid state memory

Country Status (4)

Country Link
EP (1) EP1991988A4 (en)
CN (1) CN101427318A (en)
TW (1) TW200910377A (en)
WO (1) WO2008111912A1 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8990644B2 (en) 2011-12-22 2015-03-24 Micron Technology, Inc. Apparatus and methods of programming memory cells using adjustable charge state level(s)

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7190617B1 (en) * 1989-04-13 2007-03-13 Sandisk Corporation Flash EEprom system
US6026027A (en) * 1994-01-31 2000-02-15 Norand Corporation Flash memory system having memory cache
US20020048203A1 (en) * 2000-10-19 2002-04-25 Findling Patrick M. Extending total write cycles of non-volatile memory for rolling codes
US7480760B2 (en) * 2003-12-17 2009-01-20 Wegener Communications, Inc. Rotational use of memory to minimize write cycles

Also Published As

Publication number Publication date
TW200910377A (en) 2009-03-01
WO2008111912A1 (en) 2008-09-18
EP1991988A1 (en) 2008-11-19
EP1991988A4 (en) 2010-05-05

Similar Documents

Publication Publication Date Title
CN108958907B (en) Context-aware dynamic command scheduling for data storage systems
US9891838B2 (en) Method of operating a memory system having a meta data manager
US11334493B2 (en) Memory system and operating method thereof
TWI652577B (en) Data storage device and method for operating non-volatile memory
US9304900B2 (en) Data reading method, memory controller, and memory storage device
CN111158579B (en) Solid state disk and data access method thereof
US10528264B2 (en) Storage device and data processing system including the same
WO2016105780A1 (en) Method and apparatus for improving read performance of a solid state drive
US20190155545A1 (en) Device controller that schedules memory access to a host memory, and storage device including the same
KR102595233B1 (en) Data processing system and operating method thereof
US11295806B2 (en) Large file integrity techniques
US9037781B2 (en) Method for managing buffer memory, memory controllor, and memory storage device
US11720359B2 (en) Large data read techniques
KR20170076350A (en) Data storage device and operating method thereof
CN109426442A (en) Data storage device and its operating method
US9652172B2 (en) Data storage device performing merging process on groups of memory blocks and operation method thereof
CN101427318A (en) Method and system to increase the write cycle of solid state memory
JP2024503956A (en) System and method for defragmentation of memory devices
US9229798B2 (en) Error handling method, memory storage device and memory controlling circuit unit
KR102409405B1 (en) Method of operating memory controller and nonvolatile memory device including same
CN109918020A (en) Storage system and its operating method
CN112988068B (en) Memory control method, memory storage device and memory controller
US10635352B2 (en) Distributed flash interface module processing
US11086570B2 (en) Storage device, controller and method for operating controller
WO2024082136A1 (en) Memory system and operation thereof

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C02 Deemed withdrawal of patent application after publication (patent law 2001)
WD01 Invention patent application deemed withdrawn after publication

Open date: 20090506