CN101425502A - Fuse breakdown method adapted to semiconductor device - Google Patents
Fuse breakdown method adapted to semiconductor device Download PDFInfo
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- CN101425502A CN101425502A CN 200810176729 CN200810176729A CN101425502A CN 101425502 A CN101425502 A CN 101425502A CN 200810176729 CN200810176729 CN 200810176729 CN 200810176729 A CN200810176729 A CN 200810176729A CN 101425502 A CN101425502 A CN 101425502A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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Abstract
A plurality of pulses each having relatively low energy are consecutively applied to a subject fuse to cause breakdown, wherein the total energy of pulses is set in light of a prescribed breakdown threshold, which is calculated in advance. The subject fuse has a pair of terminals and an interconnection portion that is narrowly constricted in the middle so as to realize fuse breakdown with ease. A pulse generator generates pulses, which are repeatedly applied to the subject fuse by way of a transistor; then, it stops generating pulses upon detection of fuse breakdown. Side wall spacers are formed on side walls of fuses, which are processed in a tapered shape so as to reduce thermal stress applied to coating insulating films. In addition, pulse energy is appropriately determined so as to cause electro-migration in the subject fuse, which is thus increased in resistance without causing instantaneous meltdown or evaporation.
Description
The application is to be that March 30, application number in 2006 are that No.200610073319.2, denomination of invention are divided an application for " fuse breakdown method that is fit to semiconductor device " patent application the applying date.
Technical field
The present invention relates to a kind of fuse breakdown method, it adopts electric pulse to be applied to be incorporated in the fuse in the semiconductor device.
Background technology
Need to surpass the high relatively power that is applied to the operand power of circuit usually and cause the disconnection that is formed on the fuse on the Semiconductor substrate.For example, cause high electric current thereby MOSFET is in series connected to fuse, cause the fusing and the disconnection of fuse, wherein these MOSFET must have big grid width, and it is greater than being used for usually as the conventional grid width of the MOSFET of digital processing tens times to hundred times.Yet the MOSFET with big grid width has increased its overall size; And this is conflicting with the high integration of circuit.
Japanese Unexamined Patent Application discloses the circuit of having instructed for H10-189741 number the collector current that is formed on the parasitic bipolar transistor on the Semiconductor substrate by employing to fuse and having disconnected fuse.Japanese Unexamined Patent Application discloses to have instructed for S63-299139 number based on snowslide and disconnects and fusing and disconnect the circuit of fuse.Japanese Unexamined Patent Application discloses has instructed for S59-105354 number based on the latch-up phenomenon of parasitic thyristor (thyristor) and fuses and disconnect the circuit of fuse.
Japanese Unexamined Patent Application discloses has instructed for H11-203888 number by using laser beam fusing and disconnecting the circuit of fuse, and wherein because the departing from of laser beam incident position, fuse may not be disconnected fully, causes small electric current to flow through fuse.Therefore, after laser beam irradiation, check whether disconnection is complete; Then, electric pulse is applied to the fuse that does not disconnect fully once more, has therefore avoided disconnecting failure.
In order to produce the high power that the fuse that causes in the semiconductor device disconnects, need produce the high power (for example electron avalanche disconnection) that causes high electric current based on for example flyback of irrecoverable and destructive procedure (snapback) of the operation of the parasitic bipolar circuit of the operation of bipolar transistor, cmos circuit and MOS transistor with high current driving ability.Japanese Patent Application Publication 2002-158289, H06-37254 and H07-307389 instruction are used in the fusing and the disconnect method of the fuse in the semiconductor device.
In said method,, electric energy causes disconnection at once thereby being applied to each fuse; Yet, when each fuse disconnects, be difficult to stop at once applying electric energy.For this reason, need the long relatively time to apply electric energy to fuse.
For said method, disconnect is not to occur on the fuse with stationary mode always; Therefore, the mainstream technology that adopts the fuse breakdown method of the energy beam of laser beam for example to form recently to be used in the fuse in the stand-by circuit in the memory that is incorporated in DRAM for example to disconnect.This discloses among the H11-203888 in for example Japanese Unexamined Patent Application and instructs.
In the said method that fuse is disconnected by energy beam, need fuse be disconnected fully with the once irradiating of high electric energy.This allows, and fuse disconnects when fuse materials is melted, disperses and evaporates.Yet, produced another problem, promptly Rong Hua material is dispersed in the peripheral region of fuse and adheres again to other electronic components of semiconductor device.
Though fuse can be disconnected by high electric current or high energy beam, when high electric current or high energy beam are applied to fuse, all may destroy on the fuse that in semiconductor circuit, comprises and other elements.
In addition, the irrecoverable and destructive operation for for example flyback of the operation of the parasitic bipolar circuit of cmos circuit and MOS transistor is difficult to the electric energy that accurately control is applied to fuse.May apply the very high electric current that surpasses the scheduled current amount that causes that fuse disconnects.Therefore this cause high-energy scattering and make around the peripheral circuit of fuse can not work or destroyed.
Though fuse is by the very bundle disconnection of high energy, fuse materials is changed by physics, because they are by transient melting or evaporation; And be difficult to control this fulminant variation of fuse materials.In other words, disconnected by electric current and energy beam even work as fuse, fuse materials is owing to the caused rapid heating of energy that is applied on it is melted, evaporates and disperses.This causes conducting channel that is connected with fuse and the undesirable destruction that centers on the dielectric film of fuse.
When being melted when being attached to peripheral circuit around fuse, relate to the other problems of circuit, for example line short with dispersed fuse materials material.Particularly, the nurse tree adipose membrane of interlayer dielectric, passivating film and covering fuse may be easily destroyed and be disperseed; The crack may be formed in the semiconductor device easily; And semiconductor device may be melted easily be out of shape.This has reduced the manufacturing output of semiconductor device; Therefore, the reliability of semiconductor device reduces.
Therefore, may need to carry out extra manufacturing process, thereby wherein remove interlayer dielectric in advance for disconnection, the nurse tree adipose membrane of passivating film and covering fuse exposes fuse, forms these films once more in order to improve reliability with the covering fuse after disconnecting.
When thereby fuse is fused by low energy emission and disconnects when not causing physical damage, because the temperature fast that propagation and dispersion caused of heat energy raises and reduce, thermal stress accumulates in dielectric film, circuit and in the peripheral circuit of fuse.The reliability that this causes the variation of line resistance and influences circuit.
The electric energy that fuse is used the known transistor generation of easy control disconnects; Yet, need the large-size crystals pipe to produce high electric current; And this has increased total chip size and manufacturing cost.Relation between the disconnection of resistance, electric current and voltage and fuse can followingly obtain:
According to following formula (1), adopting fuse resistor Rfuse, transistorized driving force (is transistorized internal resistance, in other words, the transistorized conducting resistance Ron that has open channels) and driving voltage (or supply voltage) Vdd define the fuse electric current I fuse that realizes that fuse disconnects.
In above-mentioned formula (1), conducting resistance Ron depends on transistorized driving force, and wherein Ron reduces along with the increase of driving force.Thereby driving voltage Vdd increases fuse electric current I fuse.Yet driving voltage Vdd pre-determines in the stage in semiconductor circuit design, and the power consumption of LSI circuit trends towards increasing usually when driving voltage Vdd uprises; Therefore, be difficult to increase driving voltage Vdd in order to cause fuse to disconnect.
Because above-mentioned reason may need to reduce resistance R _ f use and Ron.Conducting resistance Ron pre-determined according to gate length Lg and grid width Wg in the transistor design stage.In order to reduce conducting resistance Ron, need reduce gate length Lg, gate length is by determined about the pre-defined rule of the design of LSI circuit and manufacturing, thus the minimum value of gate length Lg is a predetermined fixed.This makes needs to increase grid width Wg to reduce conducting resistance Ron.
Fuse resistor Rfuse is determined according to following formula (2) by the sheet resistance pf that depends on fuse materials and thickness and the fuse widths Wf that all determines in the design phase and fuse element length Lf.
Sheet resistance pf is based on the selection of electric conducting material in the LSI manufacturing process and thickness and determine.In order to allow fuse to disconnect easily, fuse widths Wf is made as the minimum value that predetermined design rule limited by the LSI design phase.This makes fuse resistor Rfuse to change according to fuse element length Lf, wherein along with the Lf Rfuse step-down that diminishes.
Above-mentioned relation is represented by following formula (3).
Ifuse＝A*F(1/Lf，Wg) ...(3)
Wherein " A " is the constant of determining in design and processes.
Usually, when fuse is used electric current that transistor produces and disconnects, width W g should tens times to hundred times ground greater than usually as the width of the MOS transistor of Digital Signal Processing.That is, fuse disconnects needs a large amount of large-sized transistors.This has increased the overall size of semiconductor chip and has therefore increased manufacturing cost.In addition, the stand-by circuit use large-size crystals pipe to highly integrated semiconductor memory chip may be unpractiaca.
Fuse element length Lf is limited by the turn-off characteristic of fuse and therefore can not so be reduced.Need fuse have predetermined resistance R ' fuse (that is, in practice, the resistance of the melt portions of fuse; R ' fuse is equal to or less than Rfuse substantially) because fuse is owing to gathering of the caused Joule heat of fuse electric current I fuse melted.The following expression of heat value J ' fuse:
J′fuse＝(Ifuse*R′fuse*T) ...(4)
Wherein on behalf of the moment and the fuse that electric current flows through fuse, T disconnect the time of being counted between the moment.
Therefore, when R ' fuse reduces, the corresponding increase of Ifuse; Yet, can reduce the total heat value J ' fuse that causes that fuse disconnects.Because this reciprocal relation, R ' fuse (or Rfuse) is limited and can not reduce arbitrarily.
Owing to be formed on the interference of the interlayer dielectric on the fuse, be difficult to make fuse to disconnect, because interlayer dielectric absorbs the energy of electronics or light beam.Therefore, interlayer insulating film, passivation layer and nurse tree adipose membrane are removed from the presumptive area of fuse and their peripheral region.Yet, this needs complicated technology, because semiconductor device is temporarily to take out and use the energy of electronics or light beam to relate to the test of the opening operation of the circuit operation of memory and fuse from making line, and returns then and make line and carry out composition and form the upper strata.This complexity owing to manufacturing process has increased manufacturing cost.In addition, because the retrofit of semiconductor circuit, fuse dimension is reduced by corresponding; And this makes and is difficult to carry out the accurate location of energy beam about fuse.This has increased regulates pinpoint time loss between them.
Relating to the retrofit of semiconductor element and the nearest technology of somewhat complex design rule allows energy beam that the irradiation of fuse is become very little.In addition, various development have been realized about the optimization of fuse dimension and shape, the optimization that is fit to the fuse resistor of transistor driving ability, therefore in the predetermined controlled range that realizes by transistor, suitably produce the class pulse current, and be used for adding thermo-fuse in the very short time cycle, fuse is disconnected.This can be avoided the generation of interlayer dielectric film, passivating film and nurse tree adipose membrane physical damage in fuse disconnection process.
Yet, when the dielectric film of suitable big figure is applied on the fuse, cause when the heat that produces in the fuse disconnection process is transmitted by it that owing to react (degassing reaction) by the hot caused degassing of dielectric film transmission, moisture gas can be emitted in interlayer dielectric; And this can reduce the reliability of LSI circuit.In addition, when the thermal contraction part occurred in this thick insulating film, interlayer dielectric may be out of shape a little, and in dielectric film crackle may take place.
Japanese Unexamined Patent Application discloses Fig. 1 of H07-307389 number and shows wherein fuse and the circuit that MOS transistor is connected and be arranged in parallel by contacting, and the current driving ability that wherein is used to produce the turn-off current of fuse calculates according to following formula.
I
D＝μC
ox(W/L)×(1/2)×(V
GS-V
T) ...(5)
In above-mentioned formula, I
DThe drain current of representative in the transistor zone of saturation; μ represents carrier mobility; C
OXRepresent transistorized grid capacity; W represents grid width; L represents gate length; V
GSRepresent gate source voltage; And V
TRepresent threshold voltage.
As known saturated drain current I
DThe time, can be according to the transistorized grid width of above-mentioned formula estimation causing fuse disconnection.
In order to produce the very high electric energy that causes that fuse disconnects, need increase transistorized size (being grid width) greatly, therefore this increase total chip size.When applying very high electric energy, fuse can be taken place thereby disconnect by transient melting and evaporation; Simultaneously, the fuse peripheral region can be affected.That is, be connected to the conducting channel of fuse and destroyed around the dielectric film of fuse.In addition, thus the material of fusing is disperseed to cause short circuit.Even when they are not destroyed, resistance may be owing to thermal stress changes, and this has reduced the reliability of semiconductor device.
When forming the trimming circuit comprise fuse and stand-by circuit in semiconductor integrated circuit, fine setting may or be carried out in the middle of the manufacturing of semiconductor integrated circuit afterwards, therefore realizes the characteristic of optimizing.
Adopt the above-mentioned relatively small number purpose fuse that circuit is selected that is used for, and adopt energy beam that it is carried out disconnection process.For fuse is disconnected fully by the irradiation of primary energy bundle, very high energy is applied to the fuse that exposes in advance.They are disconnected fully when fuse is melted, disperses owing to the very high energy of application and evaporates; Yet the material of fusing disperses in the peripheral region of fuse and can be adhered again to circuit.
Using the disconnect method of energy beam is unpractiaca for a large amount of fuses, because it need realize being radiated at the accurate location of the energy beam on the fuse for a long time.After encapsulation, can not write fuse to information.
Summary of the invention
The purpose of this invention is to provide a kind of method that in semiconductor device, adopts low current to disconnect fuse, wherein apply several times the low-power electric pulse to disconnect fuse to fuse.
In a first aspect of the present invention, a kind of fuse breakdown method is provided, wherein a plurality of pulses are applied to continuously via insulating barrier and are formed on target fuse on the Semiconductor substrate, thereby cause disconnection, and the gross energy that wherein is applied to the target fuse is set according to precalculated predetermined disconnection threshold value.The target fuse makes up by the interconnect portion of paired terminal and interconnected described terminal.Interconnect portion is retracted to narrow down has triangular shaped recess in the centre; It has at least one sweep; Perhaps it has for example spiral-shaped.
Because the energy of each pulse reduces, can reduce by causing that the temperature that electric energy caused that fuse disconnects increases; Therefore, can significantly reduce to be applied to the influence of fuse peripheral region and insulating barrier.This makes can be provided with a plurality of fuses, and they are vertically overlapped on Semiconductor substrate.Each fuse can have in the centre and shrinks the interconnect portion narrow down, makes its easy disconnection.When interconnect portion has at least one sweep or when spiral-shaped, can increase the effective length of fuse.
In a second aspect of the present invention, each all has low-energy relatively a plurality of pulses and is repeated to be applied to fuse, thereby may cause the hypothesis of transport phenomena and disconnect fuse based on repeating to apply thermal stress, therefore can reduce to be applied to fuse heat damage on every side.That is, though around being sent to by the caused heat of the electric energy that is applied to fuse, it can be with the fuse temperature proportional and with cube inversely proportional rapid minimizing of transfer rate.By the number of the pulse that is applied to fuse continuously suitably is set, the fuse temperature can reduce in the time in pulse spacing, therefore reduces to be sent to fuse heat on every side.
Compare with the conventional fuse breakdown method that individual pulse disconnected that fuse wherein is applied on it, the advantage of fuse breakdown method of the present invention is that (transmitted by heat that pulse caused and cause) thermal stress reduces; Therefore, can cause that fuse disconnects, and simultaneously its peripheral circuits for example dielectric film and circuit are not subjected to the influence of this thermal stress substantially.The reliability that this has reduced the variation of line resistance and has improved circuit.
In addition, can introduce and be used to survey the disconnection detection circuit whether fuse is disconnected by a plurality of pulses, therefore can prevent that too much pulse unnecessarily is applied on the fuse; And therefore can reduce the total processing time of relevant fuse interrupt routine.
In a third aspect of the present invention, form dielectric film to cover the sidewall spacers of fuse, thereby increase with the upper strata (i.e. the dielectric film that covers outward) that covers on it between distance, wherein be formed on outer around the fuse and cover dielectric film and be removed with the high heat propagation that prevents from when fuse disconnects, the to take place dielectric film that applies in other zones that are formed on beyond the fuse, so the degassing (degasification) in the dielectric film that has covered outside having suppressed; Therefore, can prevent that crackle from forming in the dielectric film that covers outside and prevent that the outer dielectric film that covers is out of shape undesirably.This has improved the reliability of semiconductor device in the manufacturing reliably.
As selection, form dielectric film with whole covering fuse; Then, in dielectric film, have on the fuse sidewall of the coverage rate that reduces and form sidewall spacers.Therefore the distance that this has increased between dielectric film and the covering upper strata (the promptly outer dielectric film that covers) has thereon reduced thermal stress.In addition, also form dielectric film has sidewall spacers with whole covering fuse; Then, on the sidewall of fuse, further form sidewall spacers with the coverage rate that reduces.This further increases dielectric film and the outer distance of covering between the dielectric film on it, therefore further reduces thermal stress.
As selection, form dielectric film with whole covering fuse and by Ar etching, O
2Etching or grind and carry out convergent and handle; Therefore can increase dielectric film and the outer distance of covering between the dielectric film on it, therefore reduce thermal stress.Can further form a dielectric film, cover described dielectric film with tapered portion; Therefore, can further increase the distance between dielectric film and the outer dielectric film that covers on it, therefore further reduce thermal stress.
The heat of the fuse that is caused by the electric energy that is applied on it can be sent to by the dielectric film that serves as the heat propagation medium around the fuse, and wherein the temperature of the temperature of the heat of being propagated and fuse is proportional and reduce rapidly inversely with the product of heat propagation volume (promptly be approximately distance cube) with specific heat.The dielectric film that covers outward is carried out quenching (quenching) heat treatment at about 400 ℃ predetermined temperature.Therefore, because the low relatively heat of fuse, the quality of the dielectric film that covers outward can not reduce; Therefore, the crackle and the degassing can not take place.Therefore, need the outer dielectric film that covers around the fuse that transmits high heat, to be removed in advance,, therefore reduce the heat that is sent to the outer dielectric film that covers perhaps away from fuse.
By the dielectric film that covers outward from fuse remove or by the dielectric film that covers outside making away from fuse, can guarantee to adopt surface of semiconductor integrated circuit smooth of the outer dielectric film that covers, thereby prove above-mentioned advantage.Particularly, being formed on outer on the fuse covers dielectric film and is carried out and eat-backs; Sidewall spacers is formed on the sidewall of the dielectric film that is applied; And use and to be difficult to the dielectric film that expanded or shrink by thermal stress; Therefore, can significantly reduce thermal stress.
In a fourth aspect of the present invention, energy is lower than and disconnects energy but be enough to cause that the pulse of solid phase shift is repeated to be applied to the fuse that is made of electric conducting material, so fuse resistor is owing to the thermal stress of gathering increases, but does not cause the instantaneous fusing or the evaporation of fuse.
Description of drawings
These and other purposes of more detailed description the present invention, aspect and embodiment with reference to the accompanying drawings, in the accompanying drawing:
Fig. 1 illustrates the figure that concerns between umber of pulse with different in width and the fuse disconnection rate;
Fig. 2 A is the figure that illustrates about the waveform that causes pulse voltage that fuse disconnects and electromotive force;
Fig. 2 B is the equivalent circuit diagram that comprises fuse and use transistorized open circuit;
Fig. 3 illustrates the figure that concerns between effective time that fuse disconnects and the fuse disconnection rate;
Fig. 4 is the flow chart that illustrates according to the fuse breakdown method of first embodiment of the invention;
Fig. 5 is the figure that concerns between the time that gathers that pulse current and fuse disconnection are shown;
Fig. 6 is the plane graph that the semiconductor device that comprises fuse and MOS transistor is shown;
Fig. 7 is the sectional view of being got along the line A8-A8 among Fig. 6;
Fig. 8 A is the sectional view that the first step of making semiconductor device is shown;
Fig. 8 B is the sectional view that second step of making semiconductor device is shown;
Fig. 8 C is the sectional view that the third step of making semiconductor device is shown;
Fig. 8 D is the sectional view that the 4th step of making semiconductor device is shown;
Fig. 8 E is the sectional view that the 5th step of making semiconductor device is shown;
Fig. 9 is the sectional view that the variation of semiconductor device shown in Figure 7 is shown;
Figure 10 is the sectional view that other variations of semiconductor device shown in Figure 7 are shown;
Figure 11 A is the plane graph that first example of fuse is shown;
Figure 11 B is the plane graph that second example of fuse is shown;
Figure 11 C is the plane graph that the 3rd example of fuse is shown;
Figure 11 D is the plane graph that the 4th example of fuse is shown;
Figure 11 E is the plane graph that the 5th example of fuse is shown;
Figure 11 F is the plane graph that the 6th example of fuse is shown;
Figure 11 G is the plane graph that the 7th example of fuse is shown;
Figure 12 A is the plane graph that the 8th example of fuse is shown;
Figure 12 B is the plane graph that the 9th example of fuse is shown;
Figure 12 C is the plane graph that the tenth example of fuse is shown;
Figure 12 D is the plane graph that the 11 example of fuse is shown;
Figure 12 E is the plane graph that the 12 example of fuse is shown;
Figure 13 A is the plane graph that the 13 example of fuse is shown;
Figure 13 B is the plane graph that the 14 example of fuse is shown;
Figure 13 C is the plane graph that the 15 example of fuse is shown;
Figure 14 illustrates the figure that concerns between pulse potential variation and the fuse potential variation;
Figure 15 is the figure that illustrates about disconnection rate and the experimental result that concerns between opening time;
Figure 16 A is the flow chart that illustrates according to the part of the fuse breakdown method of second embodiment of the invention;
Figure 16 B is the flow chart that another part of described fuse breakdown method is shown;
Figure 17 is the figure that concerns between the time that gathers that pulse current and fuse disconnection are shown;
Figure 18 is the circuit diagram that first example of fuse open circuit is shown;
Figure 19 is the circuit diagram that second example of fuse open circuit is shown;
Figure 20 is the circuit diagram that the 3rd example of fuse open circuit is shown;
Figure 21 is the circuit diagram that the 4th example of fuse open circuit is shown;
Figure 22 is the circuit diagram that the 5th example of fuse open circuit is shown;
Figure 23 is the circuit diagram that the 6th example of fuse open circuit is shown;
Figure 24 is the plane graph that diagram illustrates the component placement of the semiconductor device of realizing the CMOS integrated circuit;
Figure 25 A is the sectional view that the line A-A along Figure 24 is got, and the first step of making semiconductor device is shown;
Figure 25 B is the sectional view that second step of making semiconductor device is shown;
Figure 25 C is the sectional view that the third step of making semiconductor device is shown;
Figure 25 D is the sectional view that the 4th step of making semiconductor device is shown;
Figure 25 E is the sectional view that the 5th step of making semiconductor device is shown;
Figure 25 F is the sectional view that the 6th step of making semiconductor device is shown;
Figure 26 is the sectional view that the example of semiconductor device is shown;
Figure 27 is the sectional view that another example of semiconductor device is shown;
Figure 28 is the plane graph that diagram illustrates the arrangements of elements of the semiconductor device of realizing the CMOS integrated circuit;
Figure 29 A is the sectional view that the line A-A along Figure 28 is got;
Figure 29 B is the sectional view that the line A-A along Figure 28 is got;
Figure 30 is the sectional view that the line B-B along Figure 28 is got, and shows the basic structure that fuse links to each other with first dielectric film, sog film and second dielectric film and forms;
Figure 31 is the sectional view that the line B-B along Figure 28 is got, and shows first example of fuse-wires structure, and wherein sidewall spacers is formed on the sidewall of fuse;
Figure 32 is the sectional view that second example of fuse-wires structure is shown;
Figure 33 is the sectional view that the 3rd example of fuse-wires structure is shown;
Figure 34 is the sectional view that the 4th example of fuse-wires structure is shown;
Figure 35 is the sectional view that the 5th example of fuse-wires structure is shown;
Figure 36 is the sectional view that the 6th example of fuse-wires structure is shown, and wherein adopts a plurality of dielectric films to form a plurality of array of fuses;
Figure 37 is the circuit diagram that the fuse open circuit is shown;
Figure 38 is the plane graph that illustrates according to the semiconductor device of the fuse open circuit that comprises Figure 37 of fourth embodiment of the invention;
Figure 39 is the sectional view that the line C-C along Figure 38 is got;
Figure 40 is the circuit diagram that the memory circuit that adopts fuse is shown;
Figure 41 is the truth table that the operation of the selector in the memory circuit that is included in Figure 40 is shown;
Figure 42 illustrates the signal waveform that is used to explain the fuse opening operation; And
Figure 43 illustrates and is used to explain the signal waveform of determining fuse disconnection/non-off-state.
Embodiment
To the present invention be described by the mode that is described in greater detail with reference to the attached drawings example.
1, first embodiment
At first, will the basic principle that disconnect about fuse be described.The individual pulse that need have high energy causes that fuse disconnects.Particularly, thereby each all has low-energy relatively a plurality of pulses and reapplies to fuse and cause thermal stress, based on repeating to apply thermal stress or other factors may cause the hypothesis of transport phenomena and disconnect fuse.
Suppose to disconnect threshold value E
ThBe defined as the energy that representative enough causes each pulse that fuse disconnects.Require when a plurality of pulses are used to cause that fuse disconnects their gross energy E
TotalBe higher than and disconnect threshold value E
ThFor example, had 5 * 10 when fuse
7When the individual pulse of [J] energy takes place to disconnect, need apply each and all have 2.5 * 10
7Two pulses of [J] energy.In order to cause that with n pulse fuse disconnects (wherein n is not less than 2 integer), each pulse has 5 * 10
7/ n[J] energy.
Needn't all pulses all have same energy; Therefore, require gross energy to become and be higher than 5 * 10
7[J].For example, when fuse was disconnected by two pulse generations, first pulse had 2 * 10
7The energy of [J], and second pulse has 3 * 10
7The energy that [J] is above.
When n pulse produced the fuse disconnection, each pulse had same energy, and this energy is reduced to and disconnects threshold value E
Th1/n.Therefore, may be difficult to take place the dispersion phenomenon that causes owing to fuse failure; Therefore, can reduce dielectric film and the fuse influence of element on every side.
Needn't all n pulse all have to be made as and disconnect threshold value E
ThThe identical energy of 1/n; Therefore, each pulse only needs E
Th/ n or more.For example, when having, each pulse disconnects threshold value E
Th60% o'clock, two above pulse generation fuses disconnect.When each pulse has the threshold value of disconnection E
Th30%, four above pulse generation fuse disconnect.
The energy of a pulse is the product of voltage, electric current and pulse duration (or time span); Therefore, when fuse disconnects along with a plurality of pulse generations, and has the threshold value of disconnection E
ThIndividual pulse compare, the voltage or the electric current of each pulse reduce, perhaps pulse duration reduces.As selection, the curtage and the pulse duration of each pulse reduce.
Fig. 1 shows fuse disconnection rate and has relation between the umber of pulse of different time length (or pulse duration).Wherein, change the energy of each pulse by the pulse duration that changes each pulse.In order to eliminate the influence owing to the temperature that application the caused rising of pulse formerly, each pulse is applied to each fuse with predetermined time interval, and this time interval allows each fuse to be cooled off fully and changed from several seconds to tens seconds.
In Fig. 1, the pulse number that trunnion axis representative causing fuse disconnects, and the disconnection rate of the fuse of vertical axis representative disconnection.5000 fuses are as experiment, and each fuse has the double-layer structure that is made of polysilicon layer and metal silicide layer, wherein adopts identical voltage and current to produce to have different in width (i.e. 1200 ns, 860 ns, 600 ns, 480 ns and 250 ns) each pulse.
All fuses are disconnected by the individual pulse that 1200ns has ENERGY E (1200) by width.In 5000 fuses, each is disconnected 4050 fuses by the individual pulse that 860ns has ENERGY E (860) by width, wherein Sheng Xia 950 fuses each all disconnected by the pulse that two or three have energy (860).Since the manufacturing factor for example shape and size, the fuse sidewall of the polysilicon grain of fuse widths and thickness, formation fuse and metal silicide crystal grain shape and around the dispersion of the thickness of the dielectric film of fuse, the dispersion of turn-off characteristic takes place in experimental result.
According to the dispersion of fuse turn-off characteristic, suppose with high reproducibility and utilize the individual pulse of 1200ns and the fuse disconnection takes place.Therefore, ENERGY E (1200) basically with disconnect threshold value E
ThBe complementary.
Each individual pulse that is all had a 600ns of ENERGY E (600) of 15% fuse disconnects; And each is all disconnected about 70% fuse by two pulses of 600ns.This is because ENERGY E (600) is half of ENERGY E (1200); Therefore, two pulse energy sums become and equal to disconnect threshold value E
ThIn addition, each is all disconnected about 85% fuse by two pulses, and its energy sum equals to disconnect threshold value E
ThEach is all disconnected remaining 15% fuse by three pulses.This may be that the fluctuation of manufacturing factor causes.
Three pulse energy sums with 480ns of ENERGY E (480) surpass disconnection threshold value E
ThIn theory, each is all disconnected by three pulses to suppose most of fuses.In fact, the fuse of quite a lot of quantity can not be disconnected by three pulses; Need seven pulses cause 80% or above fuse disconnect; And each is disconnected all fuses fully by ten pulses.That is, the actual number that causes the pulse that fuse completely disconnects is greater than based on the disconnection threshold value E about ENERGY E (480)
ThThe predetermined pulse number of being foretold.Similar result takes place in the 250ns pulse for having ENERGY E (250).
To describe the actual pulse number in detail greater than the reason of estimating pulse number with reference to figure 2A and 2B.
Fig. 2 B shows the equivalent electric circuit that comprises fuse and open circuit.The driving voltage of 5V is applied to the first terminal of fuse Fu, and this first terminal is the n channel MOS transistor Tr that is connected in series to source ground.Voltage V1 is applied to the grid of this MOS transistor Tr.The electromotive force of V2 appears in the tie point between second terminal of the drain electrode of MOS transistor Tr and fuse Fu.When the pulse with voltage V1 was applied to the grid of MOS transistor Tr, this MOS transistor Tr was switched on, thereby allowed electric current to flow by fuse Fu.Energy in accumulating in fuse Fu surpasses disconnection threshold value E
ThThe time, fuse Fu is disconnected.
Shown in Fig. 2 A, voltage V1 has square waveform, and its level increases along with certain time constant, and keeps a period of time subsequently.(see voltage V1) when the pulse level increases, electric current begins to flow through fuse Fu; Therefore, electromotive force V2 reduces rapidly owing to the caused voltage drop of fuse Fu, and remains on predeterminated level then temporarily.When fuse Fu disconnected, electromotive force V2 dropped to ground potential rapidly.
When pulse duration is compared long enough with the rise time, can ignore by the caused influence of leader.Yet when pulse duration shortens when reaching 480ns or 250ns, becoming is difficult to ignore the influence that is caused by leader.For example, its level increases and reduces before pulse arrives constant level, and the electric current that then flows through fuse Fu reduced rapidly before arriving constant level.The number that this has increased the pulse that causes that fuse disconnects makes it greater than predetermined pulse number.
Each can be disconnected all fuses fully by the pulse of 15 to 20 250ns.This is indicating that ENERGY E (250) is basically from disconnecting threshold value E
Th1/15 to 1/20 change.That is, though the pulse of 250ns each with disconnect threshold value E
ThThe phase specific energy all lacks one, but can cause that fuse disconnects by the number that increases pulse reliably.
All level increases before arriving constant level of the pulse of each 480ns.This is indicating that pulse pulse duration and voltage for 480ns all reduce simultaneously.In other words, although pulse each all on voltage, reduce, can cause that fuse disconnects by the number that increases pulse reliably.
Carried out other experiments and realized the effective time that fuse disconnects to determine the electric current that flows through fuse by change, and will describe its result in detail with reference to figure 3, wherein the trunnion axis representative realizes the effective time that fuse disconnects, and be unit with millisecond [ms], and vertical axis is represented fuse disconnection rate [%].Realizing being defined by the product of pulse duration and pulse number effective time that fuse disconnects, is 70mA, 60mA, 50mA and the 40mA line that drawn about different electric currents wherein, and each all has identical pulse duration 1 * 10
-3Ms.
The line that draws about 70mA illustrates about 90% fuse, and each needs 1000ms to realize disconnecting.As for the pulse of the 1200ns that is produced by the 40mA electric current, it has been foretold and has realized that the pulse total number that fuse disconnects is " 834 ".In order to realize all fuses, may need being made as 10000ms effective time by the disconnection of 40mA electric current.Can realize by the pulse of 40000 250ns the effective time of 10000ms.
Then, will be with reference to the fuse breakdown method of Figure 4 and 5 and table 1 detailed description present embodiment.Carry out the method by changing pulse duration along with the time.
Fig. 4 shows flow chart, and the fuse breakdown method of present embodiment is shown.In step S1, be that 1mA or following and width are the initial resistance of 1ms or following pulse measurement target fuse to be disconnected by applying electric current.In step S2, this initial resistance and target resistance have been compared about the target fuse.When initial resistance was equal to or less than the twice of target resistance, flow process proceeded to step S3.When initial resistance during greater than the twice of target resistance, flow process proceeds to step 4, its output error order; Then, flow process proceeds to step S3.The reason whether the decision initial resistance is greater than or less than the twice of target resistance is that the output that causes for fear of primary fault reduces.Therefore, any multiple that can target setting resistance is to replace twice.
In step S3, variable m is set at " 1 ", and this variable m representative will be applied to the pulse number of target fuse continuously.In step S5, m pulse is applied to the target fuse continuously.
Table 1 shows pulse number with different in width and pulse and gathers relation between the time.
Table 1
| Pulse number | Pulse duration (msec) | Gather the time (msec) |
| 1 | 0.10 | 0.10 |
| 2 | 0.15 | 0.25 |
| 3 | 0.25 | 0.50 |
| 4 | 0.50 | 1.0 |
| 5 | 1.0 | 2.0 |
| 6 | 3.0 | 5.0 |
| 7 | 5.0 | 10 |
| 8 | 10 | 20 |
| 9 | 30 | 50 |
| 10 | 50 | 100 |
| 11 | 100 | 200 |
| 12 | 300 | 500 |
| 13 | 500 | 1000 |
| 14 | 1000 | 2000 |
In last table, be used for the pulse of big figure than long pulse width.Because m=1 in step S3, its width is that the pulse of 0.1ms is applied to the target fuse in step S5.In step S6, above-mentioned about the described condition of step S1 under the resistance of measurement target fuse.
In step S7, whether decision target fuse is exposed to the time of gathering of electric energy less than 2000ms.Can easily calculate the time of gathering according to variable m shown in the table 1 and the relation gathered between the time.When the time of gathering was equal to or greater than 2000ms, flow process reached step S10.When time of gathering during less than 2000ms, flow process proceeds to step S8, and in this step, whether the resistance of decision target fuse is equal to or greater than 1M Ω.When the resistance of target fuse is equal to or greater than 1M Ω, determine that the target fuse disconnects; Flow process proceeds to step S10 then.In step S10, therefore record finishes fuse breakdown method about the measurement result of target fuse resistor.
When the resistance of target fuse among the step S8 during less than 1M Ω, in other words, when definite target fuse did not disconnect, flow process proceeded to step S9, in this step, added " 1 " to variable m; Therefore flow process again proceeds to step S5.
As mentioned above, up to the time of gathering reach 2000ms or more than, or disconnect up to definite target fuse, pulse is applied to the target fuse continuously with measuring resistance.As shown in table 1, long pulse duration is used for the pulse of greater number.
Carried out above-mentioned fuse breakdown method about a plurality of fuses, and its result is shown in Figure 5.
Fig. 5 shows that the electric current that flows through fuse and fuse disconnect gathers relation between the time, and wherein the trunnion axis representative is the pulse current that unit is measured with the millisecond, and the vertical axis representative is the time of gathering that fuse that unit is measured disconnects with the millisecond.According to pulse voltage is that 2.1V, 2.3V, 2.5V, 2.7V, 3.0V and 3.5V classify all types of target fuse family.Occur in the fluctuation that pulse current in every group disperses to depend on the initial resistance of target fuse.
When pulse current is 45mA or when above, each fuse is disconnected by the individual pulse of 0.1ms.Along with pulse current diminishes, fuse disconnects, and to gather the time elongated.When pulse current became less than 42mA, the time of gathering that fuse disconnects was significantly elongated.For by using its width longly to gather the time, need increase the number of pulse greatly as what the pulse of constant guaranteed that fuse disconnects; And therefore this increase the processing time of realizing that fuse disconnects.For example, for the time of gathering of realizing 2000ms, need the processing time of 4000ms by the pulse of using the 0.25ms that exports with the 0.25ms time interval.
Though table 1 does not illustrate, along with pulse duration increases gradually, the processing time arrives 2003.5ms to realize the time of gathering of 2000ms.Along with the pulse number that is applied to each target fuse continuously becomes big, may reduce the processing time by increasing pulse duration.
Certainly, the pulse duration that is fit to present embodiment not needs be confined to shown in the table 1 those.For example, each A * 2 that are fit in m the pulse can be set
mPulse duration; Usually, this pulse duration may be calculated A * i
m(wherein A and i are optional integer constants).As selection, pulse duration may be calculated A * m
i
As selection, the time interval between the continuous impulse can be made as constant, and perhaps this time interval can be elongated and increase along with pulse duration.Yet, be increased to when being complementary when the time interval with pulse duration, becoming is difficult to reduce the processing time.Therefore, the time interval is made as certain period, between this section in each fuse recovery temperature after the PULSE HEATING formerly that is applied on it.
In step S8 shown in Figure 4, whether disconnect with reference to predetermined resistance decision target fuse, this predetermined resistance is made as 1M Ω, realizes that fuse disconnects other high resistances of determining yet it also can be made as.For example, this resistance can be made as hundreds of kilohm (k Ω) or any other high impedance, and this makes and can determine that fuse disconnects by reading circuit.When resistance is used for semiconductor device from tens ohm of trimming circuits that change to hundreds of ohm, for example, when changing from several kilohms to tens kilohms, fuse resistor can determine that fuse disconnects.Disconnect in case detect fuse, no longer apply pulse to the target fuse.This has prevented from unnecessarily to apply pulse to the target fuse reliably.Therefore, can reduce the time that fuse disconnects.
Then, description is comprised the semiconductor device of fuse and open circuit, wherein basic structure is identical with the equivalent electric circuit shown in Fig. 2 B, and wherein driving voltage is not necessarily limited to 5V.Conducting resistance and the driving voltage of the MOS transistor Tr that the electric current that flows through fuse Fu depends on the resistance of fuse Fu, be switched on.When fuse Fu is disconnected,, there is not drain current to flow through for the pulse voltage on the grid that is applied to MOS transistor Tr.
Fig. 2 B shows the simple series circuit of fuse Fu and MOS transistor Tr.The array of fuses that comprises many groups of above-mentioned series circuits with single semiconductor device can be provided.As selection, single open circuit can be used for a plurality of fuses, and the energy that wherein is applied to each pulse of single fuse reduces, but may cause disconnection simultaneously by applying a plurality of pulses on a plurality of fuses.
As selection, for single fuse is provided with a plurality of transistors so that high relatively turn-off current to be provided, wherein transistor can be constructed as CMOS transistor or bipolar transistor.Exclusive circuit can be used for generation and be applied to transistorized high grid voltage, therefore increases the pulse duration that flows through transistor turn-off current repeatedly.
Pulse generator can be used to produce the pulse of flowing through fuse synchronous with the clock signal of semiconductor integrated circuit.In addition, it is fractional frequency signal that frequency divider can be used for the frequency inverted of clock signal, thereby produces pulse synchronously with fractional frequency signal.In addition, delay circuit can be used for pulse from clock signal delay.
The conduction detection circuit can be used for determining whether each fuse disconnects fully.As selection, can improve show the feedback that each fuse fully disconnect of the feasible response of circuit from the conduction detection circuit, there is not pulse to be applied to each fuse.Can the employing program carry out this control.
Fig. 6 illustrates the plane graph that wherein fuse 1, MOS transistor 2 and p pit pull (tap) 3 are formed on the semiconductor device on the Semiconductor substrate.MOS transistor 2 comprises gate electrode 2G, source region 2S and drain region 2D.One end of fuse 1 is connected to power line 6 (being arranged in the upper strata) by contact hole CH1.The other end of fuse 1 interconnects by contact hole CH2, interconnection line 5 (being arranged in the upper strata) and a plurality of contact hole CH3 and drain region 2D.
Fig. 7 is the sectional view of being got along the line A8-A8 among Fig. 6.Insulating barrier 11 is formed on the surface of the Semiconductor substrate 10 that is made of p type silicon to divide a plurality of active areas.P trap 12 and n trap 13 are formed on the surface of Semiconductor substrate 10.P trap 12 comprises two active areas.N trap 13 is formed on below the insulating barrier 11.
P pit pull 3 is formed on the surface of an active area in the p trap 12; And in another active area, form said n channel MOS transistor 2 with source region 2S, drain region 2D and gate electrode 2G.Fuse 1 is formed on the insulating barrier 11.From the normal direction observation perpendicular to Semiconductor substrate 10, n trap 13 forms a fuse 1 and is included in wherein.Each gate electrode 2G and fuse 1 all have double-decker, comprise polysilicon layer and high melting point metal silicide layer.
The manufacture method of above-mentioned semiconductor device will be described to 8E with reference to figure 8A.
Shown in Fig. 8 A,, in the selected zone of the Semiconductor substrate 10 that constitutes by p type silicon, form the thick insulating barrier 11 of 500nm that constitutes by silica by LOCOS method or STI (shallow trench isolation, shallow trench isolation from) method.Carrying out ion injects to form p trap 12 and n trap 13.Remove the anti-oxidant mask that is used to form insulating barrier 11, thereby expose the surface of Semiconductor substrate 10 corresponding to active area.On surfaces of active regions, form silicon oxide layer 15 by thermal oxidation process.In addition, be formed on the silicon oxide layer 15 of the active area that is used for MOS transistor formation as gate insulation layer.
Replace silicon oxide layer 15, can adopt the double-decker that comprises silicon oxide layer and silicon nitride layer, comprise the double-decker of tantalum oxide layers and silicon oxide layer, perhaps wherein silicon nitride layer is inserted in two three-deckers between the silicon oxide layer.Wherein, silicon nitride layer can replace by oxidized silicon layer.The mode that forms silicon nitride layer is for adopting N
2Gas or NO
xThe silicon oxide layer that gas forms thermal oxidation is heat-treated and therefore it is carried out nitrogenize.As selection, can by adopt tetraethyl orthosilicate (tetra-ethyl-ortho-silicate, TEOS), oxygen (O
2), ozone (O
3) and the method for the excitation of plasma CVD of NOx or the chemical vapor deposition (CVD) by adopting ecr plasma form silicon nitride layer.In addition, only the surface of silicon nitride layer is carried out thermal oxidation to form three-decker in oxidizing atmosphere, and wherein silicon nitride layer is inserted between two silicon oxide layers.
Shown in Fig. 8 B, under following condition, by adopting silane (SiH
4) and nitrogen (N
2) method on the surface of Semiconductor substrate 10, form polysilicon layer 16.
Flow-rate ratio between silane and the nitrogen: 20:80
Gas flow: 200sccm
Pressure: 30Pa
Underlayer temperature: 600 ℃
By underlayer temperature being provided with to such an extent that be lower than above-mentioned value, can realize the deposit of amorphous silicon.As selection, heated substrate and therefore it is carried out polycrystallization and handle after the si deposition.Certainly, can directly adopt amorphous silicon layer.The thickness of polysilicon layer 16 suitably from 20nm to 1000nm, preferably changes from 80nm to 200nm.From for example 800 ℃ under the predetermined temperature of 900 ℃ of variations, phosphorus (P) material is diffused into polysilicon layer 16 equably to realize 1 * 10
20Cm
-3Impurity concentration.Before diffusion, preferably go up the natural oxidizing layer that forms by adopting buffering (buffered) hydrofluoric acid to remove polysilicon layer 16 surfaces.
By sputtering method or CVD method, on polysilicon layer 16, form the high melting point metal silicide layer 17 that constitutes by tungsten silicide (WSix), wherein its thickness preferably changes from 80nm to 200nm from 25nm to 500nm.Can replace WSix and adopt MoSix, TiSix and TaSix to form high melting point metal silicide layer 17.Replace high melting point metal layer 17, for example can form by the transition metal of refractory metal, for example Co, Cr, Hf, Ir, Nb, Pt, Zr and the Ni of for example Mo, Ti, Ta and W and comprise refractory metal and the metal level that alloy constituted of transition metal.
Under 1100 ℃, carry out ten seconds rapid thermal annealing (rapid thermal annealing, thus RTA) realize the low resistance of polysilicon layer 16 and high melting point metal silicide layer 17.The generation of interfacial separation between polysilicon layer 16 and the high melting point metal layer 17 has been avoided in this heat treatment reliably.Annealing time is from 1 second to 120 seconds, preferably from 5 seconds to 30 seconds.Annealing temperature is from 800 ℃ to 1150 ℃, the preferably variation from 900 ℃ to 1100 ℃.Replace RTA, can adopt electric furnace to heat-treat in the given time, this scheduled time is from 5 minutes to 90 minutes, preferably from 15 minutes to 30 minutes.
Shown in Fig. 8 C, polysilicon layer 16 and high melting point metal silicide layer 17 are carried out composition, therefore form gate electrode 2G and fuse 1, its each all have double-layer structure.Adopt etching gas to carry out etching by the ecr plasma etch device on bilayer, this etching gas is chlorine (Cl
2) and oxygen (O
2) mixture.
Shown in Fig. 8 D, phosphonium ion is injected into Semiconductor substrate 10 about the both sides as the gate electrode 2G of mask, therefore forms low concentration region 2Sa and 2Da corresponding to low concentration drain electrode (LDD) structure.The boron ion is injected into the surface of the active area of p trap 12, therefore forms p pit pull 3.It is that the low concentration region that injects into according to the LDD structure of p channel MOS transistor (not shown) with ion carries out simultaneously that the boron ion is injected into p pit pull 3.
Shown in Fig. 8 E, form the sidewall spacers 18 that constitutes by silica in gate electrode 2G both sides and fuse 1 both sides.On surface, carry out phosphonium ion and inject corresponding to the Semiconductor substrate of the mask both sides of gate electrode 2G and sidewall spacers 18 thereof, so the high concentration region of formation source and leakage.Therefore, can form source region 2S and drain region 2D corresponding to the LDD structure.
When the boron ion was injected into the high concentration source region of p channel MOS transistor into and drain region, the boron ion also was injected into p pit pull 3.After finishing the ion injection, activate annealing.
Then, carry out known step to form conductive plugs and line and the lead in interlayer insulating film, contact hole, the contact hole.Therefore, can obtain semiconductor device shown in Figure 7.
Can on the semiconductor device shown in Fig. 8 E, additionally carry out autoregistration and handle, on source region 2S, drain region 2D and p pit pull 3, to form metal silicide layer.In this situation, the high-melting-point silicide layer is exposed on gate electrode 2G and the fuse 1; Therefore, may not carry out silicification reaction thereon.Therefore, can improve manufacture method makes in the step of Fig. 8 B, do not form high melting point metal silicide layer 17, and in the step of Fig. 8 E, finish after the ion in source region and drain region injects, carry out autoregistration and handle on gate electrode 2G and fuse 1, to form high melting point metal silicide layer.
Be formed on the parasitic capacitance that n trap 13 below the fuse 1 reduces 10 of fuse 1 and Semiconductor substrate.
Fig. 9 shows the semiconductor device as the distortion of semiconductor device shown in Figure 7, and the fuse 1 that wherein is connected to MOS transistor 2 forms the surface of contact insulation layer 11.In semiconductor device shown in Figure 9, fuse 30 (corresponding to fuse 1) is formed on first interlayer insulating film 20.A terminal of fuse 30 is connected to the drain region 2D of MOS transistor 2 by being embedded in the conductive plugs of passing first interlayer insulating film 20 among the contact hole CH3.Second interlayer insulating film 22 covers fuse 30.
The another terminal that fuse is not connected with MOS transistor 2 is connected to power line 6 by being embedded in the conductive plugs of passing second interlayer insulating film 22 among the contact hole CH10.
Each that is formed on first interlayer insulating film, 20 lip-deep fuses and intermediary element 31 and 32 all has the double-decker that comprises polysilicon layer and high melting point metal silicide layer.Following description provides about forming the method for above-mentioned double-layer structure.
At first, form polysilicon layer according to the CVD method; For example the diffusion of impurities of phosphorus is in this polysilicon layer.On polysilicon layer, form high melting point metal silicide layer according to the CVD method.After double-deck formation is finished, carry out ten seconds rapid thermal annealings (RTA) at 850 ℃.Here, heat treatment is in that preferred predetermined temperature from 700 ℃ to 950 ℃ of variations carries out from 500 ℃ to 1000 ℃.Thereby the variation that impurity distributes in the source region and the drain region of MOS transistor 2 does not take place in the upper limit substantially that determine the temperature of heat-treating, and does not take place substantially because the variation of first interlayer insulating film, 20 surface configurations that reflux (reflow) causes.In addition, heat-treat the scheduled time, from 1 second to 120 seconds, preferred 5 seconds to 30 seconds.
Replace rapid thermal annealing (RTA), can adopt electric furnace to heat-treat in the scheduled time of preferred variation from 10 minutes to 30 minutes from 5 minutes to 90 minutes.After finishing heat treatment, high melting point metal silicide layer and polysilicon layer are carried out composition, therefore expose fuse 30 and intermediate conductive element 31 and 32.
Certainly, can form intermediate conductive element 31 and 32 by using the single polysilicon layer.In this situation, the resistor that adopts the single polysilicon layer to form can be arranged on first interlayer insulating film 20.
Above-mentioned fuse breakdown method can be used for the semiconductor device of Fig. 9, and wherein a plurality of pulses are applied to fuse to disconnect.Here, the low relatively influence that fusing caused by fuse 30 takes place in the zone around.This allows fuse 30 to be arranged near the MOS transistor 2.In other words, the active area of MOS transistor 2 can be set to overlap with fuse 30 on Semiconductor substrate 10 surfaces.This helps the minimizing of fuse and circuit size thereof.
Figure 10 is the sectional view that semiconductor device structure is shown, and wherein is similar to the described semiconductor device of Fig. 7, forms insulating barrier 11 and covers Semiconductor substrate 10 with part, wherein forms MOS transistor 2 in being insulated layer 11 active area that centers on.Thereby a plurality of fuses 40 form the surface of contact insulation layer 11 and form array of fuses.First interlayer insulating film 41 covers fuse 40 and MOS transistor 2.
A plurality of fuses 42 are formed on first interlayer insulating film 41 to form array of fuses and to be covered by second interlayer insulating film 43.A plurality of fuses 44 are formed on second interlayer insulating film 43 and by the 3rd interlayer insulating film 45 and cover.Lead 50 is formed on the 3rd interlayer insulating film 45 and protected seam 51 covers.
Figure 10 illustrates a plurality of fuses and is provided with to such an extent that be connected with a plurality of conductor layers, and wherein each fuse has the double-decker that comprises polysilicon layer and high-melting-point silicide layer or has the simple structure of single polysilicon layer.
Above-mentioned fuse breakdown method is applicable to the semiconductor device of Figure 10, thereby can reduce when each fuse disconnects the influence around the element of each fuse.Fuse below this allows and top fuse are vertically overlapped on the surface of Semiconductor substrate 10.
Figure 11 A shows the various examples of fuse to 11G, its each all have paired terminal and interconnect portion, each terminal all has square, each interconnect portion all has width W and length L.
Particularly, Figure 11 A shows first example of fuse, the wherein core of the interconnected terminal of interconnect portion.Figure 11 B shows second example of fuse, the wherein top of the interconnected terminal of interconnect portion.
Figure 11 C shows the 3rd example of fuse, the core of the interconnected terminal of interconnect portion wherein, a side of this interconnect portion in the centre by isosceles triangle depression compression straitly with right angle.Figure 11 D shows the 4th example of fuse, the top of the interconnected terminal of interconnect portion wherein, this interconnect portion in the centre by isosceles triangle depression compression straitly with right angle.
Figure 11 E shows the 5th example of fuse, the core of the interconnected terminal of interconnect portion wherein, the both sides of this interconnect portion all in the centre by isosceles triangle depression compression straitly with right angle.Figure 11 F shows the 6th example of fuse, the top of the interconnected terminal of interconnect portion wherein, the both sides of this interconnect portion all in the centre by isosceles triangle depression compression straitly with right angle.
Figure 11 G shows the 7th example of fuse, the interconnected terminal of interconnect portion top wherein, and the both sides of this interconnect portion are all straitly compressed by the triangular shaped recess with acute angle in the centre.Here, the triangular shaped recess that is respectively formed at the interconnect portion opposite side near and be formed parallel to each other.
The narrowed portion of interconnect portion makes each fuse be disconnected by relatively little energy easily.
Figure 12 A shows the other types of fuse to 12C, its each comprise paired terminal and interconnect portion, each terminal all has square, interconnect portion (having width W and length L) bends to the right angle in some part.
Particularly, Figure 12 A shows the 8th example of fuse, and wherein interconnect portion has two bending areas, thus the bottom of the top of an interconnected terminal and another terminal.Figure 12 B shows the 9th example of fuse, and wherein interconnect portion has four bending areas, thus the top of interconnected terminal.Figure 12 C shows the tenth example of fuse, and wherein interconnect portion has six bending areas, thus the bottom of the top of an interconnected terminal and another terminal.
Figure 12 D and 12E show the other types of fuse, its each comprise that all each is square paired terminal and the interconnect portion with length L.
Particularly, Figure 12 D shows the 11 example of fuse, wherein the top of the interconnected terminal of the interconnect portion that is bent upwards with 45 in the centre (having width W 1).Figure 12 E shows the 12 example of fuse, wherein in the centre with the core of the interconnected terminal of interconnect portion of rectangle part (have and be shorter than the length L 2 of length L) broadening greater than the width W 2 of width W.
Figure 13 A shows the 13 example of fuse, wherein has the top of the interconnected terminal of zigzag interconnect portion and the bottom of another terminal.Figure 13 B shows the 14 example of fuse, wherein has the core of the terminal of the interconnected setting adjacent one another are of spiral interconnect portion.Figure 13 C shows the 15 example of fuse, wherein has the top of the interconnected terminal positioned opposite to each other of sawtooth and spiral interconnect portion.
2. second embodiment
Be similar to first embodiment, second embodiment is had the principle of lower powered relatively a plurality of pulse disconnections based on each fuse by each and designs.
The gross energy E ' that is applied to the pulse of fuse must be equal to or greater than the least energy E that individual pulse enough causes disconnection; Therefore, E ' 〉=E.Suppose to have disconnection ENERGY E=5.0E-7[J] individual pulse cause that fuse disconnects.If two electric pulses cause fuse and disconnect, gross energy is that E ' (1+2) is equal to or higher than E; Therefore E ' (1+2) 〉=5.0E-7[J].
Evenly remove " 2 " producing two pulses if disconnect ENERGY E, each pulse have be equal to or higher than 2.5E-7[J] ENERGY E/2.That is, each pulse need disconnect half of energy.Needn't require the first pulse energy E ' (1) to equal the second pulse energy E ' (2); Be that in them one can be made as and is higher than another; Therefore, E 〉=E ' (1) 〉=E ' (2) or E 〉=E ' (2) 〉=E ' (1).Be expressed as E ' first pulse energy and the second pulse energy sum (1+2) and should be equal to or higher than E; Therefore E≤E ' (1+2).
When the disconnection energy even is removed " n " with n pulse of generation, each pulse has the energy that is equal to or higher than (5.0E-7)/n, therefore can reduce (by E ' (1), E ' (2) ... E ' (n) represents) energy of each pulse, promptly E ' (1), E ' (2) ... E ' (n)≤E; And gross energy E ' (1+2+...+n) is equal to or higher than E; Therefore, E ' (1+2+...+n) 〉=E.
Each pulse that energy reduces to the 1/n that disconnects ENERGY E is not high enough to cause the fusing and the dispersion of fuse materials; Therefore, can prevent from around fuse, to take place physical damage.This be because E ' (1+2+...+n) 〉=E, and the pulse E ' that is substantially equal to E/n that applies at last (n) can cause finally that fuse disconnects.
Therefore in above-mentioned, " n " needn't be made as integer and can be set to arbitrary value, if each fuse can by E ' (1+2+...+n) 〉=a plurality of pulses of E reliably disconnect.
For example, when each pulse has disconnection ENERGY E=5.0E-7[J] (wherein n=1.25) 80% the time, first pulse energy E ' (0)=4.0E-7[J] do not cause disconnection; Yet, first pulse energy and the second pulse energy sum be E ' (1+2)=8.0E-7[J], surpass to disconnect ENERGY E=5.0E-7[J]; Therefore, first and second pulses that are applied to continuously on it of each fuse disconnect fully.Similarly, when each pulse has disconnection ENERGY E=5.0E-7[J] (wherein n=3.333) 30% the time, the energy sum of three pulses be calculated as E ' (1+2+3)=4.5E-7[J], it enough causes disconnection; Yet, the energy sum of four pulses be calculated as E ' (1+2+3+4)=6.0E-7[J], thereby four pulses that each pulse is applied on it continuously disconnect fully.
In practice, a plurality of pulses of the theoretical number of determining may not can disconnect fuse fully under ideal conditions; Therefore, in distributing, may disperse about the pulse number that causes the fuse disconnection; Yet aforementioned calculation may be useful in determining to cause the pulse number that fuse disconnects.
Three kinds of methods (A), (B) are proposed and (C) come relation according to E=W*s=V*A*s that (wherein E represents energy; W represents electrical power; The V representative voltage; A represents electric current; And s represents the time) by the accumulation E ' (1), E ' (2) ... E ' (n) set up above-mentioned relation E ' (1+2+...+n) 〉=E, wherein method (A) is to reduce time span (or width) for each pulse, method (B) is to reduce electric current A or voltage V for each pulse, and method (C) is method (A) and combination (B).
And method (C) relates to the energy each pulse is set according to disconnecting, and wherein the time is removed " n ", and electric current (or voltage) removes " m " thus energy removes " n*m ", and therefore be reduced to 1/ (n*m).For convenience, under the hypothesis of n=n*m, carry out the description of back.
(A) time span (or time) remove " n " thus paired pulses is set up s 〉=s ' (1), s ' (2) ..., s ' (n) and s≤s ' (1)+s ' (2)+...+s ' relation (n).This expression for pulse E ' (1)=E*s ' (1)/s, E ' (2)=E*s ' (2)/s ..., E ' (n)=E*s ' (n)/s; Therefore E ' (1), E ' (2) ..., E ' (n)≤E, and E ' (1+2+...+n) 〉=E.
(B) electric current removes " n " thereby sets up A 〉=A ' (1) for pulse, A ' (2) ..., A ' (n) and A≤A ' (1)+A ' (2)+...+A ' relation (n).This expression for pulse E ' (1)=E*A ' (1)/A, E ' (2)=E*A ' (2)/A ..., E ' (n)=E*A ' (n)/A; Therefore E ' (1), E ' (2) ..., E ' (n)≤E, and E ' (1+2+...+n) 〉=E.Can cut apart voltage similarly because V=A*R (wherein R represents fuse resistor, and it is assumed to constant).
(C) method (C) is method (A) and combination (B).Promptly, time span and electric current (or voltage) are all evenly removed " n ", thereby set up above-mentioned s 〉=s ' (1) for pulse, s ' (2), ..., s ' (n) and s≤s ' (1)+s ' (2)+...+s ' relation and above-mentioned A 〉=A ' (1) (n), A ' (2), ..., A ' (n) and A≤A ' (1)+A ' (2)+...+A ' relation (n).This expression for pulse E ' (1)=E*s ' (1)/s*A ' (1)/A, E ' (2)=E*s ' (2)/s*A ' (2)/A ..., E ' (n)=E*s ' (n)/s*A ' (n)/A; Therefore, E ' (1), E ' (2) ..., E ' (n)≤E, and E ' (1+2+...+n) 〉=E.
(1) example A
Fig. 1 shows about fuse disconnection rate and the experimental result that causes the pulse number that fuse disconnects, and each fuse quilt is by disconnecting time span except that n the pulse that " n " realizes.Fig. 1 shows along with each burst length length shortens, and causes that the pulse number of disconnection increases; Yet can cause disconnection with each pulse that all has the predetermined number of the time span that reduces.That is, confirmed that each fuse is disconnected fully by a plurality of pulses that are applied on it.
By further analysis based on experimental result shown in Figure 1, know any kind fuse each all be made as the individual pulse institute that 1200ns has an ENERGY E (1200) and disconnect fully by time span.
Time span is that the individual pulse of 860ns applies ENERGY E (860)=E (1200) * 860/1200 to fuse, generally, and E (860)=0.717*E (1200).This show each two pulse sum that all have ENERGY E (860) can satisfy E ' (1+2) 〉=relation of E.In practice, each individual pulse with ENERGY E (860) of about 80% fuse disconnects.Fig. 1 shows in remaining 20% fuse, only 10% fuse each all disconnected by two pulses, and only 8% fuse each all disconnected by three pulses.
Owing to the fluctuation of making factor causes the generation of above-mentioned phenomenon, for example size and thickness, the shape and size of crystal grain, the sidewall shape in the etching of fuse change this manufacturing factor, chip position, the location, the date difference of handling batch, device fabrication difference etc. of wafer in batches on the thickness of the dielectric film of fuse and temperature, the wafer.This causes the dispersion of the manufacturing factor that relates to fuse of brokenness aspect.
Suppose that the least energy that causes disconnection under ideal conditions can be made as E (860); Yet,, cause that reliably disconnecting required least energy can be made as E (1200) because the fuse of brokenness aspect is made the fluctuation of factor.
Carried out experiment to determine to apply to fuse the timing of pulse, wherein each pulse is applied to each fuse with the predetermined time interval from several seconds to tens seconds, and this has guaranteed that each fuse cools down reliably after the PULSE HEATING that had before been applied.
If pulse was applied to each fuse continuously before its heat dissipates, in each fuse, gather heat owing to the pulse that applies continuously, thereby each fuse disconnects easily.For fear of such error result, carried out experiment and made the time interval between pulse (m-1) and the pulse m to be provided with arbitrarily, wherein 2≤m≤n.
According to the distribution of disconnection rate shown in Figure 1, know the fluctuation that in the line that draws about each pulse of relative short time length, to find fuse with realization ENERGY E (600).Fig. 1 shows in five lines that draw at Fig. 1, about having corresponding to half the line of pulse of ENERGY E (600) of each the burst length length with ENERGY E (1200), locate (seeing the trunnion axis of Fig. 1) in " 2 " and shown the highest percentage, promptly 70% or below.This expression above-mentioned relation E ' (1+2) 〉=E sets up.The number that seems the fuse that each two pulse that all had ENERGY E (600) disconnects becomes the highest.Suppose that if in size and manufacturing factor, do not fluctuate each can be had two pulses disconnections of ENERGY E (600) all fuses.
Line broadening on distributing that each all has the ENERGY E about pulse (480) of short period length does not wherein have fuse to keep not being disconnected.This has guaranteed to be applied to the number of the pulse on the fuse and reliably to disconnect all each fuses by increase.ENERGY E (480) is lower than ENERGY E (1200), differs the factor of 0.4 (=480/1200), and its inverse is 2.5.That is, based on applying of three pulses with ENERGY E (480), can set up above-mentioned E ' (1+2+...+n) 〉=relation of E; In other words, suppose that three pulses that each fuse is applied on it continuously disconnect fully.
Fig. 1 shows " 7 " that the peak value that distributes about the disconnection rate appears at trunnion axis and locates, and expression is applied to seven pulses of each fuse continuously.This number is that " 3 " are very different with the supposition number, because each pulse does not have square waveform completely owing to the delay in its forward position (leading edge), this delay may be to lead with inductance caused by the electricity in the internal circuit that is included in power circuit, test circuit, LSI device, the lead etc.
In Figure 14, curve C 1 representative causes the potential change of the pulse that fuse disconnects, and curve C 2 representatives are applied to the potential change of the fuse of the pulse disconnection on it.
Be forced to flow through fuse at place, the forward position of pulse electric current and cause that electromotive force reduces rapidly thereby curve C 2 shows; Then, electromotive force keeps constant for a moment; After this, when fuse disconnected, electromotive force dropped to 0[V suddenly]; After this, to remain on be zero to electromotive force substantially.
Owing to cause the forward position of the pulse deopiking that fuse disconnects, the pulse that its time length is made as 480ns or 250ns must keep constant to reduce electromotive force before a period of time at the disconnection electromotive force.Experimental result shown in Figure 1 is to arrive the aforesaid drawbacks that constant disconnects electromotive force according to the electric current that wherein flows through fuse to obtain.
Above-mentioned prophesy represents, based on E ' (1+2+...+n) 〉=relation of E, three pulses that each fuse can be had ENERGY E (480) disconnect fully.Yet the experimental result of Fig. 1 is very different with prediction, wherein about the line of E (480), locates to occur peak value in " 7 " of trunnion axis.
This may represent that each fuse is disconnected fully by a plurality of pulses of 1/7 that each all has ENERGY E (1200); In other words, seven pulses with energy (480) of each fuse disconnect fully.
Each pulse that time span is made as 250ns has ENERGY E (250), and itself and energy (1200) have relatively reduced the factor of 0.21=250/1200, and its inverse is 4.8.These five pulses representing that each fuse is had an ENERGY E (250) disconnect fully.Yet Fig. 1 shows " 15 " that the peak value that distributes about the line disconnection rate of E (250) appears at trunnion axis and locates.
Can suppose that each pulse with ENERGY E (250) can actually have 1/15 of ENERGY E (1200) based on experimental result shown in Figure 1.That is, each fuse is disconnected fully by a plurality of pulses of 1/15 that each has ENERGY E (1200); In other words, 15 pulses with ENERGY E (250) of each fuse disconnect fully.
(2) example B
The above results can show that wherein curtage is very effective for the fuse disconnection except that the method (C) of " n ".As mentioned above, reduced the pulse energy that is applied on the fuse by cutting apart total time length, and this pulse energy reduces by cutting apart curtage also.
Cause that reliably disconnecting required least energy is made as E (1200).This can show that each pulse with ENERGY E (480) can have 1/2.5 of the ENERGY E (1200) that will be applied to each fuse.The experimental result of Fig. 1 illustrates that each ENERGY E (480) is actual to have 1/7 of an ENERGY E (1200), because it is because the reduction of curtage and having been weakened; Therefore, each fuse is all had low-energy a plurality of pulse by each and disconnects fully.Similarly, calculate and have ENERGY E each pulse of (250) can have 1/4.8 of ENERGY E (1200); Yet, in practice, energy be each pulse of E (250) have ENERGY E (1200) 1/15 because its reduction owing to curtage weakens; Therefore, each pulse is all had very low-energy a plurality of pulses by each and disconnects fully.
And impulse waveform can be selected arbitrarily; Therefore, may use the alternately waveform of for example square waveform, sinusoidal waveform and two-phase or three-phase.
(3) example C
Figure 15 basic and Fig. 3 coupling illustrates for fuse disconnection rate that relates to the various current values that are applied to the pulse on the fuse and the relation between opening time, and wherein be the product of pulse duration and pulse number opening time.According to the line that electric current drew about 70mA, each is all disconnected about 90% fuse by single pulse; And each is all disconnected remaining 10% fuse by two pulses.Fig. 3 is clearly shown that all fuses disconnect fully, even diminish from 60mA to 50mA to 40mA along with electric current and be elongated opening time.Can be by reducing electric current (or voltage, because the relation of V=A*R, wherein fuse resistor R is a constant) and reduce the energy of each pulse; Therefore, the pulse number that is applied to continuously on each fuse can be set arbitrarily.
Based on experimental result shown in Figure 15,834 pulses cause that fuse disconnects completely, and each pulse has the pulse duration of 1200ns, according to the opening time of 1000ms and the turn-off current of 40mA.According to the longest opening time of 10000ms among Figure 15,40000 pulses cause that fuse disconnects completely, and each pulse has the pulse duration of 250ns.
The pulse number that allows fuse to disconnect is necessary for two or more and unrestricted; Yet Figure 15 can show that pulse number from " 1 " to " 40000 " changes.
According to above-mentioned relation about the pulse energy sum, need set up E ' (1), E ' (2) ..., E ' (n)≤relation of E; Yet, always do not need to set each E ' (1), E ' (2) ..., E ' (n) equals E/n substantially.In brief, above-mentioned experimental result illustrates each that do not need n pulse and all has identical energy.
Then, will be with reference to the fuse breakdown method of the flow chart description shown in figure 16A and the 16B according to present embodiment, wherein pulse is applied to target fuse predetermined opening time of T continuously, be T (1)=0.10ms, T (2)=0.15ms, T (3)=0.25ms, T (4)=0.50ms, T (5)=1.0ms, T (6)=3.0ms, T (7)=5.0ms, T (8)=10ms, T (9)=30ms, T (10)=50ms, T (11)=100ms, T (12)=300ms, T (13)=500ms, and T (14)=1000ms.
The fuse breakdown method of present embodiment is designed to change in a continuous manner pulse duration.That is the disconnection condition of target fuse, is set in step S21; They are identified and are stored in the memory in step S22; The initial resistance of measurement target fuse in step S23; Then, pulse is repeated to be applied to the target fuse and measures its resistance simultaneously up to disconnecting (seeing that step S24 is to S30).Shown in Figure 17 by the result that this fuse breakdown method produces.
Even when changing pulse duration in a continuous manner, confirm that from Figure 17 fuse is reliably disconnected by a plurality of pulses.For 45mA or above pulse current, each is all disconnected most of fuses by pulse in 0.1ms or following short time; Therefore, may not need to increase in a continuous manner pulse duration.On the contrary, for less pulse current, thereby wherein the said method that increases in a continuous manner of pulse duration can fully be worked and realized that fuse disconnects.
In brief, greater number " n " for editing pulse, the accumulative total opening time that the pulse that Figure 15 shows needs 40000 250ns realizes 10000ms, and by for example adopting the pulse of the 250ns that every 500ns cycle launches, this accumulative total can further be increased to 20000ms opening time.In other words, can reduce time interval between the pulse by increasing continuously pulse duration.When each time interval was made as 250ns, the cumulative time of adopting 16 pulses was 10000ms; And this shows and is calculated as 10000+ (0.250*16)=14000ms total time; Therefore, can save 6000ms altogether.
Above-mentioned in the pulse that is applied to the target fuse continuously, compare the method that increases next pulse duration with previous pulse duration and have following advantage:
As a rule, because the caused heat of pulse, fuse resistor tends to increase in time.Therefore, because the increase of fuse resistor is adopting constant voltage (for example Vdd=5.0V) to produce under the predetermined condition of pulse, the electrical power of each pulse is tended to reduce along with the increase of pulse number.
Constant current source may be favourable, owing to flow through the constant current of target fuse, the energy of each fuse can not reduce along with the increase of fuse resistor.Yet, thereby can by adopt increase according to fuse resistor increase continuously pulse duration guarantee each pulse constant energy method and cause that reliably fuse disconnects.
For example, pulse duration (each is represented by Tp) increases continuously and equably with the factor 2,2.5,4 and 5; So Tp=A * n (wherein A represents optional constant).The factor can freely be determined.For example, pulse duration increases continuously with exponential form; Therefore, Tp=A * n
x(wherein x represents optional constant for example 2 and 2.5).As selection, the numerical digit of pulse duration can increase continuously; So Tp=10
n, Tp=A
n, or Tp=n*A
n(wherein n represents optional integer).
In addition, the time interval Tint between the continuous impulse can be fixed as constant; Perhaps Tint=B (wherein B represents optional constant).In addition, time interval Tint can be made as and equal pulse width T p; Therefore, Tint=Tp.As selection, time interval Tint can change corresponding to above-mentioned pulse width T p.
Relation between pulse width T p and the time interval Tint can determine according to table 1, in conjunction with first embodiment in the above to its description.
Then, the fuse open circuit that adopts pulse will be described in detail.
Figure 18 illustrates first example of fuse open circuit; The grid that the cut-off signal that wherein has a pulse is applied to transistor 102 continuously disconnects up to fuse takes place, thus transistor 102 conductings, so that pulse is flow through fuse 101 by its drain electrode.Thereby the pulse Continuous Flow is crossed fuse 101 and is caused disconnection.
Adopt the pulse generator (not shown) to produce above-mentioned cut-off signal, this pulse generator produces the pulse with preset width that has predetermined time interval therebetween and also transmits them by for example AND circuit.
According to above-mentioned formula (1), fuse electric current I fuse depends on fuse resistor Rfuse, conducting resistance Ron and driving voltage Vdd.In addition, fuse electric current I fuse defines in above-mentioned formula (3), and it shows that the driving force along with transistor 102 uprises, and conducting resistance Ron reduces.That is, in order to increase fuse electric current I fuse, need to reduce conducting resistance Ron, yet this conducting resistance is predetermined and depend on grid size and grid width in the design phase of transistor 102.
Take place in case fuse disconnects, owing to the cut-off signal that is applied on it, it is mobile that transistor 102 can not make drain current pass through fuse 101.
The fuse open circuit of Figure 18 comprises single fuse 101; Yet, can provide a plurality of fuses to form array of fuses.In this situation, can single transistor be set for a plurality of fuses.As selection, can a plurality of transistors be set respectively for a plurality of fuses, thereby wherein their grid receives the selection of selecting signal to realize fuse.
Can introduce the pulse generator (not shown) is applied to fuse 101 with generation the pulse synchronous with clock signal of system.Here, can use frequency divider (frequency divider) to improve or reduce clock frequency.In addition, can additionally introduce delay circuit to regulate the synchronous of sequential.
In brief, can adopt the circuit of any kind, its each can both apply continuous impulse to fuse 101.In addition, can use and be used to survey about the disconnection detection circuit of the disconnection of fuse 101 and non-off-state or be used to survey the circuit of the sequence number of the pulse that applies at last that realizes that fuse 101 disconnects.Therefore, can improve the fuse open circuit and disconnect the output signal of detection circuit, thereby when detecting off-state, stop to apply pulse with feedback.This function can realize in the mode of programming.
Figure 19 shows second example of fuse open circuit, and it comprises AND circuit 103 and the transistor 102 that also has two input terminals except fuse 101.The lead-out terminal of AND circuit 103 is connected to the grid of transistor 102.
The fuse open circuit permission of Figure 19 clock signal in the ON cycle (perhaps high level cycle) of cut-off signal is applied to (comprising pulse) grid of transistor 102 continuously; Therefore, pulsion phase should be applied to fuse 101 to disconnect.
For example, can introduce the disconnection detection circuit of the disconnection that is used to survey fuse 101 and non-off-state or be used to survey the circuit of the sequence number of realizing the pulse that applies at last that disconnects.The output signal of foregoing circuit is fed as cut-off signal, and its level uprises up to fuse and disconnects, and disconnects the back step-down at fuse then.This allows pulse to be applied to fuse 101 continuously up to disconnection.
AND circuit 103 can by logical circuit or for example the logical circuit combination of inverter, NAND circuit, OR circuit and NOR circuit replace, be applied to the pulse of transistor 102 grids with improvement.In addition, can introduce the programmable circuit that produces various cut-off signals, therefore the fuse 101 to complex pattern applies pulse.
Figure 20 shows the 3rd example of fuse open circuit, it makes up to such an extent that be similar to the fuse open circuit of Figure 19, wherein the first input end of AND circuit 103 receives cut-off signal, and the drain current of transistor 102 is fed back second input terminal of AND circuit 103, and the output signal of AND circuit 103 is applied to the grid of transistor 102.Can introduce the pulse generator (not shown) and be used to produce pulse as the cut-off signal that is input to AND circuit 103.
In above-mentioned, the electromotive force at the tie point place between the drain electrode of fuse 101 and transistor 102 uprises, and disconnects up to fuse 101.In such high level period, be included in the interior pulse of cut-off signal is applied to transistor 102 continuously by AND circuit 103 grid; Therefore, corresponding pulse is applied to fuse 101 repeatedly from the drain electrode of transistor 102.When fuse 101 disconnects, the electromotive force step-down at the tie point place between fuse 101 and transistor 102 drain electrodes.Such low potential is fed back to second input terminal of AND circuit 103.This makes the output signal of AND circuit 103 and cut-off signal step-down irrespectively; Therefore, the grid of transistor 102 is forced to be made as low.
The fuse open circuit of Figure 20 has advantage, because do not need to be used to survey the disconnection of fuse 101 and the disconnection detection circuit of non-off-state.That is, the fuse open circuit can simplified structure; Therefore, can reduce total chip size.In addition, transistor 102 does not need to carry out complex operations, and wherein it is only in the non-off-state conducting of fuse 101, and need be in the off-state conducting of fuse 101.This has eliminated the unnecessary power consumption that the MOSFET with big gate regions as transistor 102 is charged.
The fuse open circuit of Figure 20 designs to such an extent that make uprise second input terminal that directly feeds back to AND circuit 103 with the electromotive force of step-down in non-disconnection and off-state.Can additionally introduce the stabilizing circuit that is used for stabilizing potential or be used to survey the electromotive force detection circuit of electromotive force, be fed back to AND circuit 103 by its electromotive force.In addition, can be ELECTROMOTIVE FORCE FEEDBACK AND LOAD FEED to the pulse generator that is used to produce the pulse that forms cut-off signal; Therefore, cut-off signal for example stops according to low potential.
In above-mentioned, AND circuit 103 can by logical circuit or for example the combination of the logical circuit of reverser, NAND circuit, OR circuit and NOR circuit replace, thereby improve the pulse be applied to transistor gate.In addition, can introduce the programmable circuit that produces all kinds cut-off signal, therefore apply pulse to the fuse 101 that is in complex pattern.
Figure 21 shows the 4th example of fuse open circuit, and the AND circuit 103 that wherein has three input terminals is used for the grid of transistor 102.
Be similar to above-mentioned fuse open circuit, the electromotive force between the drain electrode of fuse 101 and transistor 102 remains height, disconnects up to fuse 101.At such high potential in the cycle, AND circuit 103 is based on cut-off signal and clock signal and provide pulse to the grid of transistor 102; Therefore, corresponding pulse is repeated to be applied to fuse 101 from the drain electrode of transistor 102; Therefore, fuse 101 finally disconnects.
When fuse 101 disconnects, electromotive force step-down and be fed back to an input terminal of AND circuit 103, thus the output signal and the cut-off signal of AND circuit 103 that is provided to the grid of transistor 102 irrespectively is retained as low.
In above-mentioned, AND circuit 103 can by logical circuit or for example the combination of the logical circuit of reverser, NAND circuit, OR circuit and NOR circuit replace, thereby improve the pulse be applied to transistor gate.In addition, can introduce the programmable circuit that produces all kinds cut-off signal, therefore apply pulse to the fuse 101 that is in complex pattern.
Pulse needn't be applied to fuse 101 synchronously with clock signal, and this clock signal can be replaced by the clock signal of system.Can introduce frequency divider to improve or to reduce clock frequency; Perhaps can introduce and adjust the synchronous delay circuit of sequential.Corresponding to non-disconnection and off-state and the electromotive force that uprises with step-down not necessarily directly feeds back to AND circuit 103.That is, can introduce and be used for stablely, be fed back to AND circuit 103 by its electromotive force, so stablize its operation corresponding to disconnecting and the stabilizing circuit of the electromotive force of non-off-state or be used to survey the electromotive force detection circuit of this electromotive force.As selection, electromotive force can be fed back to the pulse generator that is used to produce the pulse that forms cut-off signal, so this cut-off signal stops in the off-state.
Figure 22 shows the 5th example of fuse open circuit, and wherein fuse 101 is disconnected by a plurality of pulses, and it has the memory function that permission is read about the information of the disconnection of fuse 101.Compare with the fuse open circuit of Figure 21, the fuse open circuit of Figure 22 also comprise be used for input information read output signal, clock signal and appear at fuse 101 and the drain electrode of transistor 102 between the AND circuit 132 of electromotive force.
Before fuse 101 disconnected, fuse 101 had been applied in driving voltage Vdd, thereby high potential is applied to AND circuit 132.When the information read output signal with high level is applied on the AND circuit 132, the information signal of the high level that 132 outputs of AND circuit and the clock signal of high level are synchronous.
When fuse 101 disconnected, low potential was applied to AND circuit 132, and this is the information signal of output low level successively, even when information read output signal and clock signal all uprise.
Because the fuse open circuit of Figure 22 allows to be output about the disconnection information of fuse 101, AND circuit 103 does not need to comprise the feedback about off-state.Certainly, can improve the fuse open circuit of Figure 22 to comprise feedback about off-state.
Figure 23 shows the 6th example of fuse open circuit, wherein adopt " m " individual fuse circuit (fuse circuit 111,112 and 113 that for example comprises fuse Fuse-1, Fuse-2 and fuse Fuse-m and transistor Tr-1, Tr-2 and Tr-m) to make up array of fuses, this array of fuses is arranged in rectangular and suitably selects by fuse selection circuit 114; And information reading circuit 115 is read the disconnection information about each fuse circuit of selecting from m fuse circuit.Here, array of fuses comprise by Fuse-1, Fuse-2 ... and m fuse representing of Fuse-m.This allow n pulse be applied to simultaneously each fuse Fuse-1, Fuse-2 ..., Fuse-m.If m≤n can reduce the load of power circuit, disconnect required little electric energy because cause fuse; Therefore, can make circuit design easy.The custom circuit that independently is applied to fuse with pulse is wherein compared, and the total time that applies pulse to fuse can reduce to 1/m.
When m=n/5, the total amount of electric energy can reduce to 1/5 of the required electric energy of ball bearing made using, because m fuse disconnected by pulse simultaneously.Therefore, can reduce the load of power-supply system, and a plurality of fuses are disconnected simultaneously; Therefore, compare with custom circuit, the total time loss can reduce to 1/m.
Then, the manufacture method of the semiconductor device that comprises fuse and interlock circuit thereof will be described with reference to Figure 24 and Figure 25 A-25E.
Figure 24 is the plane graph that the CMOS integrated circuit that comprises fuse and interlock circuit thereof is shown.This CMOS integrated circuit includes gate electrode G, fuse F, contact hole and the lead of source region, MOSFET, and all are formed on the semiconductor substrate surface.
Figure 25 A is the sectional view that the line A-A along Figure 24 is got to 25E, wherein carries out the structure of six steps with the CMOS integrated circuit that produces Figure 24 successively.
Shown in Figure 25 A, carry out the LOCOS method on the surface of Semiconductor substrate, to form field oxide film and gate oxide film, each all has predetermined thickness, and wherein form the p trap and link to each other with the MOSFET district, and the n trap that links to each other with fuse of formation.
For example, form the thick mask (not shown) of the 15nm be made of SiN to cover the whole surface of Semiconductor substrate, this Semiconductor substrate is covered by the thick thermal oxide film of 50nm in advance.This mask is removed from selection area but still is retained in and is used for the active area that MOSFET forms.This mask prevents that oxidation film is formed on the surface of Semiconductor substrate.Carry out high-temperature thermal oxidation and come the oxidation selection area, mask is removed from this zone, thereby forms thick " thick " field oxide film of 500nm.When after field oxide film forms, removing this mask, do not have oxidation film to be formed in the active area that mask covered that is constituted by SiN basically, but thin-oxide film can be retained in the active area.
Then, use the hydrofluoric acid of dilution to remove thin-oxide film from the active area that is used for MOSFET formation; Then, heat-treat once more to form " approaching " gate oxide film.
As for gate oxide film, for example can adopt the double-decker of the single layer structure that uses silicon oxide film, the silicon oxide film that uses predetermined material and silicon nitride film or the double-decker of use tantalum-oxide film and silicon oxide film with high-k.Can adopt three-decker, wherein silicon nitride film is inserted between the two-layer silicon oxide film, and wherein silicon nitride film can be replaced by silicon oxynitride (silicon oxide nitride) film.
Can be by in nitrogen or comprise that carrying out hot nitrogenize in the mist of nitrogen of NOx on preformed oxidation film forms silicon nitride film.Be inserted in the situation of the three-decker between the two-layer silicon oxide film at silicon nitride film, comprise NOx, tetraethyl orthosilicate (TEOS), oxygen (O by plasma exciatiaon CVD method or by adopting the CVD method of electron cyclotron resonace (ECR) plasma, adopting
2) or ozone (O
3) mist form silicon nitride film (or silicon oxynitride film).
Then, in the oxygen atmosphere, the nitride film that forms by hot nitrogenize and CVD method is carried out thermal oxidation, therefore produce silicon nitride film wherein and be inserted in three-decker between the two-layer oxidation film.And, can select to form the material and the thickness of gate insulating film arbitrarily with high-k.
Shown in Figure 25 A, form the trap of the conductivity type opposite that need be pre-formed conduction type and Semiconductor substrate about fuse F; For example, the n trap is formed in the p N-type semiconductor N substrate.Because the formation of n trap, even when the heating of fuse F to be disconnected causes destruction to Semiconductor substrate, can prevent that also the leakage current of not expecting is mobile in Semiconductor substrate.In addition, fuse F and field oxide film can be used as the electric capacity dielectric film, and it forms very little electric capacity with Semiconductor substrate successively.Because the formation of n trap, the electric charge of the Semiconductor substrate under the fuse F that can avoid not expecting moves.On the contrary, the p trap is effectively worked for n N-type semiconductor N substrate.
Figure 25 A shows the formation of n channel mosfet in active area.In order to simplify, Figure 25 A does not illustrate the formation of p channel mosfet.Certainly, the manufacture method of present embodiment can easily be applied to the formation of p channel mosfet or the formation of other types complementary MOS FET (or cmos circuit).
N channel mosfet and p channel mosfet all can be included in the structure of cmos circuit, and wherein before field oxide film formed, the trap with two kinds of conduction types was pre-formed on Semiconductor substrate.In the situation of p type silicon substrate, for example, for the formation of p channel mosfet and form the n trap.
The gate electrode of n channel mosfet and p channel mosfet can form by identical technology before polysilicon-metal silicide etching.In order to form the MOSFET of two kinds of conduction types respectively,, need to use dissimilar ionic impurities for the LDD formation that relates to low concentration region with for the ion injection that relates to as the high concentration region formation of source electrode and drain electrode.
For the threshold voltage of realizing expecting, can in the step shown in Figure 25 A, define active area and introduce the impurity of predetermined concentration to channel region afterwards.As selection, can introduce suitable impurity to fate corresponding to the gate electrode of the gate electrode of n channel mosfet or p channel mosfet, therefore change the work function (work function) of gate electrode.Ion injects the introducing that is generally used for realizing above-mentioned impurity.
Shown in Figure 25 B, after first polysilicon layer forms, can introduce suitable impurity to the fate (corresponding to the gate electrode of n channel mosfet or the gate electrode of p channel mosfet).
In above-mentioned, field oxide film is formed on the silicon substrate by the LOCOS method, and this method can be changed into the STI that other partition methods for example form about active area (shallow trench isolation, shallow trench isolation from) method.In this situation, field oxide film can form by the film formed the whole bag of tricks that insulate of being suitable for beyond the thermal oxidation process.
Semiconductor substrate needn't be limited to silicon substrate; Therefore, it can comprise that the IV-IV compound of SiGe and GaAs forms by employing.Active element needn't be limited to MOSFET; Therefore, can adopt the active element of HEMT type for example, ambipolar and SIT type.
Figure 25 B shows polycrystalline silicon deposition process, and wherein polysilicon layer is deposited on the whole surface of Semiconductor substrate by the CVD method.Polysilicon layer adopts SiH
4(20%) and N
2(80%) mist forms under the temperature of the pressure of 200sccm flow velocity, 30Pa and 600 ℃.When the temperature of Semiconductor substrate considerably reduces to said temperature when following, the amorphous silicon growth replaces polysilicon.Yet by the heating Semiconductor substrate, recrystallized amorphous silicon also changes polysilicon into.Therefore, can optionally adopt amorphous silicon or polysilicon.
The thickness of polysilicon layer preferably changes from 80nm to 200nm from 20nm to 1000nm.
Then, carrying out impurity diffusion technology from 800 ℃ of predetermined diffusion temperatures to 900 ℃ of variations, thereby with about 1020cm
-3Predetermined impurity concentration on polysilicon layer, spread phosphorus equably.Impurity diffusion technology may unexpectedly form high concentration and mix the phosphorus oxidation silicon fiml, and it adopts the hydrofluoric acid of buffering to remove, and therefore realizes the cleaning on polysilicon layer surface.
Then, deposit high melting point metal silicide layer, metal level or metal alloy layer on polysilicon layer.
In the depositing technics of refractory metal silicide, for example, the refractory metal silicide of selection such as tungsten silicide (WSix) and by sputter or the deposit of CVD method, thus polysilicon layer and relevant portion (for example dielectric film) thereof covered in the mode of conformal (conformal).
Adopt the WSix target to carry out sputter, its component can be determined arbitrarily.According to the character of silicide, " x " is set in the scope of 1.5≤x≤3.5, preferably in the scope of 2.0≤x≤3.0.For example,, adopt the DC magnetron sputtering apparatus under predetermined deposition conditions, promptly carry out sputter under the power of the Ar air-flow of 3mTorr pressure, 30sccm, 200 ℃ underlayer temperature and 1150W in the situation of WSi2.7 (being x=2.7).The thickness of deposit preferably changes from 80nm to 200nm from 25nm to 500nm.
Adopt tungsten hexafluoride (WF
6) and silane (SiH
4Thereby) mist carry out the CVD method and realize WSi according to following chemical equation
2Deposit.
WF
6+2SiH
4→WSi
2+6HF+H
2
Adopt MoSix, TiSix and TaSix to form high melting point metal silicide layer.Here, the metal silicide that adopts component to determine arbitrarily forms sputtering target.By using refractory metal for example Mo, Ti, Ta and W and by using transition metal for example Co, Cr, Hf, Ir, Nb, Pt, Zr and Ni, metal that refractory metal silicide can be scheduled or predetermined metal alloy replace.
Thereby above-mentioned layer can be carried out heat treatment to be caused and the reaction of polysilicon layer, therefore forms metal silicide by silicification technics.
After the deposit of high melting point metal silicide layer is finished, before the formation of interlayer dielectric, heat-treat, therefore reduce fuse and the resistance that comprises the multicrystalline silicon compounds gate electrode of refractory metal silicide.Above-mentioned heat treatment prevent metal silicide and polysilicon layer since the follow-up heat treatment that is applied to metal silicide for example because the quenching heat treatment of after interlayer dielectric forms, carrying out and unexpectedly separated from one another.
Can under preferred predetermined temperature, adopt diffusion furnace or realize heat treatment by rapid thermal annealing (RTA) from 900 ℃ to 1000 ℃ of variations from 800 ℃ to 1150 ℃.For diffusion furnace, heat-treating in the preferred predetermined period of time that changed from 15 minutes to 30 minutes from 5 minutes to 90 minutes.For RTA, heat-treating in the preferred predetermined period of time that changed from 5 seconds to 30 seconds from 1 second to 120 seconds.In the present embodiment, RTA carried out 10 seconds at 1100 ℃.
And heat treatment is carried out after the gate electrode composition or with the formation of side separator simultaneously.
After heat treatment is finished, can form anti-reflective film, its processing for fine gate electrode and fuse may need.Certainly, not necessarily need anti-reflective film and therefore not shown in the drawings.
Particularly, TiN or TiOxN (wherein the ratio x that sets for oxygen element preferably changes from 10atm% to 15atm% from 5atm% to 30atm%) are carried out deposit, thereby form the anti-reflective film that thickness preferably changes from 10nm to 100nm from 30nm to 60nm.That is (be Ar, N at sputter gas, by using the DC magnetron sputtering apparatus
2And O
2Mist) in use the reactive sputtering of Ti target.Anti-reflective film reduces the light reflection on gate electrode and the lip-deep suicide element of fuse.Can carry out photoetching.Anti-reflective film can carry out before above-mentioned heat treatment; Therefore, anti-reflective film is removed after the finishing dealing with of meticulous gate electrode and fuse, and then, heat-treats.
Shown in Figure 25 C, a part of dielectric film that still keeps composition not is as mask, thereby carries out composition on first and second polysilicon layers and metal (or metal silication construction element), therefore forms gate electrode.
In above-mentioned, photoresist is applied on the surface of high melting point metal silicide layer; Afterwards, this photoresist is carried out selects exposure to be removed then, therefore stays the predetermined photoresist pattern of covering corresponding to the presumptive area of the gate electrode G of MOSFET and fuse (and lead M, not shown).This photoresist pattern is used as etching mask, thereby carries out the policide etching by using under ecr plasma etching machines (the Sumitomo Metal Industry Co. by the Japan makes) condition below.
Etching gas: Ci+O
2Gas
Gas flow: 25sccm, and 11sccm
Pressure: about 2mTorr
RF power: 40W
RF frequency: 13.56MHz
Microwave power: 1400W
Microwave frequency: 2.45GHz
Electrode temperature: 15 ℃ to 20 ℃
As a result, high melting point metal silicide layer and the polysilicon layer of being covered by the photoresist pattern is not carried out the selection etching, thereby the gate electrode G of MOSFET, fuse F and lead M are formed simultaneously.
After policide and polysilicon etching, the photoresist pattern is removed from high melting point metal silicide layer.Shown in Figure 25 C, metal silicide layer is formed on the polysilicon layer in the presumptive area of covering grid electrode G, fuse F and lead M, therefore realizes providing the ad hoc structure of policide layer and policide electrode.
Then, shown in Figure 25 D, the gate electrode G of MOSFET that still keeps not carrying out above-mentioned composition is as mask, thereby forms the diffusion layer with LDD structure in active area.
In active area, the gate electrode G with policide layer injects the structure with self-aligned manner formation LDD as mask thereby pass through n type ion.Figure 25 D illustrates the LDD structure of n channel mosfet; Certainly, about the p channel mosfet, this LDD structure can form similarly.This allows by using the resist mask that n type ion and p type ion are injected into zones of different independently in photoetching.
Should not carry out p type ion to the zone that relates to different elements and lead beyond the active area that forms the p channel mosfet injects.This is because n type ion (for example phosphorus) formerly mixes and advances the gate electrode G of MOSFET and the policide layer of fuse F, so their sheet resistance may change owing to the injection of p type ion (for example boron).
Figure 25 D does not specifically illustrate and does not use mask to carry out the injection of n type ion in the front side of wafer; Therefore, n type ion is injected on the fuse F.Thereby this resistance that may reduce fuse F disconnects fuse F easily.Adopt the resist pattern to carry out p type ion and inject,, thereby do not inject p type ion to other zones wherein by the opening of photoetching formation corresponding to the active area that is used for the formation of p channel MOS transistor.
As mentioned above, by using resist pattern to adopt the mode that limits to carry out the injection of p type ion as mask.Therefore, carry out p type ion for the LDD structure of p channel mosfet and inject, its mode is offset by the p type ion that the n type ion that formerly is injected on it newly is injected on it.
Then, shown in Figure 25 E, for the diffusion layer of source region and drain region formation high concentration, thereby its mode is finished the formation of LDD structure for forming sidewall spacers with self-aligned manner, then, according to the above-mentioned technology shown in Figure 25 D MOSFET is carried out composition and ion injection.
By using the CVD method and the reactive ion etching (RIE) that realize the dielectric film deposit to form this sidewall spacers.When eat-backing on the CVD execution level of realizing the LDD structure when forming sidewall spacers, thereby the surface of realizing the polysilicon layer of resistance may be cut away a little and caused resistance variations.
Above-mentioned defective can solve by the material and the thickness of suitable selection anti-reflective film, thereby so anti-reflective film can be as bearing the etched protective film with done with high accuracy expectation resistance.Anti-reflective film as diaphragm can be removed after selecting to be etched in sidewall spacers formation.Anti-reflective film is not necessarily removed because its thickness is compared extremely thin with silicide layer thickness.Even partly keeping, anti-reflective film is not removed, also no problem basically in manufacturing process.
In the situation of cmos circuit structure, carry out p type ion and inject to be formed for the high concentration diffusion layer in source region and drain region, wherein need to prevent that by the resist composition p type ion is injected into other zones.This is because high concentration ion injects the sheet resistance that can influence silicide layer greatly.
Can before or after injecting, the ion that is used to form the high concentration diffusion layer that is used as source region and drain region shown in Figure 25 E introduce the silicide process that adopts metal silicide.In this situation, can not change the policide film shown in Figure 25 D basically and form technology and introduce improved silicide process.In addition, can on the policide film, form silicide film with the thickness that reduces; And can realize the normal silicide process that polysilicon forms simply.
When improved silicide process is used for the policide film shown in Figure 25 D and forms technology, the reaction film that is made of predetermined material is formed on diffusion layer or the policide film, and this predetermined material for example depends on the TiSix and the CoSix of the predetermined metal (for example Ti, Co, Ni and TiCo alloy) that is used in the improved silicide process.Here, because from being pre-formed the very little supply of silicide layer below, reaction film may not can be fully grown or may be reduced greatly by thickness.Therefore, the policide film that is used for fuse may cause the little variation of sheet resistance, and does not therefore change the turn-off characteristic of the fuse that is applied with pulse substantially.
The advantage of this silicide process is because the sheet resistance that reduces of diffusion layer, and MOS transistor can improve its driving force, therefore produces and is applied to the high energy pulse of fuse, and do not change transistorized size.
Form technology when only realizing that polysilicon forms (not having silicide to form) when normal silicide process is applied to the policide film shown in Figure 25 D, by silicide material for example the reaction film that constitutes of TiSix and CoSix be formed on diffusion layer and the policide film.This has set up silicide film wherein and has been deposited on policide structure on the polysilicon film, and the metal that wherein is formed on the polysilicon film can absorb Si to induce reaction from it, therefore forms silicide film.Therefore, and compared by the formed silicide film of normal process shown in Figure 25 B, little variation may take place in the thickness of silicide film and sheet resistance.
By before reaction, regulating thickness and conditioned reaction temperature, can regulate the sheet resistance of the silicide film that is used for fuse.The variation of sheet resistance can be by regulating transistorized driving force and by absorbing corresponding to fuse resistor regulating impulse energy.
Figure 25 F shows the formation of interlayer dielectric, contact hole, W bolt and plain conductor.
After the technology that relates to sidewall spacers and diffusion layer formation shown in Figure 25 E, carry out the known manufacturing process that relates to the CMOS integrated circuit, thereby then form interlayer dielectric, contact hole, W bolt (realizing) and metal wire by embedding contact hole; At last, form passivating film is formed on semiconductor device surface with protection circuit.
Particularly, successively deposit for example the predetermined material of phosphosilicate glass (PSG) and boron phosphosilicate glass (BPSG) therefore form the interlayer dielectric that thickness changes from 0.6 μ m to 0.8 μ m to cover MOS transistor and fuse.Then, carry out photoetching and dry etching to form contact hole in precalculated position corresponding to the diffusion layer of gate electrode, fuse and the policide line (not shown) of source region and drain region, MOS transistor.
Form the adhesion layer that constitutes by TiN or TiON/Ti by sputter or CVD method to cover the inside of contact hole and interlayer dielectric.Particularly, form adhesion layer, its mode is for forming the thickness Ti film that (preferred 20nm) changes from 5nm to 50nm, and the deposition thickness TiN film that (preferred 100nm) changes from 50nm to 200nm on the Ti film then.The TiN film can be replaced (the value x of oxygen element preferably changes) by the TiOxN film here from 10atm% to 15atm% from 5atm% to 30atm%.
The deposit of Ti film realizes by carrying out sputter under the condition below.
Underlayer temperature: 150 ℃
Ar flow: 30sccm
Pressure: 3mTorr
Sputtering power: 1150W
In the deposit of Ti film, preferably adopt collimated sputtering or long slow sputter (long-slow sputtering), therefore can have enough Ti films of big thickness in the formation of fine contact hole bottom.The CVD method can be used to form has the desirable Ti film that applies the factor.
Adhesion layer needn't be made of above-mentioned material.That is, it can be made of the combination of the metal nitride of high melting point metal alloy, metal silicide, metal silicide and for example TiN of for example TiW and the combination (for example boride) of refractory metal and its nitride.
After the formation of adhesion layer is finished, can under nitrogen atmosphere, carry out the high speed heat treatment (for example rapid thermal annealing (RTA)) of the scheduled time from 10 seconds to 60 second, to improve the thermal endurance and the obstructing capacity of adhesion layer in target substrate temperature from 500 ℃ to 800 ℃ of variations.
Then, form the conductive layer that constitutes by the W bolt to cover the interior section of contact hole and adhesion layer by the CVD method.The thickness of determining conductive layer makes each contact hole be filled with electric conducting material.That is, the thickness of conductive layer be made as the contact hole diameter that is filled with electric conducting material half or more than.For example, when the diameter of contact hole was about 0.50 μ m, the thickness of conductive layer was made as 1.2 times to 2.0 times greater than radius, and therefore changes from 300nm to 500nm; Therefore preferably, it is made as 1.4 times to 1.6 times greater than radius and change from 350nm to 400nm.Because the thickness of conductive layer is less, eat-back (with the device that is used for it) can bear less load.
For example select electric conducting material the predetermined material of WF6 from having high evaporation pressure compound.For example, can realize the tungsten deposit by the CVD method under the condition below.
Underlayer temperature: 450 ℃
Gas flow: WF
6/ H
2/ Ar, and its component is 40/400/2250sccm
Pressure: 10kPa
Electric conducting material is carried out anisotropy eat-back, thereby electric conducting material only is retained in the contact hole.Particularly, be that reactive ion etching (RIE) realizes that anisotropy eat-backs by dry etching, thereby adhesion layer expose from conductive layer under the condition below.
Gas flow: SF
6/ Ar, its component is 30-140/40-140sccm (preferred 110/90sccm)
High frequency power: 450W
Pressure: 32Pa
The light F that launches by monitoring
+The density of (its wavelength is 704nm), in other words, by surveying the light F of the big emission of difference change
+Intensity increase and survey finishing of tungsten etch.Can carry out above-mentioned etching and be removed from interlayer dielectric, so this interlayer dielectric is exposed up to adhesion layer.
After this, form wiring layer to cover adhesion layer and contact hole and W bolt by sputter, CVD method or plating.In addition, the heating wiring layer is handled with reflux as required (reflow) under vacuum condition.
Below under the condition to by Al-Si or comprise Al-S and wiring layer that the Al alloy of Cu constitutes carries out sputter, with the predetermined thickness of realizing that (preferred 500nm) changes from 100nm to 1000nm.
Underlayer temperature: 200 ℃
Ar flow: 33sccm
Pressure: 2mTorr
Sputtering power: 9000W
After the formation of wiring layer is finished,, Semiconductor substrate carries out reflow treatment under the predetermined temperature from 400 ℃ to 550 ℃ of variations thereby remaining under the vacuum condition and be heated.Wiring layer can replace Al or Al alloy formation by Cu or Cu alloy (for example Cu-Cr, Cu-Zr and Cu-Pd), and wherein sputtering target becomes Cu or Cu alloy.Before the wiring layer that is made of Cu etc. forms, form conduction and build layer with direct covering adhesion layer and contact hole and W bolt (after this being called contact bolt); Then, for example forming wiring layer on the layer of conduction base.
Build layer and can intercept constituent element (for example Al) diffusion of wiring layer, so improve the anti-leakage characteristics in connecting.Build layer and can be used as adhesion layer, this adhesion layer is used for forming by the wiring layer of CVD method; Therefore, can further improve reliability.
Be similar to adhesion layer, building layer can form by adopting sputter consecutive deposition Ti layer and TiN layer (or TiON layer).Building layer needn't be made of above-mentioned material; Therefore, can use for example combination and the refractory metal of for example tantalum and tantalum nitride and the combination of nitride (or boride) of the metal nitride of refractory metal, metal silicide, metal silicide and for example TiN of TiW.
After the formation of building layer is finished, in order to improve thermal endurance and the barrier properties of building layer, can be under nitrogen atmosphere from carrying out 10 seconds to 60 seconds rapid thermal treatment (for example RTA) under 500 ℃ to 800 ℃ the predetermined temperature.And, can irrespectively on wiring layer, form conductive cap layer with the formation of building layer.This cap rock can form by the Ti layer of consecutive deposition 7nm thickness and the TiN layer of 40nm thickness.
This cap rock has various functions, and for example, it prevents the light reflection in photoetching, and it prevents the oxidation of wiring layer, and it prevents the diffusion of wiring layer constituent element (for example Al).
Wiring layer is carried out composition by photoetching and dry etching, is connected to contact bolt and contact terminal (not shown) then.Build layer and cap rock and be carried out composition, therefore form wiring pattern with wiring layer.
Replace ground, carry out inlaying process on fuse, to form through hole bolt and lead; Perhaps carry out the dual damascene method to form them simultaneously.Processing and fuse characteristics about contact and lead are irrelevant.
After this, be used as the passivating film of surface protection film to cover above-mentioned all layers by the formation of CVD method.Particularly, from 50nm to 200nm, change NSG film or the SiO of preferred 100nm by consecutive deposition thickness
2Film and thickness change the SiN film of preferred 1000nm or SiON film and form thickness changes preferred 1.1 μ m to 1.4 μ m from 0.8 μ m passivation layer from 600nm to 1200nm.Then, pressure welding point is carried out Hall technology, this pressure welding point is corresponding to the splicing ear that is used for connecting with external devices, and by photoetching be dry-etched in that delineation limits the line that chip is cut apart on the passivating film.Like this, can finish manufacturing simulation MOS integrated circuit.
As mentioned above, present embodiment provides the semiconductor device with policide structure, and the metal silicide that wherein has predetermined thickness is deposited on the polysilicon layer, and the thickness and the material of the gate electrode of this policide structure and MOS transistor are complementary.
Figure 26 shows each fuse that adopts second polysilicon layer or the second policide layer to form, and this second policide layer has the double-decker that is made of second polysilicon layer and second metal silicide layer.In this situation, Figure 25 A is partly improved to the manufacture method shown in the 25F, thereby changes heat treatment temperature and impurity injection a little about the formation and the composition of interlayer dielectric.
That is, deposit second refractory metal silicide film then, was heat-treated before the formation of second interlayer dielectric, wherein must the limit temperature scope with the resistance and the fuse resistor of the polycide gate electrode that reduces to adopt refractory metal silicide.
Can be in that preferred predetermined temperature from 700 ℃ to 950 ℃ of variations adopts diffusion furnace or heat-treats by RTA from 500 ℃ to 1000 ℃, when adopting diffusion furnace, heat-treating in the preferred predetermined period of time that changed from 10 minutes to 30 minutes from 5 minutes to 90 minutes.As selection, carrying out RTA in the preferred predetermined period of time that changed from 5 seconds to 30 seconds from 1 second to 120 seconds.In being described below, RTA carried out under 850 ℃ 10 seconds.
Because having carried out impurity injects to be formed for the LDD structure of MOS transistor, because high-temperature heat treatment or long heat treatment may change in impurities concentration distribution.This causes can not obtaining for MOS transistor the shortcoming of desired characteristic.The above-mentioned BPSG that is used for first interlayer dielectric can easily flow at low temperatures; And this may be owing to heat treatment causes the surface configuration distortion of not expecting.Therefore, the heat treatment of carrying out after the deposit of second refractory metal silicide film is finished need be for the close attention of temperature and time.
For above-mentioned reasons, preferably adopt RTA, because RTA finishes heat treatment at short notice and realizes accurate management about Temperature Distribution.Certainly, can omit the increase of heat treatment with the sheet resistance of the second policide layer avoiding not expecting.In addition, can omit the impurity that is used for LDD structure and source region and drain region formation injects.In this situation, inject owing to lack impurity, the sheet resistance of policide can increase a little.This may need some adjustment about transistor driving ability, pulse energy and fuse resistor, wherein fuse each can normally disconnect.
As shown in figure 26, form first fuse by using the first policide film, this first policide film is that the formation with the gate electrode of MOS transistor forms simultaneously; Then, second polysilicon layer or the second policide film that is formed on first interlayer dielectric by use forms second fuse.
May between first policide film (or first polysilicon film) and the second policide film (or second polysilicon film), form electric capacity.When only adopting polysilicon to form second fuse, may in one deck, form resistor.And, can adopt n the polysilicon layer that comprises resistance and electric capacity to form fuse, this n polysilicon layer is that each all adopts the known manufacturing process of the various devices of a plurality of polysilicon layers to form by being used for for example simulating LSI device and DRAM etc.In addition, may set up the policide structure, wherein on n polysilicon layer, form silicide layer.
In the structure of Figure 26, second fuse is directly connected to following polysilicon layer by the contact bolt that the drain electrode near MOS transistor forms.This is not restriction; Therefore, second fuse can tie the drain electrode of receiving MOS transistor by top through hole.Here, mosaic technology is used to form second fuse; And carry out dual-damascene technics and go up through hole bolt and lead to form simultaneously.Certain first and second fuses can directly link together, and perhaps its predetermined terminal can link together simply.When first and second fuse design when having different turn-off characteristic, they can be used as memory, wherein can write binary bit information.
Figure 27 shows sandwich construction, wherein adopts a plurality of polysilicon layers or a plurality of policide layer to form fuse.Technology by the above-mentioned fuse that relates in second polysilicon layer shown in Figure 26 or the second policide layer forms has realized the vertical formation of array of fuses by using multilayer, and wherein a plurality of fuses are horizontal.Here, carry out above-mentioned STI (shallow trench isolation from), wherein form transistor by above-mentioned silicide process to realize element separation.
Particularly, employing is made first array of fuses with the gate electrode identical materials by identical silicide process.Similarly, second array of fuses and the 3rd array of fuses each all form and be arranged on first array of fuses successively and vertically by above-mentioned technology shown in Figure 26.Certainly, can form the array of fuses of the predetermined number of freely determining.
3. the 3rd embodiment
The 3rd embodiment is designed to avoid apply pulse to disconnect the physical damage of their caused heat to interlayer dielectric to fuse, and reduce to be applied to the thermal stress of interlayer dielectric (the promptly outer dielectric film that covers), therefore may be suppressed at the degassing in the outer dielectric film that covers, and may prevent that the crack is formed in the dielectric film that applies, and prevent that the outer dielectric film that covers is deformed.
Before describing the 3rd embodiment in detail, will compare with the operating principle of second embodiment, its operating principle is simply described.
Second embodiment relates to three kinds of methods (A), (B) and (C), and wherein the 3rd embodiment comprises following additional explanation:
For method (B), we can say that disconnecting energy is cut apart to produce each and all have very little energy pulses, can not disconnect by its fuse in finite time length.This can represent the lower limit of electric current A, is represented by Amin; Therefore, A ' (1), A ' (2) ..., A ' is (n)〉Amin, and A ' (1)+A ' (2)+...+A ' is (n)〉n*Amin.This also represents E ' (1)=E*A ' (1)/A〉E*Amin/A, E ' (2)=E*A ' (2)/A〉E*Amin/A ..., and E ' (n)=E*A ' (n)/A E*Amin/A.
Electric current removes in the method (C) of m therein, needs divided electric current to be higher than lower limit Amin.
In addition, the 3rd embodiment also relates to following method (D):
(D) helping to reduce pulse duration, electric current and voltage method (A) and (B) or in the combination situations of method (C), needn't use n and m evenly to cut apart the disconnection energy, but can cut apart in a continuous manner, wherein the time interval between the pulse can be determined arbitrarily.
And the fuse breakdown method that is applied to the 3rd embodiment is identical with the fuse breakdown method that is applied to second embodiment shown in Figure 16 A and the 16B; Therefore, do not provide the description of repetition.In addition, the 3rd embodiment also relates to table 1, and table 1 is being described in conjunction with first embodiment before; Therefore, do not provide the description of repetition.
With reference to the Figure 17 that describes in conjunction with second embodiment before,, may all in the 2000ms accumulated time, be disconnected by not all fuse by the electric current of the voltage of 2.1V and 35mA along with fuse changes opening time in a continuous manner.This is illustrated in and uses the fuse opening operation of pulse to finish in finite time under the predetermined condition.
Therefore, need to introduce above-mentioned lower current limit Amin, it can estimate to be made as about 30mA reliably by the electrical testing that carries out on the fuse that is made of polysilicon, and wherein resistor and lead also are made of polysilicon.
The 3rd embodiment also relates to the fuse open circuit shown in Figure 18 and 22, has before described this circuit in conjunction with second embodiment; Therefore, do not provide the description of repetition.
Then, with the manufacture method of describing in detail according to the 3rd embodiment.
Figure 28 is the plane graph that the CMOS integrated circuit is shown, and it includes gate electrode G, fuse F, contact hole and the lead of source region, MOS transistor.
The manufacture method of the 3rd embodiment is substantially similar to the manufacture method to second embodiment of 25D in conjunction with Figure 25 A; Therefore, do not provide the description of repetition.Certainly, Figure 25 A is the sectional view of being got along the line A-A among the Figure 28 among the 3rd embodiment to 25D.
For the diagram of Figure 25 B, the 3rd embodiment is different with second embodiment, thereby passes through to use the DC magnetron sputtering apparatus to realize the deposit of high melting point metal silicide layer under the condition below.
Sputtering target: the component factor x for WSix is made as 2.7
Pressure: 8mTorr
Ar flow: 30sccm
Underlayer temperature: 150 ℃
Power: 2000W
Can carry out chemico-mechanical polishing (CMP) as required to realize the leveling on interlayer dielectric surface.In this situation, the turn-off characteristic that is formed on the fuse on the plane surface of interlayer dielectric does not change, and the variation of turn-off characteristic may take place owing to irregular.In addition, above-mentioned leveling is being favourable aspect the retrofit of contact hole, fuse and lead.Particularly, the resist that can adopt thickness to reduce is realized retrofit; Can increase the exposure content; And can reduce to relate to etched dispersion.
The bpsg film that preferably carries out CMP has enough big thickness and is exposed to the surface to prevent down psg film.In addition, may prevent to be formed on policide in the kick of LOCOS oxidation film owing to CMP is exposed to the surface; Therefore, may avoid short circuit between upper conductor layer and the fuse; And can eliminate the parasitic capacitance that the little thickness owing to related film causes.In addition, the difference that may prevent to be used for after psg film thickness is owing to difference between the polishing factor of PSG among the CMP and bpsg film and CMP to eliminate between the etching factor of the chemically cleaning PSG of polishing fluid and BPSG reduces.
Require CMP not expose bpsg film, even be zero substantially when the thickness of interlayer dielectric becomes to the surface.For example, for the psg film of 100nm thickness and the bpsg film of 900nm thickness, the polishing thickness of being realized by CMP is made as 400nm.Here, the minimum thickness of bpsg film depends on the difference in height between the giving prominence to of trap and LOCOS oxidation film, wherein preferably changes from 100nm to 200nm.
Be similar to second embodiment, form adhesion layer by consecutive deposition Ti film and TiN film.In the 3rd embodiment, the Ti film forms by sputter under the condition below.
Sputtering target: Ti
Underlayer temperature: 150 ℃
Ar flow: 15sccm
Pressure: 4mTorr
Sputtering power: 1150W
Formation for adhesion layer, can use other materials, such as, for example for example combination of Ta/TaNx and nitride (or nitrogen oxide or boride) of the combination of the metal nitride (or nitrogen oxide) of the metal silicide of the high melting point metal alloy of TiW, for example TiSix, metal silicide and for example TiNx and refractory metal.
Can be by carrying out the deposit that sputter realizes TiNx film or TiOxNy film under the condition below.
Sputtering target: Ti
Underlayer temperature: 150 ℃
Ar/N
2Flow: 40/85sccm
Pressure: 4mTorr
Sputtering power: 1100W
Can be formed on the collimated sputtering of contact hole bottom or the deposit that long slow sputter realizes the TiN film by TiN (or TiON) film that allows to have enough big thickness, realize that therefore high-performance builds the formation of film.
For the formation of TiON film, above-mentioned condition changes to Ar/N a little
2/ O
2Flow: 30/10/85sccm.In addition, by sputtering target is become Ta from Ti, can form high melting point metal film (constituting) and nitride film or oxynitride film (for example TaNx, TaOxNy) according to said method by Ta.
For conductive, the compound that can select to have high evaporation pressure is WE for example
6Metal.For example, realize the nucleation of tungsten (W) below under the condition.
Underlayer temperature: 430 ℃
Gas flow: WF
6/ SiH
4Be 7-20/4sccm
Pressure: 4Torr
Time: 30-50 second
In addition, the formation of tungsten (W) layer realizes under the condition below.
Underlayer temperature: 450 ℃
Gas flow: WF
6/ H
2/ Ar is 80/7/20sccm
Pressure: 50-80Torr
Formation speed: per minute 0.3 μ m is to 0.5 μ m
Then, conductive layer is carried out anisotropy eat-back, so it is only stayed on the contact hole.That is, under the anisotropic etching condition, on conductive layer, carry out dry etching to expose adhesion layer.Particularly, adopt magnetic microwave plasma etching machine to carry out dry etching under the condition below.
Gas flow: SF
6Be 140sccm
High-frequency bias power: 200W
Pressure: 270Pa
Underlayer temperature: 30 ℃
By monitoring F
+Light emissive porwer (at the 704nm wavelength) and survey finishing of tungsten etch is wherein worked as F
+The light emissive porwer becomes big (perhaps its differential value becomes big), and in time, surveyed.Can carry out tungsten etch and remove from interlayer dielectric, so interlayer dielectric is exposed to the surface up to adhesion layer.
Can adopt additive method for example inlaying process and dual damascene method formation adhesion layer and conductor layer.In this situation, form adhesion layer and contact bolt by sputter, CVD method or plating; Then, the bolt material of removing the part of the adhesion layer of not expecting and not expecting by the CMP method; Therefore, can embed contact hole to bolt.
For the contact hole material that is carried out inlaying process, can replace for example W and adopt Al or Al alloy for example Al-Si and Al-Si-Cu of refractory metal, perhaps can adopt Cu or Cu alloy for example Cu-Cr, Cu-Zr, Cu-Ag and Cu-Pd.Can introduce preliminary treatment as required before CMP, the Semiconductor substrate that wherein has adhesion layer and contact bolt is carried out heat treatment, reflow treatment and planarization.
In above-mentioned, contact hole and base metal are to form under the predetermined condition that is similar to the formation of W bolt; After this, form above-mentioned layer by the sputter under the condition below:
Sputtering target: Al-Si alloy
Underlayer temperature: 200 ℃
Ar flow: 33sccm
Pressure: 2mTorr
Sputtering power: 900W
As mentioned above, after the formation of bolt material is finished, under vacuum condition, under 400 ℃ to 550 ℃ predetermined temperature, Semiconductor substrate is being heat-treated and reflow treatment; Therefore, can finish the embedding of contact hole.
For the bolt material, can adopt Cu or Cu alloy for example Cu-Cr, Cu-Zr and Cu-Pd, wherein sputtering target becomes Cu or Cu alloy.Certainly, can on Cu or Cu alloy, carry out plating.
Then, will describe formation and composition second polysilicon layer and second metal level (constituting) in detail by metal silicide.Second polysilicon layer and second metal level as fuse and lead form and carry out composition on above-mentioned interlayer dielectric and contact bolt.
In above-mentioned, carry out the polysilicon deposit by the above-mentioned technology shown in Figure 25 B and the 25C; Therefore, do not provide the description of repetition.
At first, will provide forming and the description of structure about second polysilicon layer and second metal level (constituting) by metal silicide.Because the variation of fuse may form second polysilicon layer or second metal level basis as fuse and lead.When only forming second polysilicon layer, the resistance of fuse and lead may increase; Yet, can reduce the thickness of second polysilicon layer.Such advantage is that fuse can form multilayer.
When only forming second metal level, may reduce second metal layer thickness and reduce fuse and the resistance of lead.The transistorized driving force that the advantage that reduces fuse resistor is to produce the turn-off current that is used for fuse can reduce; Therefore can improve integrated level and reduce electrical power consumed.
In addition, the formation order can change; That is, can on second metal level, form second polysilicon layer.This has reduced and the contact resistance that is embedded in the bolt in the following contact hole; Therefore, can further reduce conductor resistance between fuse and the transistor.
Can introduce three-decker, wherein second polysilicon layer is clipped between the lower metal layer (or metal silicide layer).In this situation, each all reduces thickness with about 1/2 the factor last lower metal layer, and the thickness of second polysilicon layer is constant.Such advantage is not increase gross thickness (or not forming the ladder difference of not expecting) and realizes constant fuse resistor.
Above-mentioned is favourable, because it can reduce and be embedded in down the contact resistance between the interior bolt of contact hole; And it can reduce and be embedded in the contact resistance between the interior bolt of through hole.
Can be the deposition thickness that each second polysilicon layer and second metal level (or second metal alloy layer or second high melting point metal silicide layer) are selected expectation according to the turn-off characteristic of fuse.For example, the thickness that depends on second polysilicon layer of the relation between sheet resistance (being fuse resistor) and the turn-off characteristic preferably changes from 100nm to 300nm from 50nm to 500nm.
The thickness of second high melting point metal silicide layer (or second metal level or second metal alloy layer) preferably changes from 100nm to 300nm from 50nm to 500nm.When allowing fuse resistor to increase according to the transistor driving ability, preferred second high melting point metal silicide layer is compared thickness with second polysilicon layer and is reduced.This is because second high melting point metal silicide layer is compared with second polysilicon layer and had very high fusing point, and therefore is very difficult to be disconnected by thermal stress.
For example refractory metal silicide (for example WSix, TiSix, TaSix and MoSix) and transition metal (for example NiSix, CoSix and CrSix) constitute by sputter or CVD method second high melting point metal silicide layer by predetermined material.
In above-mentioned, adopt the sputtering target of Wsix (wherein component factor x is based on the characteristic of metal silicide and in the range of the preferred 2.0≤x in 1.5≤x≤3.5≤3.0) to carry out sputter.Describe below and the component factor x of WSi is made as 2.7 carries out.
Above-mentioned second high melting point metal silicide layer can be replaced by second metal level or second metal alloy layer, wherein can adopt refractory metal for example Mo, Ti, Ta and W, transition metal is Co, Cr, Hf, Ir, Nb, Pt, Z and Ni for example, and the alloy that is made of above-mentioned metal.And, for example can form metal silicide based on reaction by heat treatment with polysilicon layer.
After finishing, polysilicon layer formation heat-treats.That is, before interlayer dielectric forms and after the deposit of refractory metal silicide, heat-treat, therefore reduce the resistance of the polycide gate electrode of fuse and employing refractory metal silicide.Above-mentioned heat treatment has been avoided by being applied to heat treatment on the metal silicide for example by separating between the metal silicide that quenching heat treatment caused and the polysilicon that are applied on the interlayer dielectric.
Can adopt diffusion furnace or carry out above-mentioned heat treatment by RTA.For example, RTA carried out ten seconds at 950 ℃, 1000 ℃, 1050 ℃, 1100 ℃ and 1150 ℃ respectively, with the average initial resistance of detection fuse and the relation between the turn-off characteristic (promptly realizing the turn-off current that fuse disconnects fully).The result is shown in the table 2, and table 2 shows the relative valuation as with reference to value " 100 " time separately of the average resistance of 950 ℃ of measurements and turn-off current.
Table 2
| 900℃ | 950℃ | 1000℃ | 1050℃ | 1100℃ | 1150℃ | |
| |
112 | 100 | 90 | 80 | 64 | 62 |
| Turn-off current | 94 | 100 | 114 | 128 | 152 | 162 |
The average initial resistance that The above results illustrates the fuse that adopts silicide film reduces and increases along with the RTA temperature.By apply the estimation about turn-off characteristic that turn-off current is measured to the fuse with the MOS transistor that drives under 5V, little turn-off current can realize that fuse disconnects.Particularly, the average initial resistance of fuse is along with the RTA temperature is reduced to 900 ℃ and linear increasing from 1100 ℃.On the contrary, turn-off current is along with the RTA temperature is reduced to 950 ℃ and reduce from 1100 ℃, step-down in the scope of its changing down between 950 ℃ and 900 ℃ wherein, and turn-off current can slowly reduce along with the reduction of RTA temperature in this scope.The changing down of estimating turn-off current is at 900 ℃ or following RTA temperature step-down.
Along with the increase of the average initial resistance of fuse, transistor may bear high capacity; Therefore, they may not can produce always and cause that fuse disconnects required turn-off current.In other words, when the MOS transistor with predetermined driving force (being preliminary dimension) was used for the fuse open circuit, it was favourable that fuse resistor reduces.This allows fuse to be disconnected by the low relatively turn-off current that small-geometry transistor produced, and this has improved integrated level successively and has reduced manufacturing cost.
Transistor properties depends on the diffusion that is caused by heat treatment; Therefore, preferred heat treatment is carried out under low relatively temperature.Particularly, 1000 ℃ or above heat treatment can change the Impurity Distribution in the transistor diffusion layer that formed greatly before fuse annealing; Therefore, be difficult to keep the transistor characteristic expected.Because the above-mentioned restriction that produces from transistor, preferred RTA temperature is lower than 950 ℃.
As mentioned above, preferably required according to initial resistance, turn-off current and the transistor of fuse condition is carried out RTA at 950 ℃ or following predetermined temperature.According to the effect of the RTA that is applied to metal silicide, preferably variation of temperature from 600 ℃ to 950 ℃.According to the effect of the separation of avoiding causing by quenching heat treatment, preferably variation of temperature from 800 ℃ to 950 ℃.RTA carried out 1 second to 120 seconds, preferred 5 seconds to 30 seconds.Describe below by carrying out 10 seconds RTA and undertaken.
By using transition metal or their silicide, can further reduce temperature.That is, preferably from 400 ℃ to 800 ℃ preferably from carrying out 1 second to 120 seconds under 450 ℃ to 600 ℃ the predetermined temperature preferably from 5 seconds to 30 seconds RTA.When adopting CoSi
2The time, can be at 550 ℃ of RTA that carry out 10 seconds.
Can adopt diffusion furnace to heat-treat being similar under the condition of RTA, under this condition, according to the anti-separating effect that overcomes quenching heat treatment and from 600 ℃ to 950 ℃ preferably from 800 ℃ to 950 ℃ predetermined temperature carry out 5 minutes to 90 minutes preferred 15 minutes to 30 minutes.Adopt transition metal to reduce temperature; Therefore, heat-treated 5-30 minute, preferably carried out 5-10 minute at 450-600 ℃ at 400-800 ℃.
Can be after the gate electrode composition, be used for carrying out above-mentioned heat treatment after the formation of oxidation film of sidewall spacers or after the formation of sidewall spacers.
Before or after heat treatment, can form processing by composition and have the required anti-reflective film of minute sized fuse.Certainly, not to need to form this anti-reflective film always.
This anti-reflective film is to form by deposit TiN or TiOxN (wherein the component factor x of oxygen changes from 5atm% to 30atm%, and thickness preferably changes from 30nm to 60nm from 10nm to 100nm).By for example adopting the DC magnetron sputtering apparatus, adopting sputter gas (corresponding to Ar, N
2And O
2Mixture) reactive sputtering realize deposit.
And after the formation of metal level is finished, can carry out silicidation reaction by the heat treatment that is applied to TiO film or TiON film.
Anti-reflective film reduces by the caused reverberation of the lip-deep suicide element of fuse, wherein can realize the photoetching of retrofit.Can after the composition of fuse, remove anti-reflective film by etching.On the basis that anti-reflective film is removed, can stablize the turn-off characteristic of fuse and reduce turn-off current.
Then, the formation of the sidewall spacers and second interlayer dielectric will be described in detail.
At first, formation is used as the dielectric film of sidewall spacers to cover fuse; Then, remove the planar section of dielectric film by anisotropic etching; Therefore, can on the sidewall of fuse, form sidewall spacers with convergent shape.The heating part of the thickness decision fuse of sidewall spacers and the distance between the sog film, wherein thermal insulation effect becomes big along with thickness and uprises, and this increases the load in the dry etching successively.Therefore, preferred thickness preferably changes from 200nm to 500nm from 150nm to 700nm.
The dielectric film of realizing conformal covering has the thickness that is beneficial to the increase sidewall spacers, and wherein oxidation film, nitrogen film or oxynitride film can form by the preordering method that is suitable for LP-TEOS and PL-TEOS.In addition, can form fluorine-containing dielectric film (for example oxidation film and oxynitride film) and bias voltage (bias) CVD dielectric film.
Can select various materials to be used for the formation of sidewall spacers.The predetermined material that selection is used for the formation of sidewall spacers and is different from the material that is formed on the lip-deep dielectric film of interlayer dielectric can improve etched enforceability.
For example, (wherein TEOS represents tetraethyl orthosilicate to the LP-TEOS oxidation film, i.e. Si (OC
2H
5)
4Form under the condition below.
Underlayer temperature: 700 ℃
Material gas: TEOS/O
2Be 60/0-5sccm
Reaction chamber pressure: 0.25Torr
Thickness: 350nm
Can be in a similar fashion by using the SiH of 40/400sccm
2Ci
2/ NH
3(or NH
3+ N
2) material gas and form nitride film.
The PL-TEOS film forms under the condition below.
Underlayer temperature: 400 ℃
Material gas: TEOS (per minute 1.8cc is with the liquid supply) and O
2(8000sccm)
Reaction chamber pressure: 2.5Torr
Plasma power: 1000W
Thickness: 450nm
In a similar manner by using TEOS (per minute 1.8cc is with the liquid supply) and O
2Or N
2The material gas of ((8000-x) sccm) and form oxynitride film, wherein x changes from 0sccm to 5000sccm.
By adopting parallel-plate-type plasma etching machine that above-mentioned dielectric film is carried out anisotropic etching to form sidewall spacers on the sidewall of fuse under the condition below.
The CHF of etching gas: 27/4/88sccm
3/ O
2/ He
Pressure: 2Torr
RF power: 450W
Because oxidation film, the formation that is etched in sidewall spacers stops after finishing, and does not wherein have oxidation film to be retained on the plane surface basically.
Concrete diagram is not provided, but the preferred oxides film can with etching irrespectively part be retained on the plane surface, thereby do not enlarge because the ladder that the over etching of dielectric film causes is poor.
Adopt parallel-plate-type plasma etching machine under the RF power of the pressure of 0.1Torr and 400W, above-mentioned nitride film to be carried out etching.Here, the formation that is etched in sidewall spacers stops after finishing, and wherein to become be zero to the thickness of planar section substantially.As selection, stop etching by staying dielectric film on plane surface top.
Then, form first insulating barrier (for example oxidation film, oxynitride film or fluorine-containing dielectric film) to cover sidewall spacers.By increasing its thickness, the thickness of first dielectric film is improved aspect thermal insulation, and this defines the heating part of fuse and the distance between the sog film successively.Yet first dielectric film with big thickness has increased the load in handling and has also increased the gross thickness of interlayer dielectric, thereby this degree of depth that increases contact hole successively is increased in the load in the dry etching and increases the resistance of bolt.Therefore, preferred thickness more preferably changes from 250nm to 500nm from 150nm to 800nm.
And, can realize first dielectric film by in above-mentioned LP-TEOS oxidation film, nitride film, PL-TEOS oxidation film, oxynitride film, fluorine-containing dielectric film and the bias voltage CVD dielectric film any one.
For first dielectric film, can form silicon oxide film by the plasma CVD method under the condition below:
Underlayer temperature: 400 ℃
The SiH of material gas: 240/5000/2800sccm
4/ N
2O/N
2
Reaction chamber pressure: 2.2Torr
Thickness: 300nm
Certainly, can form above-mentioned LP-TEOS oxidation film, nitride film, PL-TEOS oxidation film and oxynitride film.
In addition, form fluorine-containing oxidation film under the condition below.
Underlayer temperature: 450 ℃
The TEOS/O of material gas: 50/250/250sccm
2/ C
2F
6
Reaction chamber pressure: 3.0Torr
Plasma power: 600W
Then, use another dielectric film to cover above-mentioned first dielectric film.In order to improve the thermal insulation that antagonism disconnects the heating of fuse, the outer dielectric film that covers that preferably has covered structure is made of inorganic SOG, organic SOG, HSQ and RSQ.Particularly, because low thermal insulation, including organic compounds, externally to cover dielectric film be favourable, and low thermal insulation can cause STRESS VARIATION, the degassing and mass change owing to the heating of fuse.
For being used for the outer material that covers dielectric film, can adopt the HSQ resin that spin coating is carried out in dissolving then to it in MIBK, with the predetermined cladding thickness of realizing from 300nm to 700nm, preferably from 350nm to 550nm, changing.Following description is to make about the thickness of 450nm.
Then, under low relatively temperature, in inert gas, the Semiconductor substrate that is coated with the HSQ resin is heat-treated, desolvate to remove, thereby the film that applies changes pre-ceramic silicon oxide film (pre-ceramic silicon oxide), wherein N into from it
2Gas is used as inert gas, and in the heat treatment of carrying out 1 minute to 60 minutes from 150 ℃ to 350 ℃ predetermined temperature.Heat treatment can be carried out in the rapid mode of multistep.For example, at N
2In the atmosphere Semiconductor substrate is placed on the hot plate, and then to its baking, 150 ℃ carry out one minute, carried out one minute and carried out one minute at 200 ℃ at 300 ℃.
Then, adopting inert gas (N for example
2) atmosphere in, carrying out another heat treatment of 5-120 minute from 350 ℃ to 550 ℃ predetermined temperature, this inert gas can oxide gas or the mist of inert gas and oxide gas replace.For example, at N
2In the atmosphere, 400 ℃ of heat treatments of carrying out 10 minutes.
For the material of the dielectric film that covers outward, can adopt organic SOG, its predetermined thickness with 300nm is applied to Semiconductor substrate, adopts hot plate at N then
2In the atmosphere it is toasted, 150 ℃ carry out one minute, carried out one minute and carried out one minute at 200 ℃, then at N at 250 ℃
2In the atmosphere, it is carried out 30 minutes annealing at 400 ℃.As selection, can adopt inorganic SOG, in identical atmosphere, it is annealed in a similar fashion.
Above-mentioned covering dielectric film is carried out suitable eat-backing outward, therefore covers dielectric film outward basically and is retained on the fuse, and perhaps it is retained on the fuse a little not reduce reliability.Adopt under the parallel-plate-type plasma etching machine condition below and eat-back.
Dry etching gas: CHF
3And CF
4Be combined as 40sccm, and He is 88sccm
Pressure: 2Torr
Power: 275W
CHF
3/ CH
4Gas ratio: 30-70%, preferred 40-55%
In above-mentioned, one section predetermined etching period dry etching stops, at this moment between inside and outside the dielectric film that covers only remove from first dielectric film.
In addition, can set identical etch-rate with the dielectric film that covers outward for first dielectric film.As selection, etch-rate can so be set, make the speed of eat-backing of the outer dielectric film that covers carry out slightly faster than the etching of first dielectric film.Therefore, can selectively remove the outer dielectric film that covers that is retained on first dielectric film that covers fuse, and not reduce the surface smoothness of the outer dielectric film that covers.
Then, on the outer dielectric film that covers that is coated on the Semiconductor substrate, form second dielectric film.Because the thickness of second dielectric film defines the heating part of fuse and the distance between the sog film, according to thermal insulation, preferred second dielectric film has big thickness.Yet if second dielectric film has very large thickness, this may increase load, the thickness of interlayer dielectric and the degree of depth of contact hole in its formation, and this increases etching load and bolt resistance successively.Therefore, preferred thickness more preferably changes from 250nm to 500nm from 150nm to 800nm.
For second dielectric film, can optionally form above-mentioned LP-TEOS oxidation film, nitride film, PL-SiH
4In oxidation film (or its oxynitride film or its nitride film), PL-TEOS oxidation film (or its oxynitride film) and the fluorine-containing dielectric film any one.
For second dielectric film, can be by adopting TEOS, the O of 7.5slm of 2.5slm
2, 85g/Nm
3O
3, and the N of 18slm
2, form the thick LP-TEOS dielectric film of 500nm at 400 ℃ underlayer temperatures.
In order to improve evenness, realize smooth and smooth surface thereby can carry out CMP as required by removing the step difference that is retained in the second dielectric film surface.In this situation,, preferred second dielectric film can not be exposed to the surface by the following sog film of handle because of CMP thereby can having enough big thickness.This be because, though so sog film is carried out annealing and changes pottery into, it has relatively little chemical stability, therefore owing to CMP in the polishing fluid that uses contact and cause and separate and form the crack, and owing to the chemically cleaning that is used for removing particulate after CMP causes the local etching.
When carrying out the CMP of 500nm on second dielectric film with 1000nm thickness, after CMP, do not have second dielectric film to keep basically, thereby sog film is not exposed to the surface.Here, the minimum thickness of second dielectric film depends on the shape of the ladder difference below it, but can preferably change from 100nm to 200nm.
Then, the formation of the bolt and the lead of through hole, embedding will be described with reference to figure 29A.
Particularly, through hole is formed in second interlayer dielectric, and the W bolt is embedded in wherein, and the lead film forms also patterned.By sputter, adopt electric conducting material for example Al or Al alloy (for example Al-Si, Al-Si-Cu) and copper or copper alloy (for example Cu-Cr, Cu-Zr, Cu-Ag and Cu-Pd) formation lead film.For example, adopt the Al-Si-Cu target to carry out sputter under the condition below.
Underlayer temperature: 150 ℃
Ar flow: 18sccm
Pressure: 8mTorr
Sputtering power: 1200W
Can before the lead film forms, form as required and build film.This base film is made of TiN or TiON, wherein can form the sandwich construction that is made of Ti/TiN (TiON) or Ti/TiN (TiON)/Ti.In addition, can on the lead film, form epiphragma (or the anti-reflective film that constitutes by Ti/TiN (TiON)) as required.
Can be by under vacuum condition, heat-treating the leveling of quickening the lead film with reflow treatment.Adopt the Al-Si alloys target that the lead film is carried out sputter below under the condition.
Underlayer temperature: 200 ℃
Ar flow: 33sccm
Pressure: 2mTorr
Sputtering power: 900W
Under vacuum condition, the lead film of the material layer that is formed for bolt is being heat-treated and reflow treatment from 400 ℃ to 550 ℃ predetermined temperature.
And, for the formation of the bolt and the lead film of through hole, embedding, can adopt inlaying process or dual damascene method.Particularly, form above-mentioned adhesion layer, contact bolt and lead by sputter, CVD method or plating; Then, carry out CMP to remove unwanted part about adhesion layer and bolt material; Therefore, can form bolt and lead.
Then, will be with reference to the formation of figure 29B description list surface protective film and pressure welding point.That is, thus forming passivating film covers the predetermined pattern that is formed on the semiconductor substrate surface as surface protection film; Then, by photoetching and dry etching to as the pressure welding point of outside terminal and the delineation line that is used to cut apart chip carry out Hall technology.
By the CVD method, from 50nm to 200nm, change NSG or the SiO that preferably has 100nm thickness by consecutive deposition thickness
2, and thickness from 600nm to 1200nm, change the SiN that preferably has 1000nm thickness or SiON and form its thickness changes and preferably be made as 1.1 μ m from 0.8 μ m to 1.4 μ m passivating film.Therefore, can finish the simulation MOS integrated circuit of manufacturing cross section structure shown in Figure 29 B.
Then, will describe the various structures be formed near the sidewall spacers the fuse with reference to figure 30-36, these illustrate the sectional view of being got along the line B-B of Figure 28.
Figure 30 shows basic structure, and wherein fuse forms together with three-decker, and this three-decker is made of first dielectric film, sog film and second dielectric film.Figure 31 shows first example of fuse-wires structure, and wherein sidewall spacers is formed on the sidewall of fuse.
Figure 32 shows second example of fuse-wires structure, and wherein sidewall spacers does not form after fuse forms immediately, but forms after first dielectric film forms.This can reduce the fluctuation of fuse characteristics effectively, because because the load that reduces in handling, in the formation of sidewall spacers, the policide surface will can directly not be exposed to etching environment (for example plasma gas and ionic bombardment).In addition, thus its advantage is the ladder difference shape of first dielectric film can improve the leveling that easily realizes sog film.
Figure 33 shows the 3rd example of fuse-wires structure, and wherein sidewall spacers forms after fuse forms immediately, then, forms another sidewall spacers after first dielectric film forms.Thereby this distance that has further increased between fuse and the sog film has further improved the thermal insulation that the opposing fuse disconnects; Therefore, can further reduce destruction to sog film.
Figure 34 shows the 4th example of fuse-wires structure, and wherein the fuse-wires structure for the above-mentioned Figure 31 of formation after first dielectric film forms of sidewall spacers has wherein carried out the convergent processing.This allows to be attached to the predetermined portions that the first dielectric film coverage rate reduces by the attachment material again that the convergent technology that is applied to dielectric film is produced.Because first dielectric film reduces can not reduce the distance between fuse and the sog film basically in low coverage rate.
By adopting for example the grinding (milling) or adopt O of Ar gas of inert gas
2Or the convergent etching of Ar and realize above-mentioned processing.The careful thickness of determining first dielectric film carries out with 45-60 ° inclination angle from the observation of fuse upper end tempestuously because convergent is etched on the predetermined portions of first dielectric film.For example, preferably adopt thickness from 300nm to 1000nm more preferably the PL-TEOS oxidation film from 500nm to 800nm form first dielectric film.
In addition, carrying out Ar under the condition below grinds.
Ar flow: 4sccm
Pressure: 2.0E-4Torr
Power: 500V, 190mA
Cooling water temperature: 23 ℃ (underlayer temperature: 40-120 ℃ here)
Grind the angle: 45-80 ° (preferred 60 °)
Taper angle: 60-45 °
Adopt anode to connect (anode-connection down-flow) the type etch device that flows downward below under the condition and carry out the etching of Ar convergent.
Ar flow: 100sccm
Pressure: 0.1Torr
RF power: 800-1200W
Underlayer temperature: 100 ℃
Taper angle: 60-45 °
Adopt the ECR etching machines to carry out O below under the condition
2The convergent etching.
O
2Flow: 100sccm
Pressure: 0.01Torr
Microwave power: 300mV
RF power: 150W
Underlayer temperature: 40 ℃
Taper angle: 80-60 °
Can use SOG to first dielectric film with above-mentioned convergent shape.As selection, as shown in figure 34, can form the PL-TEOS oxidation film that thickness preferably changes from 100nm to 500nm from 250nm to 350nm.
Fuse-wires structure shown in Figure 35 is characterised in that first and second dielectric films form twice on fuse.That is, be substituted in fuse had and carry out convergent on first dielectric film of relative low cover degree and handle, directly form dielectric film below under the condition by forming bias voltage CVD dielectric film with convergent shape.
Underlayer temperature: 400 ℃
The SiH of material gas: 45/55/70sccm
4//O
2/ Ar
Microwave power: 2000W
RF power: the 13.56MHz place is 1400W
Reaction chamber pressure: 2mTorr
The thickness of preferred dielectric film preferably changes from 500nm to 800nm from 300nm to 1000nm.
Therefore, first dielectric film with convergent shape reduces at the thickness from its predetermined portions of the 45-60 ° of inclination angle observation in fuse upper end.Therefore, may need to form another dielectric film and cover the fuse upper end.Preferably the PL-TEOS oxidation film that preferably changes from 350nm to 600nm from 200nm to 800nm by used thickness forms dielectric film.
Figure 36 shows the fuse-wires structure that wherein adopts a plurality of polysilicon layers or a plurality of policide layer to form fuse.In above-mentioned example, (see Figure 28, Figure 25 A-25D and Figure 29 A-29B), form at least one fuse between first and second interlayer dielectrics, but the fuse-wires structure of Figure 36 is designed to form fuse between a plurality of interlayer dielectrics.
As previously mentioned, the 3rd embodiment has improved the reliability of semiconductor integrated circuit, because reduced for the thermal stress as the sog film of interlayer dielectric, the degassing of the dielectric film that covers outward is suppressed, and the dielectric film that covers outward is indeformable and do not form crackle.Therefore, repeat to use the above-mentioned manufacturing process of polysilicon layer and policide layer, comprise the array of fuses of a plurality of fuses that link to each other with multilayer with manufacturing.
The advantage of present embodiment is, significantly reduced step difference in the stacked interlayer dielectric thereby reduced lower step difference by LOCOS method and STI method, and wherein by above-mentioned silicide process, the resistance and the thickness of transistor and diffusion layer reduce.
Particularly, being formed on first array of fuses on the sti structure is to be used for same material that gate electrode forms and the silicide process of step forms by employing; And second array of fuses is formed on the transistor; And the 3rd array of fuses further forms thereon.
Above-mentioned laminated construction is preferred for forming the information reading circuit that adopts a plurality of fuses.It reduces to have the gross area of the silicon substrate of a plurality of fuses; It improves integrated level; And it reduces manufacturing cost.
In addition, the convergent shape is applied to the sidewall of fuse or the dielectric film of covering fuse; Therefore, can increase fuse and the dielectric film that covers outward between distance.As a result, can reduce to be applied to the outer heat stress of insulating film of covering; Can suppress the degassing of the outer dielectric film that covers; Can prevent that the outer dielectric film that covers is out of shape undesirably; Can avoid covering outside and form crackle in the dielectric film; And therefore can improve the reliability of semiconductor integrated circuit.In addition, sidewall spacers is formed on the fuse sidewall; And sidewall spacers can also be formed on the dielectric film that covers fuse; Therefore, can further increase distance between fuse and the interlayer dielectric.
On the dielectric film that covers fuse, carry out Ar etching or O
2Be etched with and realize the convergent shape.As selection, on the dielectric film that covers fuse, grind.Therefore, can reduce to be applied to thermal stress on the dielectric film that covers outward by increasing fuse and distance between the dielectric film that covers outward.
When fuse is applied to pulse on it when disconnecting, present embodiment also reduces to be applied to the physics and the heat damage of fuse.Particularly, from 400 ℃ of predetermined temperatures fuse is being heat-treated to 900 ℃ of variations; Therefore can reduce transistorized heat damage and improve the turn-off characteristic of fuse.
4. the 4th embodiment
Known when crossing conductor, high-current flow in constituent atoms or molecule electromigration takes place.Need the long relatively time to realize that fuse disconnects by electromigration; Yet, wish that electromigration can be accelerated when high-current flow is crossed the lead of heating, and can further quicken electromigration by the thermal stress that Joule heat causes.
Figure 37 shows the example of fuse open circuit, and wherein fuse 201 is in series connected to n channel MOS transistor (being MOSFET) 203.The terminal 201a of fuse 201 has been supplied driving voltage Vdd, and another terminal 201b is connected to the drain electrode 205a of transistor 203.The source electrode 205b of transistor 203 is grounded (at Vss).Pulse signal Vp is applied to the grid 205c of transistor 203.As grid 205c when being high, thereby transistor 203 is switched on and makes electric current flow through fuse 201.When very high electric current flow through fuse 201, the temperature of fuse 201 was owing to Joule heat increases, thereby fuse 201 disconnects owing to fusing and evaporating.
Figure 38 is the plane graph that the semiconductor device of the fuse open circuit that comprises Figure 37 is shown.Figure 39 is the sectional view that the line C-C along Figure 38 is got.
Shown in Figure 38 and 39, isolated area 202a, 202b and 202c are formed on the p N-type semiconductor N substrate 211 by LOCOS (being the local silicon oxidation) method, and this LOCOS method can be replaced by STI (be shallow trench isolation from) method.Being used to form transistorized active area is limited by isolated area 202a, 202b and 202c.P trap Wp is formed in the active area to form the n channel transistor.N trap Wn is formed on below the isolated area 202c (being the LOCOS oxidation film) avoiding and is caused being short-circuited by the crackle that is formed among the LOCOS oxidation film 202c when fuse disconnects.In addition, the p trap contact zone Wc formation that links to each other with p trap Wp.
The gate insulating film 215a that is made of silica is formed on the active area by thermal oxidation method.The polycide gate electrode 217 that is made of polysilicon layer 217a and tungsten silicide layer 217b is formed on the gate insulating film 215a.Here, concentration is about 10
20Cm
-3N type doping impurity to polysilicon.And policide can be equal to self-aligned silicide (salicide) (or silicide) substantially; Therefore, can only adopt polysilicon to form gate electrode 217.
Being used to form the policide layer (or polysilicon layer) 223 of fuse 223 and the formation of isolated area 202c is formed on the isolated area 202c simultaneously.
After the formation of sidewall spacers 215b was finished, (its concentration was from 10 for high concentration n type impurity
20Cm
-3To 10
21Cm
-3Change) be introduced into the both sides of the gate electrode 217 on the p N-type semiconductor N substrate 211.Source region 205a and drain region 205b are formed in the p trap Wp on gate electrode 217 both sides.In addition, thus impurity is introduced in gate electrode 217 and fuse 223 reduces its resistance.
The interlayer dielectric 221 that formation is made of silica, PSG or BPSG is to cover gate electrode 217 and the policide layer 223 on the Semiconductor substrate 211. Opening 218a, 218b and 218c are formed in the interlayer dielectric 221 to arrive source region 205a, drain region 205b and the trap contact zone Wc about gate electrode 217.In addition, opening 225 and 227 is formed in the interlayer dielectric 221 two ends with the upper surface that arrives policide layer 223.
By sputter, the adhesion layer that is made of Ti, TiN or TiON forms and is embedded among opening 218a, 218b, the 218c, 225 and 227; Then, by CVD method deposit tungsten layer; Therefore, can form conductive plugs 228.Remove the unwanted part of conductive layer by CMP; After this, the lead of realizing by the lamination that is made of TiN/Ti/Al/Ti (or TiN) is deposited on the interlayer dielectric 221 and is carried out composition then, therefore forms conductor layer 231a, 231b and 231c.
Therefore, can produce the fuse open circuit that comprises fuse 201 (corresponding to fuse 223) and transistor 203 (being MOSFET).
Fuse turn-off characteristic and experimental result have been described in conjunction with Fig. 1, Fig. 2 A (or Figure 14), Fig. 3, Figure 17 and table 1; Therefore, no longer provide the description of repetition.
The fuse breakdown method that is applicable to the 4th embodiment has been described in conjunction with Figure 16 A and 16B, except following minor variations:
In step S27, make the decision whether pulse number reaches " 14 ", perhaps make the decision whether total time reaches 2000ms.In step S28, make the decision whether resistance is equal to or higher than 1M Ω.In step S30, make the decision whether fuse number (being n) reaches maximum fuse number (being nMAX).
Figure 40 shows the memory circuit that comprises " n " level, its each all comprise fuse F and the transistor T 1 that is connected between power line and the earth connection.Thereby transistor T 2 also is connected in series to fuse F makes weak current flow through fuse F.
Figure 41 shows the truth table of the operation of presentation selector SEL, and wherein when input S was zero, input A appeared at output O, and when input S was " 1 ", output B appeared at output O.When the information read output signal was low and is applied to the input S of selector SEL, in response to shift signal, the output of trigger (flip-flop) FF was sent to next stage; Therefore, the n level together cooperation realize the n bit shift register.The synchronous cut-off signal of this information basis that allows represent fuse resistor and shift signal is transmitted n time.
Figure 42 shows the sequential chart about the signal of fuse opening operation.Here, shift signal comprises " n " individual pulse, thereby in each stage, disconnection/the information of disconnected phase does not appear at the output Q of trigger FF about fuse.Based on this information, can disconnect by make each fuse with clock signal driving transistors T1 with pulse.Inferior by repeating aforesaid operations " m ", can realize that fuse disconnects with " m " individual pulse.Can be by the characteristic of suitably selecting transistor T 2 the regulating impulse energy.In addition, can control pulse duration with respect to the time span of clock signal.
Figure 43 shows about determining that fuse disconnects/signal timing diagram of off-state not.Here, the initial setting up of information read output signal in the high level cycle, in this cycle by applying individual pulse, about fuse disconnect/the information of off-state is not transferred to another level from one-level.After this, the information read output signal is arranged on the low-level cycle, therefore realizes adopting multistage displacement resistor to connect.Therefore, about the fuse disconnection/the information of off-state is synchronously exported continuously with the clock signal with (n-1) individual pulse.
At last, the present invention does not need to be confined to the foregoing description, and these embodiment are schematic rather than restrictive; Therefore, the institute in category of the present invention changes and is out of shape all and is included within the present invention.
The present invention requires the priority of the Japanese patent application of Japanese patent application 2005-99404,2005-101481 and 2005-103542 number, and its content quotation herein as a reference.
Claims (6)
1, a kind of semiconductor device comprises:
Semiconductor substrate; With
At least one fuse has the sidewall that is formed on the convergent on the described Semiconductor substrate.
2, semiconductor device according to claim 1, wherein said at least one fuse comprises:
Paired terminal is formed separately from each other; With
The interconnect portion that is used for interconnected described terminal, wherein said interconnect portion are compared width with described terminal and are reduced.
3, a kind of semiconductor device comprises:
Semiconductor substrate;
At least one fuse is formed on the described Semiconductor substrate; With
At least one dielectric film covers described fuse,
Wherein said dielectric film is carried out anisotropic etching, thereby its planar section is removed so that the sidewall spacers with convergent shape to be provided on the sidewall of described fuse.
4, a kind of semiconductor device comprises:
Semiconductor substrate;
At least one fuse is formed on the described Semiconductor substrate; With
At least one dielectric film covers described fuse,
Wherein said dielectric film is used Ar or O
2Gas is etched with and forms the convergent shape.
5, a kind of semiconductor device comprises:
Semiconductor substrate;
At least one fuse is formed on the described Semiconductor substrate; With
At least one dielectric film covers described fuse,
Wherein said dielectric film is carried out and grinds to realize the convergent shape therein.
6, a kind of manufacture method that is used for semiconductor device comprises the steps:
Form dielectric film, cover the fuse that is formed on the Semiconductor substrate; With
Carry out anisotropic etching,, therefore on the sidewall of described fuse, form sidewall spacers with convergent shape to remove the planar section of described dielectric film.
Applications Claiming Priority (6)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP099404/05 | 2005-03-30 | ||
| JP2005099404 | 2005-03-30 | ||
| JP101481/05 | 2005-03-31 | ||
| JP2005101481A JP2006286723A (en) | 2005-03-31 | 2005-03-31 | Semiconductor device and method of cutting fuse element in the device |
| JP103642/05 | 2005-03-31 | ||
| JP2005103642A JP5191628B2 (en) | 2005-03-31 | 2005-03-31 | Semiconductor device structure and semiconductor device manufacturing method |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 200610073319 Division CN100501973C (en) | 2005-03-30 | 2006-03-30 | Fuse disconnection method fit for semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101425502A true CN101425502A (en) | 2009-05-06 |
| CN101425502B CN101425502B (en) | 2012-07-11 |
Family
ID=37195462
Family Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 200610073319 Expired - Fee Related CN100501973C (en) | 2005-03-30 | 2006-03-30 | Fuse disconnection method fit for semiconductor device |
| CN 200810176729 Expired - Fee Related CN101425502B (en) | 2005-03-30 | 2006-03-30 | Fuse breakdown method adapted to semiconductor device |
Family Applications Before (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 200610073319 Expired - Fee Related CN100501973C (en) | 2005-03-30 | 2006-03-30 | Fuse disconnection method fit for semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| CN (2) | CN100501973C (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI555162B (en) * | 2009-09-25 | 2016-10-21 | 精工半導體有限公司 | Semiconductor integrated circuit device and manufacturing method thereof |
Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5133574B2 (en) * | 2007-02-13 | 2013-01-30 | セイコーインスツル株式会社 | Fuse trimming method of semiconductor device |
| US8598679B2 (en) * | 2010-11-30 | 2013-12-03 | Taiwan Semiconductor Manufacturing Company, Ltd. | Stacked and tunable power fuse |
| CN104051417B (en) * | 2013-03-13 | 2016-08-31 | 中芯国际集成电路制造(上海)有限公司 | Electric fuse structure and forming method thereof |
| KR102127178B1 (en) * | 2014-01-23 | 2020-06-26 | 삼성전자 주식회사 | e-fuse structure of a semiconductor device |
| CN104979356B (en) * | 2014-04-01 | 2018-07-06 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and the method for cut-out wherein storage unit block connection |
| US9455222B1 (en) * | 2015-12-18 | 2016-09-27 | Texas Instruments Incorporated | IC having failsafe fuse on field dielectric |
| KR102313601B1 (en) * | 2017-03-24 | 2021-10-15 | 삼성전자주식회사 | Method for operating memory device |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6121074A (en) * | 1998-11-05 | 2000-09-19 | Siemens Aktiengesellschaft | Fuse layout for improved fuse blow process window |
| US6804159B2 (en) * | 2001-11-06 | 2004-10-12 | Yamaha Corporation | Semiconductor device having fuse and its manufacture method |
-
2006
- 2006-03-30 CN CN 200610073319 patent/CN100501973C/en not_active Expired - Fee Related
- 2006-03-30 CN CN 200810176729 patent/CN101425502B/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI555162B (en) * | 2009-09-25 | 2016-10-21 | 精工半導體有限公司 | Semiconductor integrated circuit device and manufacturing method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1855426A (en) | 2006-11-01 |
| CN101425502B (en) | 2012-07-11 |
| CN100501973C (en) | 2009-06-17 |
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