CN101425490A - Chip and manufacturing method thereof - Google Patents
Chip and manufacturing method thereof Download PDFInfo
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- CN101425490A CN101425490A CN 200710165130 CN200710165130A CN101425490A CN 101425490 A CN101425490 A CN 101425490A CN 200710165130 CN200710165130 CN 200710165130 CN 200710165130 A CN200710165130 A CN 200710165130A CN 101425490 A CN101425490 A CN 101425490A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Apparatuses And Processes For Manufacturing Resistors (AREA)
- Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)
Abstract
The invention discloses a chip and a manufacturing method thereof. The manufacturing method of the chip comprises the following steps: arranging a plurality of first conducting gaskets on the chip along one direction, wherein the first conducting gasket comprises a first part and a second part relative to the first part, and the length of the first part along the direction is larger than that of the second part along the direction; and arranging a plurality of second conducting gaskets arranged with the first conducting gaskets in a staggered manner on the chip, wherein each second conducting gasket comprises a third part and a fourth part relative to the third part, and the length of each third part along the direction is larger than that of the fourth part along the direction. The direction from the third part to the fourth part is opposite to the direction from the first part to the second part. The chip and the manufacturing method thereof can ensure that the conducting gaskets are densely arranged on the chip; and the design of the conducting gaskets at the corner can reduce the pressure damage of the chip generated during the encapsulation process.
Description
Technical field
The present invention relates to a kind of chip and manufacture method thereof, and especially, the present invention relates to a kind of chip and manufacture method thereof of conduction liner design that closeer conduction liner is arranged and can be reduced the pressure damage of chip corner that have.
Background technology
Because semiconductor science and technology is fast-developing, the function of chip is more and more diversified in recent years.Correspondingly, the required circuit design of chip effect is also complicated day by day, and therefore, on one chip, play the part of provides the quantity of the conduction of electronic signal contact liner to increase thereupon.When the quantity of conduction liner surpasses to a certain degree, certainly will directly have influence on the size of chip, and the number of chips that brilliant unit of the unit of making can cut out reduces.So, the cost of chip production correspondingly improves.Moreover excessive chip also runs in the opposite direction with the product trend toward miniaturization of electronic industry now.Therefore, arrangement and the layout of conduction liner on chip becomes cost-effective important directions.
In the prior art, United States Patent (USP) notification number the 6th, 040,984 and 6,780 has disclosed the conduction liner of have dislocation (staggered pattern) and differing heights or thickness for No. 749, in order to reduce chip size.Referring to Fig. 1, Fig. 1 is the schematic diagram that the 6th, 040, No. 984 disclosed chips of United States Patent (USP) notification number are connected with circuit board.As shown in Figure 1, the conduction liner A2 that has differing heights (that is, dislocation) on conduction liner A1 on the chip C1 and the circuit board B1 is connected.Note that for the conduction liner on discrimination circuit plate and the chip, represent the conduction liner that is positioned on the circuit board with " contact " speech in this manual.In addition, United States Patent (USP) notification number the 6th, then power line-ground wire (power line-ground line) and holding wire (I/O) are made separate design 291, No. 898, so that the circuit board connection design corresponding to the conduction liner of dislocation design to be provided at the conduction liner of above-mentioned dislocation design.
On the other hand, the corner regions of chip is usually because of the stress that canned program produced sustains damage, and then makes the chip yield influenced.Therefore, if can solve the problem of chip corner unbalanced stress, can make and to utilize the space to become big on the chip and stable maintenance yield preferably.
Summary of the invention
Therefore, the object of the present invention is to provide a kind of manufacturing method of chip, to solve foregoing problems.
According to a specific embodiment, manufacturing method of chip of the present invention comprises the following step: at first, on chip, a plurality of first conduction liners (bondingpad) are set along preset direction, each first conduction liner comprises first and with respect to the second portion of first, and, each first along the length on the preset direction greater than each second portion along the length on the preset direction.Then, a plurality of second conduction liners are set on chip first to conduct electricity liner and is staggered with these, each second conduction liner comprises third part and with respect to the 4th part of third part, and, each third part along the length on the preset direction greater than each the 4th part along the length on the preset direction.Especially, from the tetrameric second direction of third part to the with the first direction to second portion is opposite from first.
Manufacturing method of chip of the present invention, wherein this chip is connected in corresponding a plurality of contacts of circuit board by these these conduction liner, and each conduction liner is connected with corresponding this contact by a wiring.
Manufacturing method of chip of the present invention, further comprise the following step: according on each the first conduction liner and the second conduction liner with this circuit board on the distance distance of this corresponding a plurality of contacts, adjustment is arranged at the solder sphere of respectively conducting electricity on liner and each contact or the size of projection, so that the resistance value of respectively should the conduction liner corresponding with it the respectively equivalent conductive path between this contact is approaching basically.
Manufacturing method of chip of the present invention, wherein according to each first the conduction liner and second the conduction liner area, on this these conduction liner, these these solder sphere or this these projections with different resistance values are set, so that the resistance value of respectively should the conduction liner corresponding with it the respectively equivalent conductive path between this contact is approaching basically.
Manufacturing method of chip of the present invention, wherein these these first conduction liner has the drops outward appearance.
Manufacturing method of chip of the present invention, wherein these these second conduction liner has the drops outward appearance.
Another object of the present invention is to provide a kind of chip, it has closeer conduction liner and arranges.
According to a specific embodiment, chip of the present invention comprises a plurality of first conduction liners and a plurality of second conduction liner.These the first conduction liners and the second conduction liner are along the interlaced arrangement of preset direction.Each first conduction liner comprises first and with respect to the second portion of first, and, each first along the length on the preset direction greater than each second portion along the length on the preset direction.Similarly, each second conduction liner comprises third part and with respect to the 4th part of third part, and, each third part along the length on the preset direction greater than each the 4th part along the length on the preset direction.Especially, opposite to the first direction of second portion from the tetrameric second direction of third part to the with first.
Chip of the present invention, wherein this chip is connected in corresponding a plurality of contacts of circuit board by these these conduction liner, and each conduction liner is connected with corresponding this contact by wiring.
Chip of the present invention, wherein according on each the first conduction liner and the second conduction liner with this circuit board on the distance distance of this corresponding a plurality of contacts, adjustment is arranged at this solder sphere of respectively conducting electricity on liner and each contact or the size of this projection, so that the resistance value of respectively should the conduction liner corresponding with it the respectively equivalent conductive path between this contact is approaching basically.
Chip of the present invention, wherein according to each first the conduction liner and second the conduction liner area, on this these conduction liner, these these solder sphere or this these projections with different resistance values are set, so that the resistance value of respectively should the conduction liner corresponding with it the respectively equivalent conductive path between this contact is approaching basically.
Chip of the present invention, wherein these these first conduction liner has the drops outward appearance.
Chip of the present invention, wherein these these second conduction liner has the drops outward appearance.
Another object of the present invention is to provide a kind of manufacturing method of chip, to solve foregoing problems.
According to a specific embodiment, manufacturing method of chip of the present invention is provided with a plurality of conduction liners near the corner of chip.Especially, these conduction liners are zonal and arc to be arranged, and big more the closer to the area of the conduction liner in corner.
Manufacturing method of chip of the present invention, further comprising the following step is a plurality of blocks with near the zonal and arc area dividing this corner, and big more the closer to the area of the block in this corner; And this these conduction is set one of in the liner on each block respectively, and the size in the zone of corresponding its setting of size of each conduction liner.
Manufacturing method of chip of the present invention, wherein this these conduction liner is with respect to this line symmetric arrays in center to this corner of arc belt-like zone roughly.
Manufacturing method of chip of the present invention, wherein the shape of this these conduction liner is selected from by rectangle, circle, ellipse, rhombus, trapezoidal and group that triangle is formed.
Another object of the present invention is to provide a kind of chip, it has the conduction liner design of the pressure damage that can reduce chip corner.
According to a specific embodiment, chip of the present invention comprises a plurality of conduction liners, and these conduction liners are arranged near the chip corner, and the setting that distributes along this corner in a predefined manner.Especially, its area of conduction liner the closer to the corner is big more.
Chip of the present invention, wherein this predetermined way is arc ribbon-like manner roughly.
Chip of the present invention, wherein this these conduction liner is with respect to this line symmetric arrays in center to this corner of arc belt-like zone roughly.
Chip of the present invention, wherein the shape of this these conduction liner is selected from by rectangle, circle, ellipse, rhombus, trapezoidal and group that triangle is formed.
Chip of the present invention, wherein these these conduction liner further comprises first conduction liner and at least two the second conduction liners, and wherein this these second conduction liner is respectively with respect to this first conduction liner setting.
Chip of the present invention, wherein this first conduction liner is positioned at this roughly on the line in center to this corner of arc belt-like zone, and this these second conduction liner is with respect to this line symmetric arrays.
Chip of the present invention, wherein each second conduction liner to the distance in this corner equates.
Chip of the present invention, wherein this first conduction liner is shaped as rectangle.
Chip of the present invention, wherein this these second conduction liner is shaped as right-angled triangle.
Can be further understood by following embodiment and accompanying drawing about the advantages and spirit of the present invention.
Description of drawings
Fig. 1 is the schematic diagram that the chip of prior art is connected with circuit board.
Fig. 2 A is the schematic diagram according to the chip of a specific embodiment of the present invention.
Fig. 2 B is the schematic diagram that the conduction liner of another specific embodiment of the present invention is arranged
Fig. 2 C is according to the first conduction liner of another specific embodiment of the present invention and the schematic diagram of the second conduction liner.
Fig. 2 D is the schematic appearance according to conduction liner of the present invention.
Fig. 2 E is the schematic appearance according to conduction liner of the present invention.
Fig. 2 F is the schematic appearance according to conduction liner of the present invention.
Fig. 3 is the flow chart of steps of manufacturing method of chip according to an embodiment of the invention.
Fig. 4 A is the schematic diagram according to the chip of a specific embodiment of the present invention.
Fig. 4 B is the flow chart of steps of manufacturing method of chip according to an embodiment of the invention.
Fig. 4 C is the schematic diagram according to the chip of another specific embodiment of the present invention.
Embodiment
Referring to Fig. 2 A, Fig. 2 A is the schematic diagram according to the chip 1 of a specific embodiment of the present invention.Shown in Fig. 2 A, chip 1 comprise have approximate drop-shaped a plurality of first the conduction liners 10 and a plurality of second the conduction liner 12.The first conduction liner 10 and the second conduction liner 12 are staggered on preset direction D respectively.Each first conduction liner 10 comprises the P1 of first and with respect to the second portion P2 of the P1 of first, and, the P1 of first along the length on the preset direction D greater than second portion P2 along the length on the preset direction D.Each second conduction liner 12 comprises third part P3 and with respect to the 4th part P4 of third part P3, and third part P3 along the length on the preset direction D greater than the 4th part P4 along the length on this preset direction D.Wherein, the second direction D2 from third part P3 to the four part P4 is opposite to the first direction D1 of second portion P2 with the P1 of first.In this specific embodiment, the line L of the second portion P2 of each first conduction liner 10 is parallel to preset direction D.The 4th part P4 of each second conduction liner 12 extends and surpasses line L to second direction D2 in 10 of two adjacent first conduction liners.Thus, but conduction liner dense arrangement.
Referring to Fig. 2 B, Fig. 2 B is the schematic diagram that the conduction liner of another specific embodiment of the present invention is arranged.Shown in Fig. 2 B, in this specific embodiment, each first conduction liner 10 ' has P1 ' of first and second portion P2 ' as aforementioned specific embodiment, and each second conduction liner 12 ' has third part P3 ' and the 4th part P4 ' as aforementioned specific embodiment.The P1 ' of first in the length on the preset direction D ' greater than the length of second portion P2 ' on predetermined direction D ', and third part P3 ' in the length on the preset direction D ' greater than the length of the 4th part P4 ' on preset direction D '.From the P1 ' of first toward second portion P2 ' is first direction D1 ', and from third part P3 ' toward the 4th part P4 ' be second direction D2 '.The line L ' of the second portion P2 ' of each first conduction liner 10 ' is parallel to preset direction D '.In this specific embodiment, the 4th part P4 ' of each second conduction liner 12 ' extends and surpasses line L ' to second direction D2 ' between the two adjacent first conduction liners 10 '.Thus, but conduction liner dense arrangement.
In addition, in a specific embodiment, chip of the present invention can conduct electricity liner by these and be connected in corresponding a plurality of contacts on the circuit board, and respectively conducts electricity liner and can be connected with corresponding contact by wiring.In actual applications, respectively to conduct electricity the resistance value of the equivalent conductive path between liner each contact corresponding with it approaching basically in order to make, visual distance of respectively conducting electricity between the corresponding contact with it of liner is far and near, adjust each contact and respectively conduct electricity the solder sphere (solder ball) on the liner or the size of projection (bump), adjusting its equivalent conductive path length, and then further basically and respectively conduct electricity the resistance value of the equivalent conductive path between the corresponding contact of liner with it.Especially, by solder sphere or size of lug difference, there is the difference of height the position of each wiring, therefore can avoid the situation of cross-talk (cross-talk) to take place.
Be noted that being provided with according to the distance between conduction liner and corresponding contact, area, other parameter and designer's the specific demand of liner of conducting electricity of solder sphere or projection is not limited to status.For example, according to the area difference of each conduction liner, each conducts electricity the material that solder sphere on the liner or projection can use different resistance values, respectively conducts electricity the resistance value of the equivalent conductive path between the corresponding contact with it of liner to further basically.
Referring to Fig. 2 C, Fig. 2 C is according to the first conduction liner 100 of another specific embodiment of the present invention and the schematic diagram of the second conduction liner 120.Shown in Fig. 2 C, this specific embodiment is that with last specific embodiment difference the area of the second conduction liner 120 is less than the first conduction liner 100, in addition, as above-mentioned specific embodiment, first the conduction liner 100 the P1 of first " at predetermined direction D " and on length greater than second portion P2 " at preset direction D " and on length, second the conduction liner third part P3 " at predetermined direction D " and on length greater than the 4th part P4 " at preset direction D " and on length.Therefore, just have living space between each adjacent two first conduction liner 100 and hold the second conduction liner 120, make the arrangement of respectively conducting electricity between the liner can be more intensive.
And referring to Fig. 2 D to Fig. 2 F, Fig. 2 D to Fig. 2 F is the schematic appearance according to conduction liner of the present invention.Note that the conduction liner that is illustrated all comprises the aforesaid first conduction liner 10 and the second conduction liner 12 in Fig. 2 D to Fig. 2 F.Shown in Fig. 2 D to Fig. 2 F, the conduction liner on the chip of the present invention except the drops outward appearance shown in the front, also visual demand and having as circular (shown in Fig. 2 D), trapezoidal (shown in Fig. 2 E) and hexagon outward appearances such as (shown in Fig. 2 F).In addition, these conduct electricity the also visual demands of liner and have the outward appearance of Else Rule or irregular polygon.
Referring to Fig. 3, Fig. 3 is the flow chart of steps of manufacturing method of chip according to an embodiment of the invention.As shown in Figure 3, manufacturing method of chip of the present invention, comprise following steps: at first, among the step S10, on chip, a plurality of drops first conduction liners that are are set along preset direction, each first conduction liner comprises first and with respect to the second portion of first, and, each first along the length on the preset direction greater than each second portion along the length on the preset direction; Then, among the step S12, on chip, be provided with and the staggered a plurality of drop-shaped second conduction liners that are of the first conduction liner, each second conduction liner comprises third part and with respect to the 4th part of third part, and, each third part along the length on the preset direction greater than each the 4th part along the length on the preset direction.Wherein, from the tetrameric second direction of third part to the with the first direction to second portion is opposite from first.
In the present embodiment, chip is connected in the corresponding a plurality of contacts of circuit board by these conduction liners, and each conduction liner is connected with corresponding contact by wiring.In order to make the total conductive path that respectively conducts electricity between liner each contact corresponding approaching basically with it, according on each the first conduction liner and the second conduction liner with circuit board on the distance of corresponding a plurality of contacts far and near, the solder sphere or the projection of different size are set on contact and conduction liner, respectively conduct electricity the resistance value of the equivalent conductive path between the corresponding contact of liner to adjust, to make it approaching basically with it.
It should be noted that the first conduction liner of the various embodiments described above and the external form of the second conduction liner are drops.Yet in actual applications, the first conduction liner and the second conduction liner can be other external form, and a first that only needs to satisfy the first conduction liner gets final product greater than tetrameric principle greater than the third part of the second portion and the second conduction liner.For example, the external form of the first conduction liner of the present invention and the second conduction liner can be, but is not subject to rhombus, trapezoidal, triangle, ellipse, or Else Rule or irregular polygon.
Referring to Fig. 4 A, Fig. 4 A is the schematic diagram according to the chip 2 of a specific embodiment of the present invention.Shown in Fig. 4 A, chip 2 comprises a plurality of conduction liners 20, is arranged near the corner of chip, and distributing along the corner in a predefined manner is provided with, and big more the closer to its area of conduction liner in corner.In addition, shown in Fig. 4 A, chip 2 of the present invention can further comprise zonal and arc zone 22, and zonal and arc zone 22 is divided into a plurality of blocks 220 again, and big more the closer to the area of the block 220 in corner.Conduction liner 20 is arranged at respectively on the block 220, and each conducts electricity the size of block 220 of corresponding its setting of size of liner 20.Thus, can reduce in the encapsulation process and may the pressure that chip causes be damaged.
In this specific embodiment, the both wings in zonal and arc zone 22 are with respect to the line in center to the corner in zonal and arc zone 22 and symmetry.Similarly, conduction liner 20 also is symmetric arrays with respect to the line in center to the corner in zonal and arc zone 22.In addition, the conductive liner plate shape of this specific embodiment is circular, but in practical application, and the conductive liner plate shape can the demand of looking be, but is not subject to rectangle, circle, ellipse, rhombus, trapezoidal, triangle, or Else Rule or irregular polygon.
Referring to Fig. 4 B, Fig. 4 B is the flow chart of steps of manufacturing method of chip according to an embodiment of the invention.Shown in Fig. 4 B, manufacturing method of chip comprises the following step: at first, among the step S20, the zonal and arc zone is set near the corner of chip, and is a plurality of blocks the zonal and arc area dividing, and wherein, big more the closer to the area of the block in corner; Then, among the step S22, the conduction liner is set respectively on each block, and respectively conducts electricity the size in zone of corresponding its setting of size of liner.
In the present embodiment, the both wings in zonal and arc zone are with respect to the line in center to the corner in zonal and arc zone and symmetry.Similarly, the conduction liner that is arranged on each block in zonal and arc zone also is symmetric arrays with respect to the line in center to the corner in zonal and arc zone.In addition, the conductive liner plate shape can the demand of looking be, but is not subject to rectangle, circle, ellipse, rhombus, trapezoidal, triangle, or Else Rule or irregular polygon.
Referring to Fig. 4 C, Fig. 4 C is the schematic diagram according to the chip 3 of another specific embodiment of the present invention.Shown in Fig. 4 C, chip 3 comprises the first conduction liner 30 and at least two second conduction liners 32.The first conduction liner 30 is positioned on the line in center to corner in zonal and arc zone, and the second conduction liner 32 is symmetric arrays with respect to zonal and arc regional center to the line in corner, and each second conduction liner 32 to the distance in corner equates.
In this specific embodiment, the first conduction liner 30 is a rectangle, and second 32 of the liners of conduction are right-angled triangle.But in actual applications, the external form of the first conduction liner 30 and the second conduction liner 32 is not limited to rectangle or right-angled triangle, need only meet the closer to the big more principle of its area of conduction liner in corner to get final product.Thus, can reduce in the encapsulation process and may the pressure that chip causes be damaged.
With respect to prior art, chip of the present invention and manufacture method thereof can make the conduction liner present the arrangement of comparatively dense on chip, the not complicated day by day chip design of reason and the size of chip is strengthened, and then save cost.In addition, the conduction liner in corner design can reduction chip improves the yield of chip because of the pressure damage that encapsulation process produces.
By the detailed description of above preferred specific embodiment, hope can be known description feature of the present invention and spirit more, and is not to come category of the present invention is limited with above-mentioned disclosed preferred specific embodiment.On the contrary, its objective is that hope can be encompassed in the interior various changes and the equivalence arrangement of scope of patent protection of institute of the present invention desire application.Therefore, the category of the scope of patent protection that the present invention applied for should be done the broadest explanation according to above-mentioned explanation, contains the arrangement of all possible change and equivalence to cause it.
The primary clustering symbol description
A1: conduction liner A2: conduction liner
B1: circuit board C1: chip
1,2,3: chip 20: the conduction liner
10,10 ', 100,30: the first conduction liners
12,12 ', 120,32: the second conduction liners
D, D ', D ": predetermined direction D1, D1 ': first direction
D2, D2 ': second direction P1, P1 ', P1 ": first
P2, P2 ', P2 ": second portion P3, P3 ', P3 ": third part
P4, P4 ', P4 ": the 4th part L, L ': line
S10, S12, S20, S22: steps flow chart.
Claims (10)
1. chip comprises:
A plurality of first conduction liners, be arranged on the described chip along preset direction, each first conduction liner comprises first and with respect to the second portion of described first, and each described first along the length on the described preset direction greater than each described second portion along the length on the described preset direction; And
A plurality of second conduction liners, be arranged on the described chip along described preset direction, and described these first conduction liners are staggered, each second conduction liner comprises third part and with respect to the 4th part of described third part, and each described third part along the length on the described preset direction greater than each described the 4th part along the length on the described preset direction;
Wherein opposite to the first direction of described second portion to described tetrameric second direction with described first from described third part, and each described the 4th part extends beyond the line of described these second portions to described second direction.
2. chip according to claim 1, wherein said chip is connected in corresponding a plurality of contacts of circuit board by described these conduction liners, and each conduction liner is connected with corresponding described contact by wiring.
3. chip according to claim 2, wherein according on each the first conduction liner and the second conduction liner with described circuit board on the distance of described corresponding a plurality of contacts far and near, adjustment is arranged at the described solder sphere of respectively conducting electricity on liner and each contact or the size of described projection, so that the resistance value of the equivalent conductive path between each described conduction liner each described contact corresponding with it is approaching basically.
4. chip according to claim 2, wherein according to each first the conduction liner and second the conduction liner area, on described these conduction liners, described these solder sphere or described these projections with different resistance values are set, so that the resistance value of the equivalent conductive path between each described conduction liner each described contact corresponding with it is approaching basically.
5. chip comprises:
A plurality of conduction liners are arranged near the corner of described chip, and distributing along described corner in a predefined manner is provided with, and big more the closer to the area of the conduction liner in described corner.
6. chip according to claim 5, wherein said predetermined way is arc ribbon-like manner roughly.
7. chip according to claim 6, wherein said these conduction liners are with respect to the line symmetric arrays in center to the described corner of described roughly arc belt-like zone.
8. chip according to claim 6, wherein said these conduction liners further comprise:
The first conduction liner and at least two second conduction liners, wherein said these second conduction liners are respectively with respect to the described first conduction liner setting.
9. chip according to claim 8, the center that the wherein said first conduction liner is positioned at described roughly arc belt-like zone are to the line in described corner, and described these second conduction liners are with respect to described line symmetric arrays.
10. chip according to claim 8, wherein each second conduction liner to the distance in described corner equates.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200710165130 CN100585842C (en) | 2007-10-29 | 2007-10-29 | Chip and its manufacture method |
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|---|---|---|---|
| CN 200710165130 CN100585842C (en) | 2007-10-29 | 2007-10-29 | Chip and its manufacture method |
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| CN 200910206626 Division CN101667565A (en) | 2007-10-29 | 2007-10-29 | Chip and manufacturing method thereof |
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| CN101425490A true CN101425490A (en) | 2009-05-06 |
| CN100585842C CN100585842C (en) | 2010-01-27 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109686765A (en) * | 2018-12-24 | 2019-04-26 | 武汉华星光电半导体显示技术有限公司 | Chip structure and display device |
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| JPH09232465A (en) * | 1996-02-27 | 1997-09-05 | Fuji Kiko Denshi Kk | Printed wiring board for mounting semiconductor |
| JP4439090B2 (en) * | 2000-07-26 | 2010-03-24 | 日本テキサス・インスツルメンツ株式会社 | Semiconductor device and manufacturing method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN109686765A (en) * | 2018-12-24 | 2019-04-26 | 武汉华星光电半导体显示技术有限公司 | Chip structure and display device |
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| CN100585842C (en) | 2010-01-27 |
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