CN101421794A - Reducing the impact of program disturb during read - Google Patents

Abstract

The unintentional programming of an unselected (or inhibited) non-volatile storage element during a program operation that intends to program another non-volatile storage element is referred to as 'program disturb.' A system is proposed for programming and/or reading non-volatile storage that reduces the effect of program disturb. In one embodiment, different verify levels are used for a particular word line (or other grouping of storage elements) during a programming process. In another embodiment, different compare levels are used for a particular word (or other grouping of storage elements) during a read process.

Description

Reduce the influence that the programming during reading is disturbed

Technical field

The present invention relates to a kind of nonvolatile memory.

Background technology

Semiconductor memory system has become and has been used for various electronic installations more at large.For instance, nonvolatile semiconductor memory is used for cellular phone, digital camera, personal digital assistant, mobile computing device, non-moving calculation element and other device.Electrically Erasable Read Only Memory (EEPROM) and flash memory are arranged in the middle of the most general nonvolatile semiconductor memory.

The EEPROM of many types and flash memory utilization are positioned channel region top in the Semiconductor substrate and the floating grid that insulate with described channel region.Described floating grid is positioned between source area and the drain region.The control grid is provided in to insulate on the floating grid and with floating grid.Transistorized threshold voltage is by the quantity of electric charge control that is retained on the floating grid.That is, connecting transistor to allow before conduction between its source electrode and the drain electrode and must control by the charge level on the floating grid to the minimum of controlling the voltage that grid applies.

An example of flash memory system uses enable nand gate, and described structure comprises that layout is clipped in two a plurality of serial transistors of selecting between the grid.Serial transistor and selection grid are known as the NAND string.Fig. 1 is for showing the vertical view of a NAND string.Fig. 2 is its equivalent electrical circuit.That comprise series connection at Fig. 1 and NAND depicted in figure 2 string and be clipped in first (or four transistors 100,102,104 and 106 between grid 120 and second (or source electrode) the selection grid 122 are selected in drain electrode.Select grid 120 NAND to be series-connected to bit line via bit line contact 126.Select grid 122 that NAND is series-connected to source electrode line 128.Control selection grid 120 by apply appropriate voltage to selection wire SGD.Control selection grid 122 by apply appropriate voltage to selection wire SGS.Transistor 100,102,104 and 106 each have control grid and floating grid.For instance, transistor 100 has control grid 100CG and floating grid 100FG.Transistor 102 comprises control grid 102CG and floating grid 102FG.Transistor 104 comprises control grid 104CG and floating grid 104FG.Transistor 106 comprises control grid 106CG and floating grid 106FG.Control grid 100CG is connected to word line WL3, and control grid 102CG is connected to word line WL2, and control grid 104CG is connected to word line WL1, and control grid 106CG is connected to word line WL0.

Show four memory cells in the NAND string although it should be noted that Fig. 1 and Fig. 2, only four transistorized uses are provided as example.NAND string can have and is less than four memory cells or more than four memory cells.For instance, some NAND strings will comprise 8 memory cells, 16 memory cells, 32 memory cells, 64 memory cells etc.Argumentation herein is not limited to any certain number destination memory location in the NAND string.

Use the typical architecture of the flash memory system of enable nand gate will comprise several NAND strings.For instance, Fig. 3 shows three NAND strings 202,204 and 206 of the memory array with much more NAND string.Each of the NAND string of Fig. 3 comprises that two are selected transistor (also being called grid) and four memory cells.For instance, NAND string 202 comprises selects transistor 220 and 230, and memory cell 222,224,226 and 228.NAND string 204 comprises selects transistor 240 and 250, and memory cell 242,244,246 and 248.Each NAND ganged up its drain selection grid (for example, selecting transistor 230 and selection transistor 250) and was connected to source electrode line.Selection wire SGS is in order to control drain selection grid (for example, 230 and 250).

Each NAND string is connected to respective bit line by the selection transistor 220,240 that is subjected to selection wire SGD control etc.Each bit line and comprise the row of described memory cell array via the corresponding NAND string that bit line contact is connected to described bit line.Bit line is shared by a plurality of NAND strings.Usually, bit line carries out and is connected to one or more sensor amplifiers (sense amplifier) with the direction perpendicular to word line on the top of NAND string.

Word line (WL3, WL2, WL1 and WL0) comprises the row of described array.Word line WL3 is connected to the control grid of memory cell 222 and memory cell 242.Word line WL2 is connected to the control grid of memory cell 224, memory cell 244 and memory cell 252.Word line WL1 is connected to the control grid of memory cell 226 and memory cell 246.Word line WL0 is connected to the control grid of memory cell 228 and memory cell 248.

Each memory cell can be stored data (analog or digital).Numerical data when (being called the binary storage device unit) when a position of storage is divided into two scopes that logical data " 1 " reaches " 0 " that are assigned with the scope of the possible threshold voltage of memory cell.In an example of NAND type flash memory, after wiping memory cell, described voltage threshold is negative, and is defined as logical one.After programming, described threshold voltage is positive and is defined as logical zero.When threshold voltage for negative and by applying 0 volt to the control grid when attempting reading, memory cell will be connected to indicate positive stored logic " 1 ".When threshold voltage for positive and by applying 0 volt to the control grid when attempting read operation, memory cell will be disconnected, this indicates stored logic " 0 ".

Memory cell also can be stored the information (being called the multistate memory unit) of a plurality of level.Under the situation of the data of storing a plurality of level, the scope of possibility threshold voltage is divided into the data of the level of described number.For instance, if store the information of four level, then existence is assigned as four threshold voltage ranges that data value " 11 ", " 10 ", " 01 " reach " 00 ".In an example of nand type memory, the threshold voltage after erase operation is for negative and be defined as " 11 ".Positive threshold voltage is used for the state that " 10 ", " 01 " reach " 00 ".

The related example of NAND type flash memory and operation thereof is provided in following United States Patent (USP)/patent application case, and all described application cases are incorporated herein by reference: United States Patent (USP) the 5th, 570, No. 315; United States Patent (USP) the 5th, 774, No. 397; United States Patent (USP) the 6th, 046, No. 935; United States Patent (USP) the 6th, 456, No. 528 and U.S. Patent Publication case US2003/0002348 number.Argumentation herein also can be applicable to the flash memory of other type and the nonvolatile memory of other type except that can be applicable to nand type memory.

When the programming flash memory cells, apply program voltage and bit line ground connection to the control grid.Owing to the raceway groove of flash memory cells and the voltage difference between the floating grid, be injected in the floating grid from the electronics of the channel region of floating grid below.When electronics was built up in floating grid, floating grid became threshold voltage electronegative and memory cell and rises.For the control grid to decent programmed cells applies program voltage, described program voltage is put on the suitable word line.As indicated above, described word line is also connected to a memory cell in each of other NAND string of utilizing same word line.For instance, when the memory cell 224 of programming Fig. 3, program voltage also will be applied to the control grid of memory cell 244, because two memory cells are shared same word line.A unit on needing programmed word line and need not to programme when being connected to other unit of same word line for example, when needs program memory cells 224 and when not needing program memory cells 244, can go wrong.Because apply program voltage, so the unselected memory unit on the same word line (not programmed memory cell) can be programmed unintentionally to all memory cells that are connected to word line.For instance, memory cell 244 is adjacent to memory cell 224.When program memory cells 224, exist memory cell 244 can by non-wittingly the programming problem.The non-programming intentionally of the unselected memory unit on selected word line is known as " programming is disturbed ".

Some technology can be with disturbing to prevent to programme.In the method for a kind of being called " from supercharging (self boosting) ", make selected NAND string and the isolation of corresponding bit line electricity, and during programming, apply by voltage (passvoltage) (for example, 7 to 10 volts, but be not limited thereto scope) to selected word line not.Selected word line is not coupled to the channel region of not selected NAND string, causes voltage (for example, 6 to 10 volts) to be present in the raceway groove of not selected NAND string, disturbs thereby reduce programming.Cause the voltage of rising to be present in the raceway groove from supercharging, this reduces the voltage difference of crossing over tunneling oxide and therefore reduces programming and disturb.Should note, because the channel voltage that raises is on deciding and also decide on the state of memory cell by the value of voltage, so the channel voltage that raises can change greatly, when wherein all memory cells in NAND goes here and there are in erase status, supercharging the most effective (the highest channel voltage).

Fig. 4 and Fig. 5 describe to be programmed and to use the NAND string of forbidding from boosting method.The NAND string that Fig. 4 describes to be programmed.The NAND string of Fig. 4 comprises eight memory cells 304,306,308,310,312,314,316 and 318.Each of described eight memory cells comprises floating grid (FG) and control grid (CG).It between each of floating grid source/drain regions 330.In some embodiments, there are P type substrate (for example, silicon), the N trap in substrate and the P trap (all described elements not being described so that graphic easier understanding) in the N trap.It should be noted that the P trap can contain so-called raceway groove and implant, it typically is and determine or help to determine that the threshold voltage of memory cell and the P type of other feature implant.Source/drain regions 330 is for being formed at the N+ diffusion region in the P trap.

Drain side is selected the end place of grid 324 at the NAND string.Drain electrode selects grid 324 via bit line contact 334 NAND to be series-connected to corresponding bit line.Drain selection grid 322 is at the other end place of NAND string.Drain selection grid 322 is series-connected to common source line 332 with NAND.During programming, the selected memory cell (for example, memory cell 312) that is used to programme receives program voltage Vpgm on its associated word line.Program voltage Vpgm can change between 12 volts to 24 volts usually.In one embodiment, program voltage signal is a set of pulses, and the value of pulse increases with each new pulse.Apply about 8 volts voltage Vpass that passes through to the control grid of the not selected memory cell that is used to programme.Drain selection grid 322 is in state of insulation, thereby locates to receive 0 volt at its grid (G).Apply low-voltage to common source line 332.Described low-voltage can be 0 volt.Yet source voltage also can be higher than 0 volt a little to provide source side to select the isolation characteristic preferably of grid.Select grid 324 to apply the voltage Vsgd in the scope of supply voltage Vdd (for example, 2.5 volts) usually to drain side.Apply 0 volt to enable the programming of word-select memory unit 312 via corresponding bit line to bit line contact 334.Raceway groove 340 is in or near 0 volt.Because the voltage difference between the floating grid of raceway groove and memory cell 314 is reined in Nordheim (Fowler-Nordheim) tunnelling by good fortune, electron tunneling is crossed gate oxide (also being called tunneling oxide usually) and is entered in the floating grid.

The NAND string that the NAND string of Fig. 5 is described to be under an embargo and programmed.Described NAND string comprises eight memory cells 350,352,354,356,358,360,362 and 364.Described NAND string also comprises via bit line contact 374 selects grid 366 with the drain electrode that NAND is series-connected to corresponding bit line, and NAND is series-connected to the drain selection grid 368 of common source line 332.Source/drain regions 370 is in that floating grid piles up between each.The NAND of Fig. 5 string has to drain electrode to be selected Vsgd that the grid of grid 366 applies, reaches at 0 volt of common source line 332 places (or higher voltage) a little to 0 volt of selecting the grid of grid 368 to apply of source side.Bit line contact 374 receives supply voltage Vdd so that the programming of forbidden storage device unit 358 via corresponding bit line.

When applying Vdd, drain electrode selects transistor 366 will be in conducted state at first; Therefore, the channel region below NAND string will be reached high potential (be higher than 0 volt and be generally equal to or Vdd no better than) by the part charging.This charging is commonly referred to as precharge.When channel potential reached Vdd or by Vsgd-Vt given than electronegative potential the time, precharge will stop automatically, wherein Vt equals to drain and selects the threshold voltage of grid 366.Usually, between precharge phase, with Vsgd-Vt〉mode of Vdd selects Vsgd so that the channel region below the NAND string can be precharged to Vdd.After raceway groove has reached described current potential, make the selection gridistor be non-conduction or become non-conduction by Vsgd being reduced to the value that is similar to Vdd (for example, 2.5 volts).Subsequently, voltage Vpass and Vpgm are elevated to its corresponding end value (may not at the same time) from 0 volt of slope, and because drain side selects gridistor 366 to be in non-conduction condition, so channel potential will begin owing to the capacitive coupling between word line and the channel region to rise.This phenomenon is called from supercharging.Make raceway groove 380 more or less be pressurized to boosted voltage equably as can be seen from Fig. 5.Because reduced the floating grid of memory cell 358 and the voltage difference between the raceway groove 380, so programming is forbidden.Can be about the more information (comprising) of programming NAND flash memory at Lu's United States Patent (USP) the 6th of people such as (Lutze) now from supercharging technology, 859, No. 397 title finds for " source side that is used for nonvolatile memory is from supercharging technology (Source Side Self Boosting Technique forNon-Volatile Memory) ", and the full text of described application case is incorporated herein by reference.

In order to another trial that solves the programming interference is that erase area is from supercharging (" EASB ").EASB attempts to make before the channel isolation through the raceway groove and the forbidden unit of programming unit.In the EASB method, the channel region that selected NAND is gone here and there is divided into two zones.Zone at the source side place of the selected word line that can contain many programmings (or erase unit) memory cell, and the unit still is in erase status or is not in the zone at drain side place of the selected word line of final programming state at least as yet therein.Two zones are separated by the word line that is biased into low-voltage (being generally 0 volt).Because this separation can make two zones be pressurized to different potentials.Under nearly all situation, will make zone at the drain side place of selected word line than being pressurized to more noble potential in the zone at source side place.Because high pressure-charging zone is for having the zone of erase unit, so this boosting method is also called erase area from supercharging (EASB).

Disturb although above boosting method has reduced programming, it does not eliminate described problem as yet.A kind of effect can occur in abutting connection with the memory cell (for example, the drain selection grid 368 of memory cell 350 adjacent maps 5) of drain selection grid is gate-induced drain leakage (GIDL), and it is also called band to the band tunnelling.When the raceway groove below the NAND string was under an embargo programming (being pressurized to high voltage), GIDL caused at drain selection grid place generation electronics.Subsequently, in electric field, quicken the electronics that produced tyrannical towards the floating grid of the memory cell of adjacency drain selection grid.Some electronics can obtain tunneling oxide or the floating grid self of enough energy with injection floating grid below, and therefore revises the threshold voltage of corresponding stored device unit.

Fig. 6 is illustrated under the situation that drain electrode is amplified, the part of the part of the NAND of Fig. 5 string and the raceway groove of memory cell 350.Owing to the supercharging of (for example, when other NAND string just is being programmed) NAND string during the programming quiescing, high voltage is present in the channel region (referring to supercharging raceway groove 380) of supercharging NAND string.This high voltage also is present in drain selection grid 368 (its usually at the 0V place through bias voltage) and locates in abutting connection with the tie region (junction area) between the memory cell 350 of drain selection grid 368.This bias voltage situation can produce GIDL, and it can cause the formation of electron hole pair.Described hole will enter P well area 384.Electronics will move to boosted channel regions territory 380.Usually, there is transverse electric field, described transverse electric field is present in the drain selection grid and selects in abutting connection with source side in the tie region between the memory cell of grid, because the part of described knot (drain/source) is depleted owing to voltage difference big between the channel region of memory cell below and the channel region of selecting below the grid.Electronics can be in electric field through quicken and can obtain enough energy with inject in abutting connection with source side select grid memory cell tunneling oxide or can even arrive the floating grid of described memory cell.Under two kinds of situations, owing to inject the existence of electronics, the threshold voltage of corresponding stored device unit will change, thereby suffer the risk of error when the memory cell that reads in abutting connection with the drain selection grid.

Therefore, need a kind of new mechanism to reduce the influence that programming is disturbed.

Summary of the invention

Propose a kind ofly to be used to programme and/or the system of reading non-volatile memory element, described system reduces the programming interference effect.In one group of embodiment, during programming process, use different checking level at particular word line (or other grouping of memory element).For the one group of example that uses the multimode device, the target level of a programming state, two programming states, another sub programming state of organizing or all programming states can be different.In certain embodiments, can use difference (, two, another sub group or all) target level with the different page datas that particular word line (or other grouping of memory element) is associated.In other embodiments, can use difference (, two, another sub group or all) target level with the different memory elements that particular word line (or other grouping of memory element) is associated.In one embodiment, come the word line of selective reception different target level with respect to the position of pressurizing area based on word line.

Embodiment comprises and uses programme group's non-volatile memory device and use the particular group target level particular group non-volatile memory device of programming of group's target level, so that the threshold distribution of described particular group non-volatile memory device is in the corresponding threshold distribution of described group non-volatile memory device after finishing programming process.In the described particular group target level at least one is lower than the corresponding target level of described group target level.

Embodiment comprises and uses programme group's non-volatile memory device and use the particular group target level particular group non-volatile memory device of programming of group's target level, so that the threshold voltage distribution of described particular group non-volatile memory device is through being offset to give prominence to (comprising not outstanding) from the corresponding threshold voltage distribution of described group non-volatile memory device at least lessly after finishing programming process, at least one in the described particular group target level is lower than the corresponding target level of described group target level.

Embodiment comprises and uses programme one group of one or more non-volatile memory device and use a particular group target level specific non-volatile memory device of programming of group's target level.In the described particular group target level at least one is lower than the corresponding target level of described group target level.Described specific non-volatile memory device is adjacent to the drain selection grid.

Embodiment comprises and uses programme first group of one or more non-volatile memory device and use second group of target level, second group of one or more non-volatile memory device of programming after described first group of one or more non-volatile memory device of programming of first group of target level.Described first group of one or more non-volatile memory device of at first programming.During a sequence programming operation, described first group of one or more non-volatile memory device are connected to first word line and described second group of one or more non-volatile memory device are connected to one group of word line by programming after first word line.Described second group of target level is different from described first group of target level.

Propose a kind ofly to be used to programme and/or the system of reading non-volatile memory storage, described system reduces the programming interference effect.In one group of embodiment, during reading process, use difference to read fiducial value at particular word line (or other grouping of memory element).During programming process, select to receive the different word lines that read fiducial value with respect to the position of the position of pressurizing area based on word line.

Embodiment comprises and uses first group to read fiducial value and read first group of non-volatile memory device and use second group to read fiducial value and read second group of one or more non-volatile memory device.Described first group of non-volatile memory device is connected to first control line.Described second group of non-volatile memory device is connected to the second group of control line that is different from described first control line.First group is read in the fiducial value at least one and is different from second group of corresponding comparative level that reads fiducial value.In an example an of embodiment (but being not all embodiments), first control line is in abutting connection with the drain selection control line.

Embodiment comprises and uses programme first group of non-volatile memory device and use described identical first group of target level second group of one or more non-volatile memory device of programming of first group of target level.Described first group of non-volatile memory device is associated with first control line.First control line is adjacent to second control line.Described process also is included on second control line of non-volatile memory device that programming signal is provided on first control line and is connected to second control line at needs the signal that disconnects in response to described signal is provided.Described second group of one or more non-volatile memory device are associated with one group of control line.First control line and second control line be not in described group of control line.Use first group to read fiducial value and read first group of one or more non-volatile memory device.Use second group to read fiducial value and read second group of one or more non-volatile memory device.First group is read in the fiducial value at least one and is different from second group of corresponding comparative level that reads fiducial value.

Described herein the whole bag of tricks can be carried out by various devices.An example that is fit to equipment comprises non-volatile memory device and the management circuit of communicating by letter with non-volatile memory device.Non-volatile memory device comprises first group of non-volatile memory device and second group of non-volatile memory device.Described management circuit is carried out described the whole bag of tricks about first group of non-volatile memory device and second group of non-volatile memory device herein.In one embodiment, management circuit comprises any one of controller, state machine, command circuit, control circuit and demoder or makes up.In other embodiments, management circuit also can comprise other element that is suitable for particular.

Description of drawings

Fig. 1 is the vertical view of NAND string.

Fig. 2 is the equivalent circuit diagram of described NAND string.

Fig. 3 is a synoptic diagram of describing three NAND strings.

Fig. 4 shows NAND string by programming.

Fig. 5 shows the NAND string that use is forbidden from boosting method.

Fig. 6 describes the part of NAND string.

Fig. 7 is the block diagram of an example of accumulator system.

Fig. 8 illustrates the example of the tissue of memory array.

Fig. 9 describes one group of threshold voltage distribution.

Figure 10 A, Figure 10 B and Figure 10 C describe threshold voltage distribution.

Figure 11 is the process flow diagram of an embodiment of the process of description programming and reading non-volatile storage.

Figure 12 A and Figure 12 B describe threshold voltage distribution.

Figure 13 is used to programme and the process flow diagram of an embodiment of the process of reading non-volatile storage for describing.

Figure 14 is used to programme and the process flow diagram of an embodiment of the process of reading non-volatile storage for describing.

Figure 15 is used to programme and the process flow diagram of an embodiment of the process of reading non-volatile storage for describing.

Figure 16 is the process flow diagram of an embodiment of description programming operation.

Figure 17 is a signal graph of describing an embodiment of read operation.

Figure 18 is used to programme and the process flow diagram of an embodiment of the process of reading non-volatile storage for describing.

Figure 19 describes one group of threshold voltage distribution.

Figure 20 is used to programme and the process flow diagram of an embodiment of the process of reading non-volatile storage for describing.

Embodiment

Fig. 7 is the block diagram of an embodiment of flash memory system, and described flash memory system can be in order to implement described one or more embodiment herein.Also can use other system and embodiment.Memory cell array 502 is by arrange control circuit 504, line control circuit 506, p- trap control circuit 508 and 510 controls of c-source electrode control circuit.The bit line that arrange control circuit 504 is connected to memory cell array 502 with the potential level that is used for reading the data that are stored in memory cell, is used for during programming operation, determining the state of memory cell and is used to control bit line to promote or to forbid programming and wipe.Line control circuit 506 is connected to word line to select one in the described word line, to apply and read voltage, apply program voltage and apply erasing voltage in conjunction with the bit line potential levels by arrange control circuit 504 control.In one embodiment, row control 306 and row control 304 comprise that demoder is to select suitable word line and bit line.C-source electrode control circuit 510 is operatively connected to the common source line (being labeled as " c-source electrode " in Fig. 8) of memory cell.P-trap control circuit 508 control p-trap voltages.

Being stored in data in the memory cell is read by arrange control circuit 504 and outputs to exterior I/O line via data input/output (i/o) buffer 512.The programming data that is stored in the memory cell is input to data input/output (i/o) buffer 512 via exterior I/O line, and is sent to arrange control circuit 504.Exterior I/O line is connected to controller 518.

The order data that is used to control flash memory device is input to controller 518.Order data notice flash memory request is what operation.Input command is sent to state machine 516, and described state machine 516 is the part of control circuit 515.State machine 516 control arrange control circuits 504, line control circuit 506, c-source electrode control 510, p-trap control circuit 508 and data input/output (i/o) buffer 512.State machine 516 is the status data of exportable flash memory also, for example ready/and busy (READY/BUSY) or by/failure (PASS/FAIL).

Controller 518 is connected to host computer system (for example personal computer, digital camera or personal digital assistant etc.) or can be connected with host computer system.The main-machine communication of itself and initial order (for example with data storage to memory array 502 or from memory array 502 reading of data), and provide or receive described data.Controller 518 is can be by command circuit 514 explanations and the command signal of carrying out with described command conversion, and command circuit 514 is the part of control circuit 515.Command circuit 514 is communicated by letter with state machine 516.Controller 518 contains memory buffer usually, and it is used for user data is written to memory array or reads user data from memory array.

An exemplary embodimentsan example memory system comprises an integrated circuit (IC) chip that comprises controller 518, and each contains memory array and one or more integrated circuit (IC) chip of the control that is associated, I/O and state machine circuit.The memory array of system and controller circuitry can be integrated on one or more integrated circuit (IC) chip.Accumulator system can maybe can be included in the storage card (or other encapsulation) that inserts removedly in the host computer system through embedding the part as host computer system.Described card can comprise whole accumulator system (for example, comprising controller) or only comprise and have associated peripheral circuits the memory array of (having the controller or the control function that embed in the main frame).Therefore, controller can embed in the main frame or be included in the removable accumulator system.

In some embodiments, some assemblies of Fig. 7 capable of being combined.In various designs, except that memory cell array 502, one or more (alone or in combination) in the assembly of Fig. 7 can be considered to management circuit.For instance, management circuit can comprise any one among control circuit 515, command circuit 514, state machine 516, arrange control circuit 504, line control circuit 506, p-trap control circuit 508, c-source electrode control circuit 510 and the data I/O 512 or make up.

Referring to Fig. 8, the demonstrative structure of memory cell array 502 is described.As an example, the NAND quickflashing EEPROM that is divided into 1,024 piece is described.Can wipe the data that are stored in each piece simultaneously.In one embodiment, described least unit for the memory cell that can be wiped simultaneously.In described example, in each piece, there are 8,512 row.Each piece is divided into the many pages or leaves that can be unit of program usually.Other unit that is used for data programmed is also for possible.In one embodiment, each page or leaf can the section of being divided into, and the described section unit that can contain the minimal amount that is written into simultaneously as basic programming operation.The above data of one page or one page are stored in the row of memory cells usually.

Have 8,512 row in each piece of example in Fig. 8, described row are divided into even bitlines (BLe) and odd bit lines (BLo).In the odd/even bit-line architecture, along common word line and the memory cell that is connected to odd bit lines the time through programming, and along common word line and the memory cell that is connected to even bitlines another time through programming.Fig. 8 shows that four memory cells that are connected in series are to form the NAND string.Be included in each NAND string although show four unit, can use greater or less than four (for example, 16,32 or another number) unit.A terminal of NAND string selects grid (be connected to and select grid drain electrode line SGD) to be connected to corresponding bit line via drain electrode, and another terminal is connected to the c-source electrode via drain selection grid (be connected to and select gate source polar curve SGS).

In other embodiments, bit line is not divided into odd number and even bitlines.Described framework is commonly referred to as full bit-line architecture.In full bit-line architecture, can read and programming operation during select all bit lines of piece simultaneously.Along common word line and be connected to any bit line memory cell can through simultaneously the programming.

In another embodiment, bit line is divided into the plane.For instance, can there be left plane (4256 the most left bit lines) and right plane (4256 the rightest bit lines).Can be programmed separately in each plane or can be programmed simultaneously in two planes.In certain embodiments, can there be two above planes.Also can use other layout.

An embodiment who uses the odd/even bit-line architecture read and programming operation during, select 4,256 memory cells simultaneously.Selected memory cell has same word line (for example, WL2-i) and the bit line of identical type (for example, even bitlines).Therefore, can read simultaneously or the programme data of 532 bytes.The data of described 532 bytes through reading simultaneously or programming form logical page (LPAGE).Therefore, in described example, can store at least eight pages for one.When two data bit of each memory cell stores (for example, the multimode unit), 16 pages of storages.Also can use other big or small piece and page or leaf.In addition, the framework except that the framework of Fig. 7 and Fig. 8 also can be in order to implement embodiment.

Read and verification operation in, the selection grid of selected piece (for example is elevated to one or more not selected word lines of selecting voltages and will selecting piece, WL0, WL1 and WL3) be elevated to read and pass through grid so that transistor is operating as by voltage (for example, 4.5 volts).The selected word line of selected piece (for example, WL2) be connected to reference voltage, the level of described reference voltage be exclusively used in each read and verification operation so that determine that the threshold voltage of relevant memory cell is higher than described level and still is lower than described level.For instance, in the read operation of binary storage device unit, selected word line WL2 is a ground connection, so that whether detection threshold voltage is higher than 0V.In the verification operation of binary storage device unit, selected word line WL2 is connected to 0.8V, for example, so that whether verification threshold voltage has reached the target level of 0.8V when programming is carried out.During reading and verifying, source electrode and p trap are in 0 volt.Make selected bit line (BLe) be pre-charged to the level of (for example) 0.7V.The non-conductive memory cell owing to be associated reads or verifies level if threshold voltage is higher than, and then the potential level of relevant bit line (BLe) keeps high level.On the other hand, because conductive memory cell reads or verify level if threshold voltage is lower than, then the potential level of relevant bit line (BLe) is reduced to low level, for example, and less than 0.5V.The state of memory cell is detected by the sensor amplifier that is connected to bit line and sensing gained bit-line voltage.The difference of memory cell between programming is still wiped depends on whether net negative charge is stored in the floating grid.For instance, if negative charge is stored in the floating grid, then threshold voltage becomes higher and transistor can be in the enhancement mode of operation.In another embodiment, can read memory cell by the electric current that detects by the memory cell conduction.

When program memory cells in an example, drain electrode and p trap receive 0 volt and the control grid receives a series of programming pulses with increase value.In one embodiment, in the described series value of pulse in 12 volts to 24 volts scopes.In other embodiments, the scope of pulse can be different in the described series.The value of pulse increases, and wherein each pulse increases predetermined step-length.Comprise among the embodiment of the memory cell of storing a plurality of data bit that one exemplary step-length is 0.2 volt (or 0.4 volt).During program memory cells, carry out verification operation in the cycle between programming pulse.With empirical tests with through fully programmed cells locking, for example in the NAND unit, by for all subsequently programming pulse bit-line voltage is elevated to V from 0 _DD(for example, 2.5 volts) are to stop the programming process of described memory cell.

When the programming process of success finished, the threshold voltage of memory cell should be in one or more of the threshold voltage of program memory cells distribute, or in due course in the distribution of the threshold voltage through wiping memory cell.Fig. 9 illustrates when two data bit of each memory cell stores, the example threshold voltage distribution of described memory cell array.Fig. 9 shows through wiping the first threshold voltage distribution E of memory cell.Also describe three threshold voltage distribution A, B and C through program memory cells.In one embodiment, the threshold voltage in E distributes (also being called physical state E) is positive for negative and threshold voltage in A, B and C distribution (also being called physical state A, B and C).

Each distinct threshold voltage range of Fig. 9 is corresponding to the predetermined value of described group of data bit.Particular kind of relationship between the data in being programmed into memory cell and the threshold voltage levels of memory cell depends on the data coding scheme that is suitable for memory cell.For instance, United States Patent (USP) the 6th, 222, No. 762 and U.S. Patent Publication case 2004/0255090 are described the various data coding schemes of multimode flash memory cells, and the full text of described two patents is incorporated herein by reference.In one embodiment, use Gray (Gray) code assignment that data value is assigned to threshold voltage ranges so that when the threshold voltage of floating grid is displaced to its vicinity physical state mistakenly, only will influence a position.One example assigns " 11 " to give threshold voltage ranges E (state E), assigns " 10 " to give threshold voltage ranges A (state A), and appointment " 00 " is given threshold voltage ranges B (state B) and assigned " 01 " to give threshold voltage ranges C (state C).Yet, in other embodiments, do not use Gray code.Although Fig. 9 shows four kinds of states, the present invention also can use with other multimode structure (comprising those structures that have greater or less than four kinds of states).

Fig. 9 shows that three are read fiducial value---voltage Vra, Vrb and Vrc---to be used for from the memory cell reading of data.Be higher than or be lower than Vra, Vrb and Vrc by the threshold voltage of testing given memory cell, system can determine what state memory cell is in.

Figure 11 shows three checkings target level---voltage Vva2, Vvb2 and Vvc2.When program memory cells arrived state A, system will test those memory cells to be had greater than the threshold voltage that still equals Vva2.When program memory cells arrived state B, system had test memory cells greater than the threshold voltage that still equals Vvb2.When program memory cells arrives state C, system will determine that memory cell has it greater than the threshold voltage that still equals Vvc2.

In one embodiment, be called complete sequence programming, can make memory cell directly be programmed into programming state A, B or the C any one from erase status E.Although some memory cells are programmed into state A from state E, other memory cell is programmed into state B and/or is programmed into state C from state E from state E.

Except that complete sequence mentioned above programming, Fig. 9 also illustrates the not example of the two-pass technique of the multistate memory unit of the data of same page (lower page and upper page) of two of program storage.For state E, two pages or leaves are all stored " 1 ".For state A, lower page stores " 0 " and upper page stores " 1 ".For state B, two pages or leaves are all stored " 0 ".For state C, lower page stores " 1 " and upper page stores " 0 ".Although it should be noted that each that specific bit patterns is assigned to described state, also can assign different bit patterns.

In first pass programming, according to the threshold voltage levels for the treatment of in being programmed into down logical page (LPAGE) of setting memory cell.If institute's rheme is a logical one, then threshold voltage is not changed, because it is in appropriate state because of early being wiped free of.Yet, being logical zero if treat position by programming, the threshold level of unit is increased to state A, as by shown in the arrow 600.That described first pass programming that just is through with.

In second time programming, according to the threshold voltage levels for the treatment of in being programmed into logical page (LPAGE) of setting memory cell.Take place if last logical page (LPAGE) position, then has programming with stored logic " 1 ", because the unit is among one among state E or the A according to the programming of lower page bit, two states all carries upper page bit " 1 ".If upper page bit will be logical zero, then threshold voltage shift.If first pass causes the unit still to be among the erase status E, the described unit of then programming in subordinate phase is so that threshold voltage is increased in the state C scope, as being described by arrow 604.If the unit is because the first pass programming is programmed among the state A, then memory cell is programmed so that threshold voltage is increased in the state B scope, as being described by arrow 602 through further in second time.Second time result is for being programmed into the unit data that do not change lower page in the state of specifying the upper page stores logical zero.

In one embodiment, can write to carry out complete sequence writing enough data setting system when filling whole page.If do not write enough data to be used for full page, then programming process may be programmed in the lower page of programming when receiving data.When receiving subsequent data, system's upper page of will then programming.In another embodiment, system can begin to write in the pattern of programming lower page and be converted to the complete sequence programming mode when receiving the memory cell of enough data whole to fill (or most of) word line subsequently.The more details of described embodiment are disclosed in inventor Sai Jia Natoli Alexeyevich brother's Lip river bit (SergyAnatolievich Gorobets) and Li Yan (Yan Li) is the U.S. patent application case the 11/013rd of " using the pipeline programming (Pipelined Programming of Non-Volatile MemoriesUsing Early Data) of the nonvolatile memory of early time data " at the title of application on Dec 14th, 2004, in No. 125, the full text of described application case is incorporated herein by reference.

Figure 10 A discloses another process that is used for programming nonvolatile memory to Figure 10 C, for any particular memory cell, described process is by being written to the coupling effect that reduces floating grid and floating grid with respect to the described particular memory cell of specific page after the adjacent memory cell that is written to previous page or leaf.By Figure 10 A in an example of the embodiment of the process of Figure 10 C teaching, Nonvolatile memery unit uses two data bit of four kinds of each memory cell stores of data mode.For instance, suppose that state E is that erase status and state A, B and C are programming state.State E stores data 11.State A stores data 01.State B stores data 10.State C stores data 00.This is the example of non-Gray code, because two positions change between adjacent states A and B.Also can use other coding of the data of physical data state.Two data pages of each memory cell stores.Be in reference purpose, described data page will be known as upper page and lower page; Yet it can be presented other mark.About the status of processes A of Figure 10 A to Figure 10 C, upper page data be 0 and lower page data be 1.About state B, upper page data be 1 and lower page data be 0.About state C, two pages or leaves are all stored data 0.

Figure 10 A is the process of two steps to the programming process of Figure 10 C.In first step, the programming lower page.If lower page will keep data 1, then memory cell state remains in state E.If data will be programmed into 0, the threshold voltage of the memory cell that then raises is so that memory cell is programmed into state B '.Therefore, Figure 10 A shows the programming of memory cell from state E to state B '.The state B ' that describes in Figure 10 A is interim state B; Therefore, will verify that target level depicts Vvb2 ' as, it is lower than Vvb2.

In one embodiment, from state E after state B ' program memory cells, with then with respect to its underpart page or leaf its neighbor memory cell in the NAND string of programming.For instance, later referring to Fig. 2, after the lower page of program memory cells 106, with the lower page of program memory cells 104.After program memory cells 104, if memory cell 104 has the threshold voltage that is elevated to state B ' from state E, then the coupling effect of floating grid and floating grid is with the apparent threshold threshold voltage of rising memory cell 106.This will have the effect that the threshold voltage distribution that makes state B ' is widened the threshold voltage distribution of being described as the threshold voltage distribution 620 of Figure 10 B.Described apparent the widening of threshold voltage distribution will be remedied when programming upper page.

Figure 10 C describe to programme process of upper page.If memory cell is in erase status E and upper page will remain 1, then memory cell will remain in state E.If memory cell is in state E and its upper page data will be programmed into 0, then the threshold voltage of memory cell will raise so that memory cell is in state A.If memory cell in intermediate threshold voltage distribution 620 and upper page data will remain 1, then memory cell will be programmed into end-state B.If memory cell in intermediate threshold voltage distribution 620 and described upper page data will become data 0, then with the threshold voltage of rising memory cell so that memory cell is in state C.Because the skew of maximal value Vt during the upper page programming reduces when the E state is to C state programming unit from the E state to A condition or from the B state to the C state rather than from Fig. 9, so the process of being described to Figure 10 C by Figure 10 A reduces the coupling effect of floating grid and floating grid, therefore, the programming of the upper page of neighbor memory cell will have little effect to the apparent threshold threshold voltage of given memory cell.Although Figure 10 A provides example about four kinds of data modes and two data pages to Figure 10 C, can be applicable to have greater or less than four kinds of states and greater or less than other embodiment of two pages to the notion of Figure 10 C institute teaching by Figure 10 A.

It should be noted that the various order that have the various pages or leaves that are used to programme.The programme many different order of various page or leaf of being used to that can be suitable for particular use the present invention.More information about programming can be the U.S. patent application case the 11/099th of " in the read operation compensating during coupling (Compensating forCoupling During Read Operations of Non-Volatile Memory) of nonvolatile memory " at the title of application on April 5th, 2005 old building (Jian Chen), find in No. 133, the full text of described application case is incorporated herein by reference.

In order to reduce the influence that programming is disturbed, different target checking level can be used for particular word line (or other grouping of memory element) during the verification step of programming process.Figure 11 provides word line and the drain selection line of explaination to adjacency drain selection grid to use one group of target level and other word line is used the process flow diagram of an embodiment of the process of another group target level.In the step 650 of Figure 11, use first group of target level programmed word line WL0, treat first word line by programming and in abutting connection with the word line of source electrode selection wire SGS (referring to Fig. 2,3 and 8).That is, whether all or a son group memory cell that uses the programming of first group of target level to be connected to WL0 has finished programming with the checking corresponding memory cell.In step 652, use second group of target level programming residue (or another son group) word line.That is, for instance, use the programming of second group of target level be connected to WL1 to all or the son group memory cell of WL4 to verify whether corresponding memory cell has finished programming.Later referring to Fig. 5, word line WL0 is in the edge of pressurizing area 380.

In one embodiment, first group of target level comprises Vva1, Vvb1 and Vvc1; And second group of target level comprises Vva2, Vvb2 and Vvc2.In an example embodiment, Vva1 is than corresponding Vva2 low about 100 to 200mV, and Vvb1 is than corresponding Vvb2 low about 100 to 200mV, and Vvc1 is than corresponding Vvc2 low about 100 to 200mV.

In other embodiments, the child group of first group of target level can be identical with the child group of second group of target level.This is because in some embodiments, can find that the programming interference only is the problem for the memory cell that is in some programming states (for example, state A, or state A and state B).Therefore, in certain embodiments, first group of target level comprises that Vva1, Vvb2 and Vvc2 and second group of target level comprise Vva2, Vvb2 and Vvc2.In other embodiments, first group of target level comprises that Vva1, Vvb1 and Vvc2 and second group of target level comprise Vva2, Vvb2 and Vvc2.Also can implement other arrangement.

When target level in first and second group target level finishes programming for the comparison point of using with the decision memory cell during programming process.For instance, the memory cell that is programmed into state A at being intended on the WL0 will be finished programming process and will finish programming process at the memory cell that being intended on the WL3 is programmed into state B when its threshold voltage has reached Vvb2 when its threshold voltage has reached Vva1.

There are some devices that use two-phase coarse/fine program method to programme.First phase (phase of programming roughly) comprises attempts with raise threshold voltage and relatively less note to realize tight threshold distribution of very fast mode.Second phase (fine program phase) attempts also to realize threshold distribution more closely with the threshold voltage that raises than slow mode simultaneously to realize target threshold voltage.The example of coarse/fine program method can find in following patent documentation: No. the 2005/0162916th, U.S. Patent Publication case; United States Patent (USP) the 6th, 301, No. 161; United States Patent (USP) the 5th, 712, No. 815; United States Patent (USP) the 5th, 220, No. 531; Reach No. the 5th, 761,222, United States Patent (USP), the full text of described patent is incorporated herein by reference.During the verifying memory unit, the checking level was carried out the proof procedure of coarse mode and is then used the checking target level to carry out the proof procedure of fine pattern subsequently in the middle of some previous solutions will at first be used during programming.The solution of the present invention that is used to change target level is applied to the checking target level during fine pattern.In some cases, also can change middle checking level.

By reducing the target level of word line WL0, in the colony of memory cell, the threshold voltage through program memory cells that the is connected to WL0 residing state of situation threshold voltages that target level do not reduce that coexists is compared and should have been reduced.For instance, Figure 12 A shows two threshold distribution of a kind of programming state (for example, state A).An example of the threshold voltage distribution (number of memory cell is to threshold voltage) of the memory cell that is connected to all word lines (except the word line WL0) is represented in distribution 670.Distribute 672 representatives when all word lines use same target level, be connected to the example of threshold voltage distribution of the memory cell of word line WL0.Because programming mentioned above is disturbed, to compare with distribution 670, distribution 672 is displaced to the right side and is widened.As can be seen, distribute 672 670 outstanding from distributing in the upper end.

By use word line WL0 than group's target level (as according to step 650 and 652), be displaced to the left side with threshold voltage distribution that WL0 is associated through program memory cells so that its when finishing programming process in the scope of the corresponding threshold voltage distribution that is associated with other word line.For instance, after Figure 12 B is illustrated in and finishes programming process (one or multipage through programming to hold the storage of one group of data (for example digital photos or other file)), owing to use being displaced to the distribution 672 in left side than the low target level and 672 being matched with in the distribution 670 of WL0 so that distribute.In another embodiment, finish programming process (one or multipage through the programming to hold the storage of one group of data (for example digital picture or other file)) after, distribute 672 since use WL0 than the low target level be displaced to the left side so that with Figure 12 A in describe compare, distribute and 672 670 less give prominence to from distributing at least in the upper end.If compare with describing among Figure 12 A, it is 672 670 less outstanding from distributing at least in the upper end to distribute, and then during reading process (for example, using ECC), any remainder error can be fixing.

It should be noted that distribution 672 and distribute 670 representative a kind of states (for example, state A, state B, state C, or different conditions).In one example, under the situation of three kinds of programming states (adding a kind of erase status), 670 similarly reach at three pairs corresponding threshold voltage distribution exist with distribution 672 and distribute.In containing the embodiment that two above information bits is stored in the memory cell, can exist and distribute 672 and the 670 similar threshold voltage distribution right more than three that distribute.In some cases, be less than all states and will have the distribution that it is offset on WL0.

Later referring to Figure 11, in step 660, use one group to read fiducial value and read all or a son group memory cell that is connected to WL0.For instance, reading fiducial value Vra, Vrb and Vrc (referring to Fig. 9) can be in order to read the data that are stored in the memory cell.In step 662, use with step 660 in all or the son that fiducial value reads the word line that is connected to beyond the WL0 that read on the same group mutually that use organize memory cell.It should be noted that arrow between step 652 and the step 660 dot with representative can the time that is different from step 650 and 652 and/or with step 651 and 652 incoherent mode execution in step 660.

Figure 13 provides explaination that the word line in the edge of pressurizing area is used one group of target level and other word line is used the process flow diagram of embodiment of the process of another group target level.In the process of Figure 11 mentioned above, WL0 is in the edge of pressurizing area.Yet in other embodiments, the edge of pressurizing area can be positioned other local place.In the step 680 of Figure 13, whether the memory cell that uses second group of target level programming to be connected to first group of word line has finished programming with the checking corresponding memory cell.In step 682, whether the memory cell of word line that uses the programming of first group of target level to be connected to the edge of pressurizing area has finished programming with the checking corresponding memory cell.In step 684, whether the memory cell that uses second group of target level programming to be connected to the residue word line has finished programming with the checking corresponding memory cell.In other embodiments, can comprise additional set word line and extra edge word lines.

In step 690, use one group to read fiducial value (for example, Vra, Vrb and Vrc) and read the memory cell that is connected to first group of word line.In step 692, use with step 692 in use mutually on the same group read the memory cell that fiducial value reads in the word line of the edge that is connected to pressurizing area during the programming.In step 694, use with step 692 on the same group the fiducial value that reads mutually of use read the memory cell that is connected to the remaining set word line.It should be noted that arrow between step 684 and the step 690 dot with representative can the time that is different from step 684 and/or with the incoherent mode execution in step 690 of step 684.

The different pieces of information page or leaf that Figure 14 provides explaination that the word line (for example, in abutting connection with the source electrode selection wire) with the edge of pressurizing area is associated uses not target level on the same group and other word line is used the process flow diagram of embodiment of the process of another group target level.In step 710, first data page is used first group of target level (Vva1, Vvb1, Vvc1) and uses not target level programming on the same group to be connected to the memory cell of word line WL0 (or another word line) to second data page.For instance, target level can not comprise target level Vva3, Vvb3, Vvc3 on the same group, wherein:

(1) Vva3 ≠ Vva1, Vvb3 ≠ Vvb1, Vvc3 ≠ Vvc1; And

(2)Vva3<Vva2，Vvb3<Vvb2，Vvc3<Vvc2。

In other embodiments, target level can not comprise among target level Vva3, Vva3 and the Vvb3 some on the same group, and the residue target level is identical with first group of target level or second group of target level.

In step 712, as indicated above, use second group of target level programming to be connected to the memory cell of WL0 additional word lines in addition.

In step 720, use one group to read fiducial value (for example, Vra, Vrb and Vrc) and read all or a son group memory cell that is connected to word line WL0.In step 722, use with step 720 in all or the son that fiducial value reads the word line that is connected to beyond the word line WL0 that read on the same group mutually that use organize memory cell.It should be noted that arrow between step 712 and the step 720 dot with representative can the time that is different from step 712 and 710 and/or with step 712 and 710 incoherent mode execution in step 720.

The word line that Figure 15 provides the edge of explaination to being connected to pressurizing area (for example, in abutting connection with source electrode selection wire, for example WL0) the Different Plane (or section or group) of memory cell use not target level on the same group and other word line used the process flow diagram of embodiment of the process of another group target level.In step 740, the memory cell of first grouping used first group of target level and uses not on the same group target level to programme to the memory cell of second grouping be connected to the memory cell of word line WL0 (or different word line).In step 742, use second group of target level programming to be connected to the memory cell of WL0 additional word lines in addition.

For instance, later referring to Fig. 8, first plane or grouping can comprise and be connected to memory cell and second plane or divide into groups can comprise be connected to bit line Ble2128 memory cell to the NAND string of Ble4255 of bit line Ble0 to the NAND string of Ble2127.In another embodiment, first plane or grouping can comprise and be connected to memory cell and second plane or divide into groups can comprise be connected to bit line Blo2128 memory cell to the NAND string of Blo4255 of bit line Blo0 to the NAND string of Blo2127.Another of first plane or grouping substitute comprise be connected to bit line 0 to the NAND string of (1/2 (x)-1) memory cell and another of second plane or grouping is alternative can comprise that being connected to bit line 1/2 (x) arrives memory cell on the NAND string of (x-1), wherein x is the total number of the bit line of user data.Alternative another the alternative memory cell that can comprise on the NAND string that is connected to even wordline that can comprise the memory cell on the NAND string that is connected to positions of odd wordlines and second plane or grouping of another of first plane or grouping.Also other grouping can be used, and plural grouping can be used.

In step 750, use one group to read fiducial value (for example, Vra, Vrb and Vrc) and read all or a son group memory cell that is connected to word line WL0 (or another word line).In step 752, use with step 750 on the same group all or the son that fiducial value reads the word line that is connected to beyond the word line WL0 that read mutually that use organize memory cell.It should be noted that arrow between step 742 and the step 750 dot with representative can the time that is different from step 740 and 742 and/or with step 740 and 742 incoherent mode execution in step 750.

Figure 16 is the process flow diagram of an embodiment of description programming operation.The process of Figure 16 can be with being connected to the memory cell of word line to use complete sequence to programme.In different time was programmed the embodiment of same page not, the process of Figure 16 can be with thinking a particular word line or particular group memory cell programming one page or one time.Because programming process can comprise a plurality of page or leaf of programming and be connected to the memory cell of a plurality of word lines, thus programming process can comprise carry out Figure 16 programming operation repeatedly.

Wipe at step 840 place and to treat memory cell by programming.Step 840 can comprise than treating that those memory cells by programming (for example, in piece or other unit) wipe more multi-memory unit.At step 842 place, carry out soft programming so that wipe the distribution narrow of the erase threshold voltage of memory cell.Because erase process, some memory cells are comparable to be in darker erase status in case of necessity.Soft programming can apply little programming pulse with move wipe memory cell threshold voltage near the erase verification level.At step 850 place of Figure 16, command circuit 514 is sent and be input to " data load " order by controller 518, thereby allow data to be input to data input/output (i/o) buffer 512.The input data are considered to order and are latched via the order latch signal (not shown) that is input to command circuit 514 by state machine 516.At step 852 place, address date slave controller or the main frame of representing page address is input to line control unit or demoder 506.The input data are considered to page address and latch via the state machine 516 that the address latch signal that is input to command circuit 514 influences.At step 854 place, will be input to data input/output (i/o) buffer 512 through the programming data page or leaf of addressed page to be used for programming.For instance, can import the data of 582 bytes in one embodiment.With described data latching in the suitable register of selected bit line.In certain embodiments, also with data latching in second register of selected bit line to be used for verification operation.At step 856 place, data input/output (i/o) buffer 512 is sent and be input to " programming " order by controller 518.Described order is latched via the order latch signal that is input to command circuit 514 by state machine 516.

After by " programming " command triggers,, will in step 854, latched data be programmed in the word-select memory unit of controlling by state machine 516 by using the step-by-step impulse that applies to suitable word line.At step 858 place, initialization Vpgm (program voltage pulse that applies to selected word line) is to initial value (for example, about 12V or another suitable level) and the program counter PC that kept by state machine 516 in the initialization of 0 place.At step 860 place, apply a Vpgm pulse to selected word line.If logical zero is stored in indication and should programmes in the particular data latch of corresponding stored device unit, then corresponding bit line ground connection.On the other hand, the unit should remain in the particular lock storage of its current data state if logical one is stored in indication corresponding stored device, and then corresponding bit line is connected to V _DDTo forbid programming.As describing among Fig. 4 and Fig. 5, selected word line receives Vpass, sets at Vsgd place that signal is selected in drain electrode and at 0v place setting drain selection signal.At 0 volt or near 0 Fu Chu setting source electrode line.

At step 862 place, use the state that target level is verified the word-select memory unit of suitably organizing, as mentioned referring to Figure 11,13,14 and 15 argumentations.Reached suitable target level if detect the threshold voltage of selected unit, the data that then are stored in the corresponding data latch change to logical one.Do not reach suitable target level as yet if detect threshold voltage, the data that then are stored in the corresponding data latch are not changed.In this way, needn't the bit line with logical one of program storage in its corresponding data latch.When the positive stored logic of all data latches " 1 ", state machine is known all selected unit of programming.At step 864 place, check whether just stored logic " 1 " of all data latches.If then programming process is finished and is successfully, because all word-select memory unit are through programming and authenticating to its dbjective state.Report at step 866 place " by " state.It should be noted that in some embodiments, check the whether positive stored logic " 1 " of data latches of at least one predetermined number at step 864 place.Described predetermined number can be less than the number of all data latches.Therefore, allowing programming process to reach it at all memory cells suitably stops before the checking level.Can during reading process, use error proofread and correct the memory cell of programming without success.

If at step 864 place, determine not to be the positive stored logic of all data latches " 1 ", then programming process continues.At step 868 place, the contrast program limit value is checked program counter PC.One example of program limit value is 20; Yet, in various embodiments, can use other value.If program counter PC is not less than 20, then determine whether be equal to or less than predetermined number without the number of successful memory cell of programming at step 869 place.If the number of the success memory cell of programming is not equal to or less than described predetermined number, then programming process be marked as by and at step 871 place report passing through state.Under many situations, can during reading process, use error proofread and correct the memory cell of programming without success.Yet if the number of the success memory cell of programming is not greater than described predetermined number, programming process is marked as failure and in step 870 place report status of fail.If program counter PC is less than 20, then the Vpgm level increases described step-length (for example, 0.2 to 0.4 volt of step-length) and increases progressively at the program counter PC of step 872 place.After step 872, described process turns back to step 860 to apply next Vpgm pulse.

Figure 17 be depicted in read or an iteration of verification operation during the sequential chart of behavior of various signals.For instance, if memory cell is the binary storage device unit, then read or proof procedure during can carry out the process of Figure 17 concurrently at each memory cell.If memory cell for have four kinds of states () multistate memory unit for example, E, A, B and C, then read or proof procedure during can carry out the process three times of Figure 17 concurrently at each memory cell.For instance, when when having the memory cell reading of data of four kinds of states, available Vcgr=Vra carries out and reads process once, and carry out the process that reads with Vcgr=Vrb and carry out once and with Vcgr=Vrc and read process once, or other group read value.When being that available Vcgr=Vva2 carries out and reads process once when having the memory cell verification msg of four kinds of states, carry out the process that reads with Vcgr=Vvb2 and once and with the Vcgr=Vvc2 execution read process once, or other group being verified level.

Usually, read and verification operation during, selected word line is connected to a voltage, the level of described voltage is exclusively used in each and reads and whether verification operation has reached described level so that determine the threshold voltage of relevant memory cell.After applying word line voltage, the conduction current of measuring memory cell is to determine whether connecting memory cell in response to the voltage that applies to word line.If measure conduction current greater than particular value, suppose then that memory cell is connected and the voltage that applies to word line greater than the threshold voltage of memory cell.Be not more than described particular value if measure conduction current, then suppose the memory cell access failure and be not more than the threshold voltage of memory cell to the voltage that word line applies.

Exist in read or verification operation during measure many methods of the conduction current of memory cell.In one example, the conduction current of memory cell can be measured by its speed of discharging dedicated capacitor in sensor amplifier.In one embodiment, use the memory array of all bit line program can measure the conduction current of memory cell by its speed of in sensor amplifier, discharging dedicated capacitor.In another example, the conduction current of word-select memory unit allows (or failing to allow) to comprise the NAND string discharge bit line of memory cell.Whether discharged to understand it at the electric charge of measuring on the bit line after the time cycle.In one embodiment, use the memory array of odd/even programming can measure the conduction current of memory cell by the bit line that determines whether to discharge.

Figure 17 shows that signal SGD, the WL_ originate in Vss (being about 0 volt) are selected, WLn, SGS, select BL and source electrode.SGD representative being connected to drain electrode and selecting signal on the drain electrode selection wire of grid of grid.SGS representative is connected to the signal on the drain selection line of grid of drain selection grid.WLn is for through the selected word line that reads/verify of being used to.The not selected not selected word line of representing of WL_.Selected _ BL is for through the selected bit line that reads/verify of being used to.Source electrode is the source electrode line of memory cell.

Figure 17 describes the behavior of system of measuring the conduction current of memory cell by the bit line that determines whether suitably to discharge.At the time of Figure 10 t1 place, make SGD (for example be elevated to Vdd, about 3.5 volts) or another voltage (usually in the 3-5V scope), making not, selected word line (WL_ is not selected) (for example is elevated to Vread, about 5.5 volts), make selected word line WLn be elevated to Vcgr, and make the selected BL of selected bit line be pre-charged to about 0.7 volt.Voltage Vread serves as by voltage (because it causes the connection of unselected memory unit) and serves as and pass through grid.At time t2 place, connect the drain selection grid to Vdd by rising SGS.This provides a path to reduce the electric charge on the bit line.If greater than Vcgr, then (or to major general connect deficiently) will be disconnected and bit line will not discharge (or to major general discharge deficiently) in the word-select memory unit, as being described by signal wire 890 through the threshold voltage of the selected memory cell that is used to read.If the threshold voltage through the selected memory cell that is used for reading is lower than Vcgr, then the memory cell that is used to read will be connected (conduction) and bit-line voltage will reduce through selecting, as being described by curve 892.After time t2 and certain some place before the time t3 (as being determined by particular), suitably sensor amplifier will determine whether bit-line voltage has reduced q.s.At time t3 place, will make the signal of describing be reduced to Vss (or being used for another value standby or that recover).Should note to change the sequential of some signals in other embodiments.

Rather than or except that verifying that by changing target level reduces the influence of disturbing of programming, and can use difference read fiducial value at particular word line (or other grouping of memory element) during reading process.For instance, Figure 18 describes an embodiment of the process that is used for operating nonvolatile memory device, and described method comprises at one or more particular word line uses difference to read fiducial value.In step 920, use second group of target level programming referred to above to be connected to the memory cell of WL0.In step 922, use second group of target level programming referred to above to be connected to the memory cell of additional word lines.In step 930, use first group to read fiducial value and read the memory cell that is connected to WL0.That is, read fiducial value with second group and be applied to suitably control grid via suitable word line.In step 932, use second group to read fiducial value and read the memory cell that is connected to additional word lines.It should be noted that arrow between step 922 and the step 930 dot with representative can the time that is different from step 922 and 920 and/or with step 922 and 920 incoherent mode execution in step 930.

In another embodiment, step 920 and 930 can be applied to a plurality of word lines (for example, WL0 and WL1, WL0-2 or comprise WL0 but can be in other grouping of the grouping of edge, such as hereinafter explaination).That is the word line that, can have two groups.To use first group to read fiducial value and read first group's word line and will use second group to read fiducial value and read second group's word line.

Figure 19 shows an example set threshold voltage distribution that is similar to distribution depicted in figure 9.Figure 19 describes two of each state and reads fiducial value.Reading fiducial value Vra1 and Vra2 is associated with state A.Reading fiducial value Vrb1 and Vrb2 is associated with state B.Reading fiducial value Vrc1 and Vrc2 is associated with state C.In one embodiment, first group is read fiducial value and comprises Vra1, Vrb1 and Vrc1; Second group is read fiducial value and comprises Vra2, Vrb2 and Vrc2; And Vra1〉Vra2, Vrb1〉Vrb2 and Vrc1〉Vrc2.Therefore, when execution in step 930, the process of carrying out Figure 17 with Vcgr=Vra1 at WL0 once, the process of carrying out Figure 17 with Vcgr=Vrb1 at WL0 once and the process of carrying out Figure 17 with Vcgr=Vrc1 at WL0 once.When execution in step 932, at each process of carrying out Figure 17 with Vcgr=Vra2 of main word line (subject word line) once, at each process of carrying out Figure 17 with Vcgr=Vrb2 of main word line once, and once at each process of carrying out Figure 17 with Vcgr=Vrc2 of main word line.In other embodiments, first group is read fiducial value and can comprise Vra1, Vrb1 and Vrc2; Or first group read fiducial value and can comprise Vra1, Vrb2 and Vrc2.Also can implement other arrangement.

In another embodiment of step 930, first group is read fiducial value and reads fiducial value in order to read the second son group memory cell that is connected to word line WL0 in order to read the first son group memory cell that is connected to word line WL0 and the 3rd group.As indicated above, two son groups can be in Different Plane or the memory cell in dividing into groups.In one embodiment, two son groups are what separate, for example, and odd number and even bitlines; Or first plane or grouping comprise that being connected to memory cell and second plane or the grouping of bit line 0 to the NAND string of (1/2 (x) 1) can comprise and be connected to the memory cell of bit line 1/2 (x) to the NAND string of (x-1) that wherein x is the total number of the bit line of user data.Also can use other grouping.It should be noted that the 3rd group read fiducial value with second group to read fiducial value (partially or completely) different.

In another embodiment of step 930, first group is read fiducial value and reads fiducial value in order to read the data that are stored in second data page in the memory cell that is connected to word line WL0 in order to read the data that are stored in first data page in the memory cell that is connected to word line WL0 and the 3rd group.The 3rd group read fiducial value with second group to read fiducial value (partially or completely) different.

Figure 20 describes another embodiment of the process that is used for operating nonvolatile memory device, and described process comprises at particular word line uses difference to read fiducial value.In step 950, use second group of target level programming referred to above to be connected to the memory cell of first group of word line.In step 952, use second group of target level programming referred to above to be connected to the memory cell of word line of the edge of pressurizing area.In step 954, use second group of target level programming referred to above to be connected to the memory cell of residue word line.It should be noted that the word line in the edge of pressurizing area is not the part of first group of word line and residue word line.

During the step 950,952 and 954 of Figure 20, programming operation be included in provide on word line or the selection wire 0 vor signal (or other proper signal) to disconnect corresponding transistor so that form pressurizing area.One example comprises to drain selection line SGS and applies 0 volt so that the drain selection grid disconnects, and described drain selection grid cuts off raceway groove and helps to cause the supercharging of NAND string from source electrode line.In certain embodiments, the word line that is connected to NAND string can receive 0 vor signal (or other proper signal) and be connected to the memory cell of described word line so that pressurizing area finishes or originate in described word line with cut-out.This also can be in order to form a plurality of pressurizing area.

In step 960, use second group referred to above to read fiducial value and read the memory cell that is connected to first group of word line.In step 962, use first group referred to above to read the memory cell that fiducial value reads the word line of the edge that is connected to pressurizing area.In step 964, use second group read fiducial value read be connected to the residue word line memory cell.It should be noted that arrow between step 954 and the step 960 dot with representative can the time that is different from step 954 and/or with the incoherent mode execution in step 960 of step 964.

In some embodiment of step 962, not reading fiducial value on the same group can be in order to read the different pieces of information page or leaf that is associated with the word line of the edge of pressurizing area.Not reading fiducial value on the same group can be in order to the plane or the grouping of the memory cell of the word line that reads the edge that is connected to pressurizing area.In two kinds substitute, do not read on the same group fiducial value also with second group to read fiducial value (partially or completely) different.

Although above argumentation focuses on the influence that minimizing is disturbed the programming of particular word line, the present invention also can be in order to reduce because any other is former thereby have an influence of the word line that broad Vt distributes.A kind of other reason that broad Vt distribute to occur on some word lines can be the so-called programming of crossing, and it is because the fast programming memory cell that (for example) concentrates on the word line of or a restricted number causes.Crossing programming also produces as similar Vt distribution depicted in figure 12.Be applied to described word line by difference being verified target level or being read fiducial value, also can reduce the influence that Vt on described word line is distributed and widens.

For explanation and description purpose, provide above detailed description the in detail of the present invention.It is not to be intended to detailed or to limit the invention to the precise forms that disclosed.According to the many modifications of above teaching and be changed to possible.Select described embodiment so that explain principle of the present invention and practical application thereof best, thereby make others skilled in the art can utilize the present invention in various embodiments best and and utilize the present invention best under the various modifications of special-purpose being suitable for expecting.Wish that scope of the present invention is defined by appending claims.

Claims (15)

1. method of operating nonvolatile memory, it comprises:

Use first group to read fiducial value and read first group of non-volatile memory device, described first group of non-volatile memory device is in abutting connection with the drain selection control line; And

Use second group to read fiducial value and read not second group of non-volatile memory device in abutting connection with described drain selection control line, described first group is read in the fiducial value at least one and is different from described second group of corresponding comparative level that reads in the fiducial value.

2. method according to claim 1, wherein:

All described first group is read fiducial value and all is different from described second group of corresponding comparative level that reads in the fiducial value.

3. method according to claim 1, wherein:

Described first group is read described one in the fiducial value greater than described second group described corresponding comparative level that reads in the fiducial value.

4. method according to claim 1, wherein:

Described first group of non-volatile memory device is connected to first control line, and described first control line is in abutting connection with the drain selection control line; And

Described second group of non-volatile memory device is connected to second control line.

5. method according to claim 4, it further comprises:

Use the 3rd group to read fiducial value and read the 3rd group of one or more non-volatile memory devices, described the 3rd group of non-volatile memory device is connected to first control line.

6. method according to claim 1, wherein:

Describedly read described first group of non-volatile memory device and comprise and use described first group to read fiducial value and read first data page and use the 3rd group to read fiducial value and read second data page.

7. method according to claim 1, wherein:

Described first group of one or more non-volatile memory device and described second group of one or more non-volatile memory device are multimode NAND flash memory device; And

Described first control line and described second group of control line are word line.

8. Nonvolatile memory system, it comprises:

Non-volatile memory device, described non-volatile memory device comprises the first group of non-volatile memory device that is connected to first control line, and being connected to second group of non-volatile memory device of the second group control line different with described first control line, described first control line is in abutting connection with the drain selection control line; And

The management circuit that is communicated with described non-volatile memory device, described management circuit causes and uses first group to read fiducial value and read described first group of non-volatile memory device and use second group to read fiducial value and read described second group of one or more non-volatile memory device, and described first group is read in the fiducial value at least one and be different from described second group of corresponding comparative level that reads in the fiducial value.

9. Nonvolatile memory system according to claim 8, wherein:

Described first group of one or more non-volatile memory device and described second group of one or more non-volatile memory device are multimode NAND flash memory device.

10. Nonvolatile memory system according to claim 8, wherein:

Described non-volatile memory device is arranged in the piece, and each piece comprises one group of page or leaf, and the delimit the organizational structure unit and the piece of journey of described page boundary defines the unit of wiping;

Described first control line and described second group of control line are word line, and described word line is a shared part;

Described shared comprises one group of bit line; And

Each of described first group of non-volatile memory device is connected to a corresponding lines not of described group of bit line.

11. Nonvolatile memory system according to claim 8, wherein:

Described first group is read described one in the fiducial value greater than described second group described corresponding comparative level that reads in the fiducial value.

12. Nonvolatile memory system according to claim 8, wherein:

Describedly read described first group of non-volatile memory device and comprise and use described first group to read fiducial value and read first data page and use the 3rd group to read fiducial value and read second data page.

13. Nonvolatile memory system according to claim 8, wherein:

Described management circuit uses the 3rd group to read fiducial value and read the 3rd group of non-volatile memory device, and described the 3rd group of non-volatile memory device is connected to described first control line.

14. Nonvolatile memory system according to claim 8, wherein:

All described first group is read fiducial value greater than described second group corresponding comparative level that reads in the fiducial value.

15. Nonvolatile memory system according to claim 8, wherein:

Described management circuit comprises any one in controller, state machine, command circuit, control circuit and the demoder or makes up.

Images