CN101420341A - Processor performance test method and device for embedded system - Google Patents
Processor performance test method and device for embedded system Download PDFInfo
- Publication number
- CN101420341A CN101420341A CNA2008101845387A CN200810184538A CN101420341A CN 101420341 A CN101420341 A CN 101420341A CN A2008101845387 A CNA2008101845387 A CN A2008101845387A CN 200810184538 A CN200810184538 A CN 200810184538A CN 101420341 A CN101420341 A CN 101420341A
- Authority
- CN
- China
- Prior art keywords
- message
- layer
- module
- network
- link layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 title claims abstract description 31
- 238000011056 performance test Methods 0.000 title claims description 16
- 238000012360 testing method Methods 0.000 claims abstract description 88
- 230000015572 biosynthetic process Effects 0.000 claims description 34
- 238000004804 winding Methods 0.000 claims description 32
- 230000008569 process Effects 0.000 abstract description 13
- 238000012545 processing Methods 0.000 abstract description 9
- 238000005516 engineering process Methods 0.000 abstract description 3
- 230000005540 biological transmission Effects 0.000 description 14
- 238000010586 diagram Methods 0.000 description 8
- 238000004891 communication Methods 0.000 description 7
- 238000010998 test method Methods 0.000 description 5
- 230000008676 import Effects 0.000 description 4
- 230000006870 function Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000006978 adaptation Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000011156 evaluation Methods 0.000 description 1
- 238000004578 scanning tunneling potentiometry Methods 0.000 description 1
- 235000019832 sodium triphosphate Nutrition 0.000 description 1
Images
Abstract
The present invention relates to a field of an embedded system, especially relates to a technology for testing the CPU performance of the embedded system. The present invention provides a method and a device for testing the CPU performance of an embedded system. The method comprises steps of inputting messages from the transport layer and outputting through the network layer and the data link layer; when determining that the messages output through the data link layer are test messages, sending the test messages to the first network port driving layer; the first network port driving layer caching the received messages into a queue and returning the messages in the queue through the data link layer, the network layer and the transport layer; determining performance of the CPU according to the delay time of the returning messages. The messages are input through the transport layer, output through the network layer and the data link layer to the virtual network port driving layer and are then returned back, finally the CPU performance can be determined according to the delay time of the returning messages. therefore, after the whole sending and receiving processes of messages, the returning time of the messages directly reflects the performance of the CPU in the whole message processing process.
Description
Technical field
The present invention relates to the embedded system field, relate in particular to the technology that the cpu performance of embedded system is tested.
Background technology
At the dedicated computer system of dedicated system design, it compares with common PC embedded system, is more suitable in these dedicated system often, has higher reliability, littler volume and power consumption.Embedded system mainly is made up of flush bonding processor (being embedded type CPU), related hardware, embedded OS and application software system.
In embedded system, to CPU (Central Processing Unit, CPU) test of performance and ordinary PC have very big different: ordinary PC generally realizes by general testing software the test of cpu performance, by moving various STPs, obtain CPU overall performance parameter; And in embedded system, be different from ordinary PC owing to operating system, generally can not move the employed testing software of ordinary PC, and these testing softwares can not test the relevant details of concrete details especially architecture, performance evaluation is not enough for embedded type CPU for this, and is especially not enough especially for the built-in network system that is concerned about message processing capability.
In the prior art, test cpu performance in the built-in network system usually by different level for the built-in network system that handles message.For example, CPU is to TCP (Transmission ControlProtocol in test, transmission control protocol)/IP (Internet Protocol, Internet protocol) the message handling property (as shown in Figure 1) of architecture, can test respectively at transport layer, network layer, data link layer etc., obtain:
TCP mark, its expression CPU handles the performance of transport layer inter-related task; Usually reflected CPU to data and buffer management ability, these are the most general and the maximum place of cost during normally TCP realizes;
IP mark, its expression CPU handles the performance of network layer inter-related task; Promptly represent the handling property that CPU is embodied when finishing the function of network router, gateway and switch;
Link mark, the performance of its expression CPU deal with data link layer inter-related task; Specifically test cpu performance in the data link layer transmission speed with message.
For example, CPU is to TIPC (Telecom Inter Process Communication in test,) the message handling property (as shown in Figure 2) of architecture, can test respectively at Socket layer (socket layer), Port layer (port layer), virtual Link layer (virtual linkage layer) etc., obtain:
Socket mark, the performance of its expression CPU treatment S ocket layer inter-related task; Usually determine socket mark with the message transmissions speed of socket adaptation layer;
Port mark, its expression CPU handles the performance of Port layer inter-related task; Usually determine Port mark with the transmission speed of port layer message;
Link mark, its expression CPU handles the performance of virtual Link layer inter-related task; Usually determine Link mark with message in the transmission speed of virtual Link layer.
The method of testing of prior art can only test out the Local treatment performance of the CPU of embedded system, and for example the performance when handling network layer or data link layer inter-related task can not reflect that CPU handles the performance of message from integral body; And since in zonal testing for each test layer, for example transport layer, network layer all are to carry out input, the output of test packet by the mode that the I/O of system (Input/Output) reads file, therefore, this method of testing I/O access times are more, and the test that the visit of I/O causes is postponed, influenced test result accurately.
Summary of the invention
The embodiment of the invention provides a kind of processor method of testing and device of embedded system, is used to test embedded system and handles the overall performance that device is handled message.
A kind of processor performance test method of embedded system comprises:
Message is imported from transport layer, through network layer, data link layer output;
When the message of confirming the output of described data link layer is test packet, this message is sent to first network port driving layer;
After described first network port driving layer receives message, described packet buffer in formation, and is returned the message in the formation through described data link layer, network layer, transport layer;
Determine described performance of processors time of delay according to returning of the message that returns.
Described test packet is the winding message; And described network layer is sent to described data link layer with this winding message after determining to receive the winding message from described transport layer.
A kind of processor performance test method of embedded system comprises:
Message is imported from transport layer, outputed to first network port driving layer through network layer, data link layer;
After described first network port driving layer receives message, described packet buffer in formation, and is returned the message in the formation through described data link layer, network layer, transport layer;
Determine described performance of processors time of delay according to returning of the message that returns.
A kind of processor performance test device of embedded system comprises: transport layer module, network layer module, data link layer module also comprise:
The message sending module is used for message is sent to described transport layer module;
The first network port driving layer module is used to receive the message of input, and described packet buffer in formation, and is returned the message in the formation; The message of described input is a message that described message sending module sends, arrive the first network port driving layer module after transport layer module, network layer module, data link layer resume module;
The message receiver module is used to receive the message that returns; The described message that returns is a message that the described first network port driving layer module is returned, arrive described message receiver module after data link layer module, network layer module, transport layer module are handled;
The processor performance determination module is used for time of delay of returning of the message that receives according to described message receiver module, determines described performance of processors.
A kind of processor performance test method of embedded system comprises:
Message from the input of socket Socket layer, is exported through port Port layer, virtual link layer;
When the message of confirming the output of described virtual link layer is test packet, this message is sent to first network port driving layer;
After described first network port driving layer receives message, described packet buffer in formation, and with the message in the formation, is returned through described virtual link layer, Port layer, Socket layer;
Determine described performance of processors time of delay according to returning of the message that returns.
A kind of processor performance test method of embedded system comprises:
Message from the input of socket Socket layer, is outputed to first network port driving layer through port Port layer, virtual link layer;
After described first network port driving layer receives message, described packet buffer in formation, and with the message in the formation, is returned through described virtual link layer, Port layer, Socket layer;
Determine described performance of processors time of delay according to returning of the message that returns.
A kind of processor performance test device of embedded system comprises: socket layer module, port layer module, virtual link layer module also comprise:
The message sending module is used for message is sent to described socket layer module;
The first network port driving layer module is used to receive the message of input, and described packet buffer in formation, and is returned the message in the formation; The message of described input is a message that described message sending module sends, arrive the first network port driving layer module after socket layer module, port layer module, virtual link layer resume module;
The message receiver module is used to receive the message that returns; The described message that returns is a message that the described first network port driving layer module is returned, arrive described message receiver module after virtual link layer module, port layer module, socket layer resume module;
The processor performance determination module is used for time of delay of returning of the message that receives according to described message receiver module, determines described performance of processors.
The embodiment of the invention is owing to import test packet from transport layer, arrive first network port driving layer (being the virtual network port Drive Layer) through network layer, data link layer, return this test packet by the virtual network port Drive Layer again through data link layer, network layer, transport layer, thereby according to the performance of determining CPU time of delay of returning of test packet.Like this, message is after having passed through whole transmission, receiving course, and returning of message directly reflected the performance of CPU to the whole process of message processing time of delay.In addition, because input and receive message more than transport layer, I/O that needn't calling system reads the message that handle in intermediate layer (as network layer, data link layer etc.), thereby has reduced the number of times to the I/O visit, the test of having avoided the I/O visit to cause postpones, and makes test result more accurate.
The embodiment of the invention is owing to import message from the Socket layer, arrive first network port driving layer (being the virtual network port Drive Layer) through Port layer, virtual link layer, return this message by the virtual network port Drive Layer again through virtual link layer, Port layer, Socket layer, thereby according to the performance of determining CPU time of delay of returning of message.Like this, message is after having passed through whole transmission, receiving course, and returning of message directly reflected the performance of CPU to the whole process of message processing time of delay.In addition, because input and receive message more than the Socket layer, I/O that needn't calling system reads the message that handle in intermediate layer (as Socket layer, Port layer etc.), thereby has reduced the number of times to the I/O visit, the test of having avoided the I/O visit to cause postpones, and makes test result more accurate.
Description of drawings
Fig. 1 is the schematic diagram that the test CPU of prior art handles the performance of TCP/IP architecture message;
Fig. 2 is the schematic diagram that the test CPU of prior art handles the performance of TIPC architecture message;
Fig. 3 is the schematic diagram that the test CPU of the embodiment of the invention one handles the performance of TCP/IP architecture message;
Fig. 4 is the method flow diagram that the test CPU of the embodiment of the invention one handles the performance of TCP/IP architecture message;
Fig. 5 is the schematic diagram of the network layer handles winding message of prior art;
Fig. 6 is the structure drawing of device that the test CPU of the embodiment of the invention one handles the performance of TCP/IP architecture message;
Fig. 7 is the schematic diagram that the test CPU of the embodiment of the invention two handles the performance of TIPC architecture message;
Fig. 8 is the method flow diagram that the test CPU of the embodiment of the invention two handles the performance of TIPC architecture message;
Fig. 9 is the structure drawing of device that the test CPU of the embodiment of the invention two handles the performance of TIPC architecture message.
Embodiment
The embodiment of the invention by test macro to the whole transmission of message, receive the process of handling, thereby the CPU that determines embedded system to whole message sends, the handling property of receiving course, also just obtained the overall performance of CPU processing message.For example, message for the TCP/IP architecture, the embodiment of the invention is imported message from transport layer, arrive the virtual network port Drive Layer through network layer, data link layer, return this message by the virtual network port Drive Layer again through data link layer, network layer, transport layer, thereby according to the performance of determining CPU time of delay of returning of message.Like this, message is after having passed through whole transmission, receiving course, and returning of message directly reflected that the performance of CPU to the whole process of message processing---the performance that the short more then CPU of return time handles message is just high more time of delay.
The invention provides two specific embodiments.Wherein, embodiment one is the technical scheme of test CPU to the message handling property of TCP/IP architecture; Embodiment two is the technical scheme of test CPU to the message handling property of TIPC architecture.
Embodiment one
TCP/IP (TCP) is a kind of network communication protocol, its standard all communication equipments on the network, especially data transmission format and the load mode between a main frame and another main frame.TCP/IP is the basic agreement of internet.Test CPU to the schematic diagram of the message handling property of TCP/IP architecture as shown in Figure 3, the flow chart of concrete method of testing as shown in Figure 4, comprises following concrete steps:
S401, message is imported from transport layer.
Message continues to pass down after transport layer process.
S402, message arrive network layer; Message is after arriving network layer, and network layer handles accordingly to message.
Because use the winding message to do the above connecting path test of network layer in the prior art usually, therefore, network layer can judge also whether this message is the winding message, if the winding message, then network layer is returned this message to transport layer; If not the winding message shows that this message is the normal message that sends, then network layer sends this message (as shown in Figure 5) to data link layer.
In embodiments of the present invention,, then can the function of network layer be changed, make network layer when detecting the winding message, still send this message to data link layer if utilize the winding message to carry out the test of cpu performance.
S403, message arrive data link layer, and data link layer is handled the back accordingly to message and passed this message down.
S404, judge whether message is test packet; If transmit this message to the virtual network port Drive Layer.
In the built-in network system, be provided with true network port driving layer, be used for sending message, perhaps receive message from network to network; In addition, also be provided with the virtual network port Drive Layer in the built-in network system, the virtual network port Drive Layer is used for using when the test cpu performance.
After judging that the message of exporting from data link layer is test packet, this message is sent to the virtual network port Drive Layer; Otherwise, send to true network port driving layer, by true network port driving layer this message is sent by network.Like this, in the process of test cpu performance, system still can send message to network; That is to say, in test process, do not influence the reception and the transmission of network message.
If system adopts the winding message as test packet, when then the message that the data link layer is exported is judged as the winding message, this message is sent to the virtual network port Drive Layer; Otherwise, send to true network port driving layer, by true network port driving layer this message is sent by network.
Here it is pointed out that and judge that whether message is that the step of test packet is not necessary.For example, the tester can be configured before test---network port driving layer is configured to the virtual network port Drive Layer.Like this, all messages all arrive the virtual network port Drive Layer through after the data link layer, and whether needn't distinguish is test packet again, and decision is to the virtual network port Drive Layer or true network port driving layer sends.
S405, message return after arriving the virtual network port Drive Layer.
The packet buffer that the virtual network port Drive Layer will receive from data link layer is after formation, the message in the formation is not sent to network by hardware device (as network interface card etc.), but activate the receiving interface thread, by the receiving interface thread message in the formation is returned to the upper strata.
S406, message return through data link layer, network layer, transport layer.
S407, according to the transmitting time and the return time of message, determine the time of delay of returning of message, thereby determine the performance of CPU.
After message returns from transport layer, according to the transmitting time and the return time of message, determine the time of delay of returning of message, thereby determine the performance of CPU.Concrete, the transmitting time of the return time-message that returns time of delay=message of message.In order to obtain test result more accurately, can add up the time of delay of returning of a large amount of messages, thereby determine the performance of the CPU of this built-in network system.For example, when the message of adding up on average returns time of delay greater than set point A, then determine the poor-performing of CPU; Perhaps, rule of thumb formulate one and return the time of delay and the cpu performance grade table of comparisons, on average return time of delay, determine corresponding cpu performance grade according to the message of testing.
The processor performance test device of a kind of built-in network system that the embodiment of the invention provides, as shown in Figure 6, comprising: message sending module 601, transport layer module 602, network layer module 603, data link layer module 604, the first network port driving layer module 605, message receiver module 606, processor performance determination module 607.
After 602 pairs of messages that receive from message sending module 601 of transport layer module are made the respective handling of transport layer, send this message to network layer module 603.
Data link layer module 604 is done this message to send these messages to the first network port driving layer module 605 after the respective handling of data link layer after receiving the message that network layer module 603 sends.
The first network port driving layer module 605 in formation, and activates the receiving interface thread with described packet buffer after receiving the message that data link layer module 604 sends; The receiving interface thread returns the message in the formation to data link layer module 604.
Data link layer module 604 receives the respective handling of making the data link layer behind the message that the first network port driving layer module 605 returns, returns this message to network layer module 603.
The message that processor performance determination module 607 is received according to message receiver module 606 return time of delay, determine performance of processors.The time that to be processor performance determination module 607 receive returned packet according to the transmitting time and the message receiver module 606 of this message is determined the time of delay of returning of message, and then definite performance of processors.
Further, described device also comprises:
Test packet determination module 608 is between the first network port driving layer module 605 and data link layer module 604, and whether the message that judgment data link layer module 604 sends to the first network port driving layer module 605 is test packet; If then this message is forwarded to the first network port driving layer module 605; Otherwise, this message is forwarded to the second network port driving layer module, 609, the second network port driving layer modules, the 609 driving network hardwares this message is sent to network.
Further, network layer module 603 also is used for still this message being sent to described data link layer module after definite message that receives from transport layer is the winding message.
The embodiment of the invention is owing to import message from transport layer, arrive the virtual network port Drive Layer through network layer, data link layer, return this message by the virtual network port Drive Layer again through data link layer, network layer, transport layer, thereby according to the performance of determining CPU time of delay of returning of message.Like this, message is after having passed through whole transmission, receiving course, and returning of message directly reflected the performance of CPU to the whole process of message processing time of delay.
Because input and reception message more than transport layer, I/O that needn't calling system reads the message that handle in intermediate layer (as network layer, data link layer etc.), thereby reduced the number of times to the I/O visit, the test of having avoided the I/O visit to cause postpones, and makes test result more accurate.
Embodiment two
The TIPC agreement is the transparent interior interprocess communication protocol, with shared drive is the scheduling of basic realization task and resource, the TIPC protocol specialized is used for inner cluster (intra cluster) communication, be in different nodes in the identical cluster and can consider that residing position directly carries out rapid and reliable communication, intra cluster can be the distributed multi-processor system of any kind.TIPC provides a cover transparent reliable host-host protocol for the interprocess communication of distributed system.
For the cpu performance in the full test built-in network system, can also test the performance (as shown in Figure 7) of CPU processing TIPC message, concrete method of testing and above-mentioned test CPU are similar to the method for testing of TCP/IP handling property, and flow chart comprises the steps: as shown in Figure 8
S801, message is imported from the Socket layer.
Message continues to pass down after the Socket layer is handled.
S802, message arrive the Port layer, and the Port layer handles accordingly to message.
Similarly, use the winding message to do the above connecting path test of Port layer in the prior art usually, therefore, the Port layer can judge also whether the message of reception is the winding message, if the winding message, then Port course Socket layer returns this message; If not the winding message shows that this message is the normal message that sends, then the virtual Link layer of Port course sends this message.
In embodiments of the present invention,, then can the function of Port layer be changed, make the Port layer when detecting the winding message, still send this message to virtual Link layer if utilize the winding message to carry out the test of cpu performance as test packet.
S803, message arrive virtual Link layer, and virtual Link layer is handled the back accordingly to message and passed this message down.
S804, judge whether message is test packet; If send this message to the virtual network port Drive Layer.
Similarly, in the built-in network system, also can be provided with true network port driving layer and virtual network port Drive Layer at the TIPC body.True network port driving layer is used for sending message to miscellaneous equipment or system, perhaps receives message from miscellaneous equipment or system; The virtual network port Drive Layer is used for using when the test cpu performance.
After the message of judging virtual Link layer output is test packet, this message is sent to the virtual network port Drive Layer; Otherwise, send to true network port driving layer, by true network port driving layer this message is sent to miscellaneous equipment or system by network.Like this, in the process of test cpu performance, system still can send message to miscellaneous equipment or system.
Here it is pointed out that and judge that whether message is that the step of test packet is not necessary.For example, the tester can be configured before test---network port driving layer is configured to the virtual network port Drive Layer.Like this, all messages all arrive the virtual network port Drive Layer through after the data link layer, and whether needn't distinguish is test packet again, and decision is to the virtual network port Drive Layer or true network port driving layer sends.
S805, message return after arriving the virtual network port Drive Layer.
The packet buffer that the virtual network port Drive Layer will receive from data link layer is after formation, the message in the formation is not sent by hardware device (as network interface card etc.), but activate the receiving interface thread, by the receiving interface thread message in the formation is returned to the upper strata.
S806, message return through virtual Link layer, Port layer, Socket layer.
S807, according to the transmitting time and the return time of message, determine the time of delay of returning of message, thereby determine the performance of CPU.
After message returns from the Socket layer, according to the transmitting time and the return time of message, determine the time of delay of returning of message, thereby determine the performance of CPU.
In order to obtain test result more accurately, can add up the time of delay of returning of a large amount of messages, thereby determine the performance of the CPU of this built-in network system.For example, when the message of adding up on average returns time of delay greater than set point B, then determine the poor-performing of CPU; Perhaps, rule of thumb formulate one and return the time of delay and the cpu performance grade table of comparisons, on average return time of delay, determine corresponding cpu performance grade according to the message of testing.
The processor performance test device of a kind of built-in network system that the embodiment of the invention provides, as shown in Figure 9, comprising: message sending module 901, socket layer module 902, port layer module 903, virtual link layer module 904, the first network port driving layer module 905, message receiver module 906, processor performance determination module 907.
After 902 pairs of messages that receive from message sending module 901 of socket layer module are made the respective handling of Socket layer, send this message to port layer module 903.
Virtual link layer module 904 done this message to send these messages to the first network port driving layer module 905 after the respective handling of virtual link layer after receiving the message that port layer module 903 sends.
The first network port driving layer module 905 in formation, and activates the receiving interface thread with described packet buffer after receiving the message that virtual link layer module 904 send; The receiving interface thread returns the message in the formation to virtual link layer module 904.
Virtual link layer module 904 receives to be made corresponding virtual link layer behind the message that the first network port driving layer module 905 returns and handles, and returns this message to port layer module 903.
The message that processor performance determination module 907 is received according to message receiver module 906 return time of delay, determine performance of processors.The time that to be processor performance determination module 907 receive returned packet according to the transmitting time and the message receiver module 906 of this message is determined the time of delay of returning of message, and then definite performance of processors.
Further, described device also comprises:
Test packet determination module 908 judges whether the message that virtual link layer module 904 sends to the first network port driving layer module 905 is test packet between the first network port driving layer module 905 and virtual link layer module 904; If then this message is forwarded to the first network port driving layer module 905; Otherwise, this message is forwarded to the second network port driving layer module, 909, the second network port driving layer modules, the 909 driving network hardwares this message is sent to network.
Further, port layer module 903 also is used for still this message being sent to described virtual link layer module after definite message that receives from transport layer is the winding message.
The embodiment of the invention is owing to import message from the Socket layer, arrive the virtual network port Drive Layer through Port layer, virtual link layer, return this message by the virtual network port Drive Layer again through virtual link layer, Port layer, Socket layer, thereby according to the performance of determining CPU time of delay of returning of message.Like this, message is after having passed through whole transmission, receiving course, and returning of message directly reflected the performance of CPU to the whole process of message processing time of delay.
Because input and reception message more than the Socket layer, I/O that needn't calling system reads the message that handle in intermediate layer (as Socket layer, Port layer etc.), thereby reduced the number of times to the I/O visit, the test of having avoided the I/O visit to cause postpones, and makes test result more accurate.
One of ordinary skill in the art will appreciate that all or part of step that realizes in the foregoing description method is to instruct relevant hardware to finish by program, this program can be stored in the computer read/write memory medium, as: ROM/RAM, magnetic disc, CD etc.
Will also be appreciated that the apparatus structure shown in accompanying drawing or the embodiment only is schematically, the presentation logic structure.Wherein the module that shows as separating component may or may not be physically to separate, and the parts that show as module may be or may not be physical modules.
The above only is a preferred implementation of the present invention; should be pointed out that for those skilled in the art, under the prerequisite that does not break away from the principle of the invention; can also make some improvements and modifications, these improvements and modifications also should be considered as protection scope of the present invention.
Claims (12)
1, a kind of processor performance test method of embedded system is characterized in that, comprising:
Message is imported from transport layer, through network layer, data link layer output;
When the message of confirming the output of described data link layer is test packet, this message is sent to first network port driving layer;
After described first network port driving layer receives message, described packet buffer in formation, and is returned the message in the formation through described data link layer, network layer, transport layer;
Determine described performance of processors time of delay according to returning of the message that returns.
2, the method for claim 1 is characterized in that, described test packet is the winding message; And described network layer is sent to described data link layer with this winding message after determining to receive the winding message from described transport layer.
3, a kind of processor performance test method of embedded system is characterized in that, comprising:
Message is imported from transport layer, outputed to first network port driving layer through network layer, data link layer;
After described first network port driving layer receives message, described packet buffer in formation, and is returned the message in the formation through described data link layer, network layer, transport layer;
Determine described performance of processors time of delay according to returning of the message that returns.
4, a kind of processor performance test device of embedded system comprises: transport layer module, network layer module, data link layer module, it is characterized in that, and also comprise:
The message sending module is used for message is sent to described transport layer module;
The first network port driving layer module is used to receive the message of input, and described packet buffer in formation, and is returned the message in the formation; The message of described input is a message that described message sending module sends, arrive the first network port driving layer module after transport layer module, network layer module, data link layer resume module;
The message receiver module is used to receive the message that returns; The described message that returns is a message that the described first network port driving layer module is returned, arrive described message receiver module after data link layer module, network layer module, transport layer module are handled;
The processor performance determination module is used for time of delay of returning of the message that receives according to described message receiver module, determines described performance of processors.
5, device as claimed in claim 4 is characterized in that, also comprises:
The test packet determination module is used to receive the message after described transport layer module, network layer module, data link layer resume module, and when determining that the message that receives is test packet, described message is transmitted to the described first network port driving layer module.
6, device as claimed in claim 5 is characterized in that, described test packet is the winding message; And
Described network layer module specifically is used for after definite message that receives from transport layer is the winding message this winding message being sent to described data link layer module.
7, a kind of processor performance test method of embedded system is characterized in that, comprising:
Message from the input of socket Socket layer, is exported through port Port layer, virtual link layer;
When the message of confirming the output of described virtual link layer is test packet, this message is sent to first network port driving layer;
After described first network port driving layer receives message, described packet buffer in formation, and with the message in the formation, is returned through described virtual link layer, Port layer, Socket layer;
Determine described performance of processors time of delay according to returning of the message that returns.
8, method as claimed in claim 7 is characterized in that, described test packet is the winding message; And described Port layer is sent to described virtual link layer with this winding message after determining to receive the winding message from described transport layer.
9, a kind of processor performance test method of embedded system is characterized in that, comprising:
Message from the input of socket Socket layer, is outputed to first network port driving layer through port Port layer, virtual link layer;
After described first network port driving layer receives message, described packet buffer in formation, and with the message in the formation, is returned through described virtual link layer, Port layer, Socket layer;
Determine described performance of processors time of delay according to returning of the message that returns.
10, a kind of processor performance test device of embedded system comprises: socket layer module, port layer module, virtual link layer module, it is characterized in that, and also comprise:
The message sending module is used for message is sent to described socket layer module;
The first network port driving layer module is used to receive the message of input, and described packet buffer in formation, and is returned the message in the formation; The message of described input is a message that described message sending module sends, arrive the first network port driving layer module after socket layer module, port layer module, virtual link layer resume module;
The message receiver module is used to receive the message that returns; The described message that returns is a message that the described first network port driving layer module is returned, arrive described message receiver module after virtual link layer module, port layer module, socket layer resume module;
The processor performance determination module is used for time of delay of returning of the message that receives according to described message receiver module, determines described performance of processors.
11, device as claimed in claim 10 is characterized in that, also comprises:
The test packet determination module is used to receive the message after described socket layer module, port layer module, virtual link layer resume module, and when determining that the message that receives is test packet, described message is transmitted to the described first network port driving layer module.
12, device as claimed in claim 11 is characterized in that, described test packet is the winding message; And
Described port layer module specifically is used for after definite message that receives from socket layer is the winding message this winding message being sent to described virtual link layer module.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2008101845387A CN101420341B (en) | 2008-12-08 | 2008-12-08 | Processor performance test method and device for embedded system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2008101845387A CN101420341B (en) | 2008-12-08 | 2008-12-08 | Processor performance test method and device for embedded system |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101420341A true CN101420341A (en) | 2009-04-29 |
| CN101420341B CN101420341B (en) | 2011-01-05 |
Family
ID=40630960
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2008101845387A Expired - Fee Related CN101420341B (en) | 2008-12-08 | 2008-12-08 | Processor performance test method and device for embedded system |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101420341B (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2010145091A1 (en) * | 2009-06-29 | 2010-12-23 | 中兴通讯股份有限公司 | Method for implementing virtual network port and embedded device for implementing virtual network port |
| CN103236955A (en) * | 2013-04-08 | 2013-08-07 | 汉柏科技有限公司 | Method for testing network equipment performance based on software |
| CN110881009A (en) * | 2018-09-06 | 2020-03-13 | 迈普通信技术股份有限公司 | Method, device, communication equipment and storage medium for receiving test message |
| CN111541583A (en) * | 2020-04-20 | 2020-08-14 | 杭州迪普信息技术有限公司 | System, method and device for testing fragment message cache |
| CN114448916A (en) * | 2021-12-24 | 2022-05-06 | 锐捷网络股份有限公司 | TIPC message processing method, device, equipment and storage medium |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8601566B2 (en) * | 2001-10-23 | 2013-12-03 | Intel Corporation | Mechanism supporting wired and wireless methods for client and server side authentication |
| US7394769B2 (en) * | 2003-08-14 | 2008-07-01 | International Business Machines Corporation | Method, system and article for rapid detection and avoidance of high data corrupting routes within a network |
| US20050213507A1 (en) * | 2004-03-25 | 2005-09-29 | International Business Machines Corporation | Dynamically provisioning computer system resources |
| GB2415319B (en) * | 2004-06-19 | 2006-11-29 | Agilent Technologies Inc | Method of generating a monitoring datagram |
| CN100495985C (en) * | 2005-06-22 | 2009-06-03 | 中国长城计算机深圳股份有限公司 | Method for rapidly detecting Ethernet exchanger loop failure |
| CN100568994C (en) * | 2006-03-09 | 2009-12-09 | 中兴通讯股份有限公司 | A kind of protocol software testing system and method |
-
2008
- 2008-12-08 CN CN2008101845387A patent/CN101420341B/en not_active Expired - Fee Related
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2010145091A1 (en) * | 2009-06-29 | 2010-12-23 | 中兴通讯股份有限公司 | Method for implementing virtual network port and embedded device for implementing virtual network port |
| CN101616088B (en) * | 2009-06-29 | 2011-12-07 | 中兴通讯股份有限公司 | Method for realizing virtual network port and embedded equipment for realizing virtual network port |
| US9240899B2 (en) | 2009-06-29 | 2016-01-19 | Zte Corporation | Method for implementing virtual network port and embedded device for implementing virtual network port |
| CN103236955A (en) * | 2013-04-08 | 2013-08-07 | 汉柏科技有限公司 | Method for testing network equipment performance based on software |
| CN103236955B (en) * | 2013-04-08 | 2016-08-31 | 汉柏科技有限公司 | The method realizing network apparatus test performance based on software |
| CN110881009A (en) * | 2018-09-06 | 2020-03-13 | 迈普通信技术股份有限公司 | Method, device, communication equipment and storage medium for receiving test message |
| CN111541583A (en) * | 2020-04-20 | 2020-08-14 | 杭州迪普信息技术有限公司 | System, method and device for testing fragment message cache |
| CN114448916A (en) * | 2021-12-24 | 2022-05-06 | 锐捷网络股份有限公司 | TIPC message processing method, device, equipment and storage medium |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101420341B (en) | 2011-01-05 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8937949B2 (en) | Method and system for Infiniband host channel adapter multicast packet replication mechanism | |
| CN108268328B (en) | Data processing device and computer | |
| CN101420341B (en) | Processor performance test method and device for embedded system | |
| CN102648455A (en) | Server and flow control program | |
| US20090213735A1 (en) | System to improve data packet routing in a data processing device and associated methods | |
| CN109075996B (en) | Monitoring controller for monitoring network performance and method performed thereby | |
| JPH04328926A (en) | Method and device for testing and evaluating dynamic functional operation of regionally dispersed communication network | |
| US10873532B2 (en) | Flow control visibility | |
| CN110505168B (en) | NI interface controller and data transmission method | |
| CN113141288B (en) | Mailbox message receiving and sending method and device of CAN bus controller | |
| CN115361348B (en) | Method for communicating with web browser performed by data acquisition device | |
| CN108984324B (en) | FPGA hardware abstraction layer | |
| US6862647B1 (en) | System and method for analyzing bus transactions | |
| CN111756588A (en) | Communication link detection method and related device | |
| US10129147B2 (en) | Network-on-chip flit transmission method and apparatus | |
| CN103973518A (en) | Method and device for detecting virtual local area network by adopting packet internet grope | |
| CN105763347A (en) | Method for obtaining parameter, network equipment and system | |
| CN116306407B (en) | Verification method, device, equipment and storage medium of Network On Chip (NOC) | |
| CN106230726A (en) | The detection method of forward-path and device | |
| CN112131154A (en) | DMA transmission control method for dynamically matching channel and service | |
| CN106598756B (en) | Data interaction method between different application programs | |
| CN113949706B (en) | Method and system for selecting mobile edge computing node | |
| CN114567679B (en) | Data transmission method and device | |
| KR100557077B1 (en) | Interprocessor communication performance test method and apparatus | |
| KR101378298B1 (en) | configuration memory apparatus and router system using the same in FPGA |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| ASS | Succession or assignment of patent right |
Owner name: PU NING Free format text: FORMER OWNER: FUJIAN XINGWANGRUIJIE NETWORK CO., LTD. Effective date: 20140530 |
|
| C41 | Transfer of patent application or patent right or utility model | ||
| COR | Change of bibliographic data |
Free format text: CORRECT: ADDRESS; FROM: 350015 FUZHOU, FUJIAN PROVINCE TO: 518052 SHENZHEN, GUANGDONG PROVINCE |
|
| TR01 | Transfer of patent right |
Effective date of registration: 20140530 Address after: 518052 Guangdong city of Shenzhen province Nanshan District Nanshan digital and cultural industry base east tower room 407 Patentee after: Pu Ning Address before: 350015 M9511 Industrial Park, fast road, Mawei District, Fujian, Fuzhou Patentee before: Fujian Xingwangruijie Network Co., Ltd. |
|
| ASS | Succession or assignment of patent right |
Owner name: STATE GRID CORPORATION OF CHINA Free format text: FORMER OWNER: PU NING Effective date: 20141010 Owner name: STATE GRID ZHEJIANG ELECTRIC POWER COMPANY SHAOXIN Effective date: 20141010 |
|
| C41 | Transfer of patent application or patent right or utility model | ||
| COR | Change of bibliographic data |
Free format text: CORRECT: ADDRESS; FROM: 518052 SHENZHEN, GUANGDONG PROVINCE TO: 100031 XICHENG, BEIJING |
|
| TR01 | Transfer of patent right |
Effective date of registration: 20141010 Address after: 100031 Xicheng District West Chang'an Avenue, No. 86, Beijing Patentee after: State Grid Corporation of China Patentee after: State Grid Zhejiang Electric Power Company Patentee after: Shaoxing Power Supply Company of State Grid Zhejiang Electric Power Company Patentee after: State Grid Zhejiang Zhuji Power Supply Co., Ltd. Patentee after: Zhuji Dongbai Electric Power Equipment Manufacturing Co., Ltd. Address before: 518052 Guangdong city of Shenzhen province Nanshan District Nanshan digital and cultural industry base east tower room 407 Patentee before: Pu Ning |
|
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20110105 Termination date: 20171208 |