CN101419407B - Stacked photolithography alignment mark - Google Patents
Stacked photolithography alignment mark Download PDFInfo
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- CN101419407B CN101419407B CN200710047360A CN200710047360A CN101419407B CN 101419407 B CN101419407 B CN 101419407B CN 200710047360 A CN200710047360 A CN 200710047360A CN 200710047360 A CN200710047360 A CN 200710047360A CN 101419407 B CN101419407 B CN 101419407B
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Abstract
The invention relates to a stackable photo-etching alignment mark, consisting of a plurality of metal layers and through-hole layers which are arranged in an intersected way. In two adjacent metal layers, the position of metal (1) in the aligning unit of the first metal layer (201) changes into oxide (2) in the second layer (203); the position of the oxide (2) in the first metal layer (201) changes into the metal (1) in the second layer (203); and the middle part of the aligning unit of each metal layer is the oxide (2). The photo-etching alignment mark can greatly save space on a cutting track.
Description
Technical field
The present invention relates to a kind of photoetching alignment mark, relate in particular to a kind of stacked photolithography alignment mark.
Background technology
Piling up as shown in Figure 1 of existing photoetching alignment mark, having a plurality of metal levels (101,103,105......) and a plurality of via layer (102,104......) to intersect to pile up forms, in the existing metal level, the aligned units of each layer is all just the same, promptly in same position, all be 1 metal, or all be 2 oxides.And in the lamination process of existing photoetching alignment mark, the different aspects of same position can not all be placed aligning (alignment mark) unit, all must stagger mutually in the position of each layer aligned units.For example under the existing SPM that in example of the present invention, is given an example (scribe-lane primary mark) the photoetching alignment mark design rule, in each metal level on its horizontal direction of aligned units occupation space be 800um * 80um, occupation space is 80um * 800um on the vertical direction, be superimposed and on Cutting Road (scribe-lane), always have 10 to 12 group for photo etching alignment marks, like this no matter on level or vertical direction, all will take the width of 8mm-9mm, so just taken the space on the too many Cutting Road, there are not enough spaces to place WAT (wafer acceptance test with regard to having caused, the electric parameter detecting of wafer) test circuit, testing electrical property circuit such as RE (Reliability test, reliability testing) test circuit etc.
Summary of the invention
Technical matters to be solved by this invention has provided a kind of stacked photolithography alignment mark, can save the space on the Cutting Road greatly.
A kind of stacked photolithography alignment mark, a plurality of metal levels and via layer cross arrangement; In adjacent two metal levels, being the place of metal in the aligned units of the first metal layer, becoming oxide in second metal level, is the place of oxide in the first metal layer, is metal in the second layer; The center section of the aligned units in each metal level all is an oxide.
Wherein above-mentioned a kind of stacked photolithography alignment mark comprises the first metal layer, second metal level, and the 3rd metal level, wherein between the first metal layer and second metal level, all be via layer between second metal level and the 3rd metal level.
The present invention is owing to adopt the stack aligned units in photoetching alignment mark, making it to misplace just can be stacked, and so just can save the space on the Cutting Road greatly.
Description of drawings
Fig. 1 is the synoptic diagram of existing SPM (scribe-lane primary mark) photoetching alignment mark;
Fig. 2 is the synoptic diagram of stacked photolithography alignment mark of the present invention;
Fig. 3 is aligned units synoptic diagram in the stacked photolithography alignment mark of the present invention;
Fig. 4 is stacked photolithography alignment mark stack synoptic diagram of the present invention.
Embodiment
The present invention as shown in Figure 2, photoetching alignment mark the first metal layer 201, the 3rd metal level 205 is the same with original metal level, do not do any change, promptly 1 remain metal, 2 remain oxide, second metal level 203 has then been made great change, it promptly in the aligned units of the first metal layer the place of metal, in the aligned units of second metal level 203, be oxide, it in the aligned units of the first metal layer the place of oxide, in the aligned units of second metal level 203, be metal, and guarantee that the center section of aligned units in second metal level 203 remains oxide, as shown in Figure 3.And 202,204 remain via layer, promptly via layer still with the metal level cross arrangement.The stacked photolithography alignment mark generally is stacked by 3 to 12 metal levels and via layer intersection, as shown in Figure 2.
And this stacked photolithography alignment mark is because the metal in the adjacent metal layer and the location swap of oxide, so need not stagger mutually, just can directly be stacked, so not only can realize the function of aiming at but also can save space on the Cutting Road.
Below in conjunction with a specific embodiment stacked photolithography alignment mark of the present invention is made a detailed explanation, as shown in Figure 2: the aligned units of the first metal layer 201 and the 3rd metal level 205 is identical, with the aligned units of original metal level is the same, and in the aligned units of second metal level 203, the position of metal and oxide just with the first metal layer 201, the metal in the aligned units of the 3rd metal level 205 and the position opposite of oxide, and the centre position that guarantees the aligned units of second metal level 203 remains oxide, wherein three stacks of metal layers gather into folds as shown in Figure 4, and 301 centre positions still guarantee to be oxide.And between the first metal layer 201 and second metal level 203 is via hole, also is via hole between second metal level 203 and the 3rd metal level 205.
Three metal levels like this can stagger, and just can directly be stacked, and can play good alignment result.
We can draw by a large amount of experimental analyses, and when three stacks of metal layers stacked, its alignment result can be best.
Present embodiment is a specific embodiment of the present invention, for the stacked photolithography alignment mark in the copper-connection processing procedure is used.Metal level and via layer among the present invention can be 3 to 12 layers, and via layer and metal level cross arrangement.In aluminium interconnection processing procedure, photoetching alignment mark also can be placed on the via layer, and it piles up principle and present embodiment is identical.
The original photoetching alignment mark of giving an example among the present invention also is a kind of specific embodiment, and the present invention can be applied to various photoetching alignment mark of putting on Cutting Road.
Stacked photolithography alignment mark of the present invention can be saved the space on the Cutting Road greatly, just can reserve more space and put other testing element.
Claims (2)
1. stacked photolithography alignment mark, by a plurality of metal levels and via layer cross arrangement, it is characterized in that, in the adjacent metal layer, be the place of metal (1) in the aligned units of the first metal layer (201), becoming oxide (2) in second metal level (203), is the place of oxide (2) in the first metal layer (201), is metal (1) in the second layer (203);
The center section of the aligned units in each metal level all is an oxide (2).
2. a kind of stacked photolithography alignment mark as claimed in claim 1, it is characterized in that described photoetching alignment mark comprises the first metal layer (201), second metal level (203), the 3rd metal level (205), wherein between the first metal layer (201) and second metal level (203), all be via layer between second metal level (203) and the 3rd metal level (205).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200710047360A CN101419407B (en) | 2007-10-24 | 2007-10-24 | Stacked photolithography alignment mark |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200710047360A CN101419407B (en) | 2007-10-24 | 2007-10-24 | Stacked photolithography alignment mark |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101419407A CN101419407A (en) | 2009-04-29 |
| CN101419407B true CN101419407B (en) | 2010-05-19 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN200710047360A Active CN101419407B (en) | 2007-10-24 | 2007-10-24 | Stacked photolithography alignment mark |
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Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103426811B (en) * | 2012-05-15 | 2016-02-17 | 无锡华润上华科技有限公司 | Method, semi-conductor device manufacturing method and semiconductor device |
| CN104952851B (en) * | 2014-03-28 | 2017-11-14 | 中芯国际集成电路制造(上海)有限公司 | Alignment mark and its alignment methods |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6146969A (en) * | 1999-01-19 | 2000-11-14 | Chartered Semiconductor Manufacturing Ltd. | Printing optimized global alignment mark at contact/via layers |
| CN1458667A (en) * | 2002-05-17 | 2003-11-26 | 台湾积体电路制造股份有限公司 | Method for producing alignment mark |
| CN1932653A (en) * | 2005-09-15 | 2007-03-21 | 联华电子股份有限公司 | Stack type alignment mark and photoetching process aligning method |
| CN1936710A (en) * | 2006-10-18 | 2007-03-28 | 上海微电子装备有限公司 | Alignment mark and its producing method |
-
2007
- 2007-10-24 CN CN200710047360A patent/CN101419407B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6146969A (en) * | 1999-01-19 | 2000-11-14 | Chartered Semiconductor Manufacturing Ltd. | Printing optimized global alignment mark at contact/via layers |
| CN1458667A (en) * | 2002-05-17 | 2003-11-26 | 台湾积体电路制造股份有限公司 | Method for producing alignment mark |
| CN1932653A (en) * | 2005-09-15 | 2007-03-21 | 联华电子股份有限公司 | Stack type alignment mark and photoetching process aligning method |
| CN1936710A (en) * | 2006-10-18 | 2007-03-28 | 上海微电子装备有限公司 | Alignment mark and its producing method |
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| Publication number | Publication date |
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| CN101419407A (en) | 2009-04-29 |
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Owner name: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING |
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Effective date of registration: 20111115 Address after: 201203 No. 18 Zhangjiang Road, Shanghai Co-patentee after: Semiconductor Manufacturing International (Beijing) Corporation Patentee after: Semiconductor Manufacturing International (Shanghai) Corporation Address before: 201203 No. 18 Zhangjiang Road, Shanghai Patentee before: Semiconductor Manufacturing International (Shanghai) Corporation |