CN101414810A - Transistor resistance and correlation method - Google Patents
Transistor resistance and correlation method Download PDFInfo
- Publication number
- CN101414810A CN101414810A CNA2007101802601A CN200710180260A CN101414810A CN 101414810 A CN101414810 A CN 101414810A CN A2007101802601 A CNA2007101802601 A CN A2007101802601A CN 200710180260 A CN200710180260 A CN 200710180260A CN 101414810 A CN101414810 A CN 101414810A
- Authority
- CN
- China
- Prior art keywords
- transistor
- resistance
- signal
- grid
- compensating
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Landscapes
- Amplifiers (AREA)
Abstract
The invention relates to a transistor resistance and a correlation method thereof. A transistor is operated in a resistance area, and the drain electrode of the transistor receives an input signal and the source electrode of the transistor outputs an output signal, and then a compensating circuit is used for generating a compensating signal which is sent into the grid electrode of the transistor according to the input signal, thus leading the voltage difference between the grid electrode and the source electrode of the transistor to approach a constant, so as to improve the resistance linearity of the transistor resistance.
Description
Technical field
The present invention relates to a kind of resistance device, raising relates to a kind of transistor resistance devices and methods therefor.
Background technology
Integrated circuit (integrated circuit, IC) in, usually need to use resistance, and conventional semiconductor technology provides multiple reality to make the mode of resistance.For example, CMOS (Complementary Metal Oxide Semiconductor) (complimentary metal oxide semiconductor in standard, CMOS) in the technology, provide following several resistance: silicification polysilicon (silicided polysilicon), silication p+ or n+ active region (active region), n type well (n well) and metal level (metal layer) etc., wherein, unit area resistance value with n type well is the highest, approximately is 1k ohm/square.Yet, in some circuit, need use very large resistance value, as the three dB bandwidth firstorder filter that is 100kHz, if its capacitance is 10pF, the about 160k ohm of its required resistance value then, even use the resistance of n type well, still can take the very large area of IC.This stresses little, the component density Gao Eryan of size for IC now, can cause puzzlement very big in the design.
Therefore, some IC designer can operate in MOS transistor resistance area (resistive region is called triode region (triode region) again), uses to be used as resistance.So, though can obtain very large unit area resistance value, its very big shortcoming is that resistance value can change along with input signal, that is the linearity (linearity) is very poor.
Summary of the invention
In view of this, a purpose of the present invention is to provide a kind of transistor resistance and method thereof, and this transistor resistance has the resistance linearity preferably.
Another object of the present invention is to provide a kind of transistor resistance and method thereof, and this transistor resistance can provide big resistance value.
Another object of the present invention is to provide a kind of transistor resistance and method thereof, and this transistor resistance of this transistor resistance has preferably the resistance linearity and big resistance value can be provided.
According to one embodiment of the invention, it discloses a kind of transistor resistance, comprise: a first transistor, operate in resistance area (resistive region), the drain electrode of this first transistor and source electrode are respectively applied for and receive one first input signal and output one first output signal; And a compensating circuit, be used for producing one first compensating signal according to this first input signal, send into a grid of this first transistor, so that the voltage difference between this grid of this first transistor and this source electrode is near a constant.
According to one embodiment of the invention, it discloses a kind of method that improves the linearity of transistor resistance, comprise: a first transistor that operates in resistance area (resistive region) is provided, wherein, one of this first transistor drain electrode is respectively applied for one source pole and receives an input signal and output one output signal; And produce a compensating signal according to this input signal, send into a grid of this first transistor, so that the voltage difference between this grid and this source electrode is near a constant.
Description of drawings
Figure 1A is the schematic diagram of an embodiment of MOS transistor resistance of the present invention.
Figure 1B is the circuit diagram of an embodiment of the bias circuit of Figure 1A.
Fig. 2 is the schematic diagram that MOS transistor resistance of the present invention is used for an embodiment of differential configuration.
Fig. 3 is the schematic diagram of a preferred embodiment of MOS transistor resistance of the present invention.
Fig. 4 is the schematic diagram of another preferred embodiment of MOS transistor resistance of the present invention.
Fig. 5 is the flow chart according to a preferred embodiment of the linearity modification method of the MOS transistor resistance shown in the present invention.
The reference numeral explanation:
10,20,30,40: transistor resistance
11,21a, 21b, 31,34,41a, 41b, 44a, 44b:NMOS transistor
12,32: compensating circuit 13,23a, 23b: bias circuit
131:PMOS transistor 132: current source
22,42: differential amplifier 33,43a, 43b: the bias circuit of transduceing surely
51-53: a preferred embodiment flow process of the linearity modification method of transistor resistance.
Embodiment
This specification is to be example with the MOS transistor, so not as limit.Figure 1A is the schematic diagram of an embodiment of transistor resistance of the present invention.Among the figure, transistor resistance 10 comprises a nmos pass transistor 11, a compensating circuit 12 and a bias circuit 13.Nmos pass transistor 11 operates in resistance area, that is its grid is to source voltage v
GSNeed greater than critical voltage (threshold vol tage) V
T, and drain electrode is to source voltage v
DSNeed less.When nmos pass transistor 11 operates in resistance area, have a current i
DFlow into from its drain electrode, and flow out from source electrode, and i
DWith v
DSBetween relation be
i
D=2K (v
GS-V
T) v
DSFormula (1)
Wherein,
μ
nWith C
OxBe the parameter relevant with material, W and L are respectively the width and the length of grid.Can push away to such an extent that the resistance value of nmos pass transistor 11 is by formula (1)
R
MOS=v
DS/ i
D=1/[2K (v
GS-V
T)] formula (2)
Shown in Figure 1A, bias circuit 13 provides a grid that is biased into transistor 11, makes transistor 11 operate in resistance area.When the drain electrode of transistor 11 received an input signal, the output signal of source electrode can be made synchronous change with this input signal, shown in the signal waveform among the figure (in the present embodiment, input is all voltage signal with output signal).Yet, by formula (2) as can be known, the resistance value R of transistor 11
MOSCan be along with v
GSAnd become.Therefore, constant if grid voltage is maintained at the bias voltage that bias circuit 13 provided, v
GSJust can float along with the change of output signal, cause R
MOSChange.In the present embodiment, the purpose of compensating circuit 12 promptly is according to input signal, produces the compensating signal with input signal same-phase (thereby also with output signal same-phase), adds to the grid of transistor 11, so that v
GSNear a constant.So, just, can make R
MOSNear definite value, and improve the resistance linearity.The signal gain of compensating circuit 12 note that as long as can make compensating signal have the v of making
GSNear the effect of constant, just can utilize the real compensating circuit 12 of doing of any way, such as but not limited to: general non-inverting amplifier (non-inverting amplifier).
Figure 1B is the circuit diagram of an embodiment of bias circuit 13.Among the figure, bias circuit 13 comprises the PMOS transistor 131 and a current source 132 of a diode type of attachment (diode connected).The source electrode of transistor 131, grid and drain electrode are coupled to a voltage source V respectively
DD, transistor 11 grid and current source 132.And the diode type of attachment, be that the grid of transistor 131 is coupled mutually with drain electrode, so can make transistor 131 fixing operations in the saturation region (saturation region, be called again and decide Current Zone (constant-current region)), also can make the grid voltage of transistor 131 not locked, and can cooperate the adding of compensating signal and change.
Fig. 2 is the schematic diagram that transistor resistance of the present invention is used for an embodiment of differential configuration (differential configuration).Among the figure, transistor resistance 20 comprises nmos pass transistor 21a and 21b, a differential amplifier (differential amplifier) 22 and bias circuit 23a and 23b.Transistor 21a and 21b all operate in resistance area, and its resistance value satisfies aforesaid formula (2).Bias circuit 23a and 23b provide a grid that is biased into transistor 21a and 21b respectively, make transistor 21a and 21b operate in resistance area.The drain electrode of transistor 21a and 21b receives first and second input signal respectively, wherein, second input signal is an inversion signal of first input signal, and the source electrode of transistor 21a and 21b respectively output first and second output signal can make synchronous change with first and second input signal, shown in the signal waveform among Fig. 2 (in the present embodiment, all inputs are all voltage signal with output signal).In the present embodiment, be with differential amplifier 22 circuit by way of compensation, with according to first and second input signal, produce respectively and synchronous first, second compensating signal of first, second output signal, add to the grid of transistor 21a and 21b respectively, so that the v of transistor 21a and 21b
GSAll can be near constant, and the resistance value that makes transistor 21a and 21b is near definite value.
Fig. 3 is the schematic diagram of a preferred embodiment of transistor resistance of the present invention.Among the figure, transistor resistance 30 comprises nmos pass transistor 31 and 34, a compensating circuit 32 and certain transduction bias voltage (constanttransconductance bias, or title constant-g
mBias) circuit 33. Transistor 31 and 34 operates in resistance area and saturation region respectively.Because transistor 34 operates in the saturation region, its drain current can be expressed as
I
D＝K(V
GS-V
T)
2
Therefore, the transduction value of transistor 34 is
Because the grid of transistor 31 and 34 joins and source electrode joins, therefore, both V
GSEquate.And in this preferred embodiment, nmos pass transistor 31 is to be designed to have the identical width of essence to the length ratio with 34 grid, and is positioned on the same integrated circuit (IC), thereby has identical K value and V
TValue.Under these conditions, can be pushed away by formula (2) and formula (3), the resistance value of transistor 31 is the inverse of the transduction value of transistor 34.
Surely the bias circuit 33 of transduceing can provide a bias current to transistor 34, so that the transduction value of transistor 34 is not subjected to temperature, element technology and the influence of the required factors such as voltage source of bias circuit 33 runnings of transduceing surely.And because the resistance value of transistor 31 is inverses of the transduction value of transistor 34, so the resistance value of transistor 31 also can not be subjected to the influence of aforementioned factor, and more increase its reliability.Surely the bias voltage skill of transduceing is that tool knows that usually the knowledgeable institute is known in the technical field of the invention, does not just give unnecessary details herein.
Fig. 4 shows another preferred embodiment of transistor resistance of the present invention, and it is that preferred embodiment with Fig. 3 is applied to differential configuration.As shown in Figure 4, transistor resistance 40 comprises transistor 41a, 41b, 44a and 44b, a differential amplifier 42 and transduce surely bias circuit 43a and 43b.Transistor 41a and 41b operate in resistance area, and transistor 44a and 44b operate in the saturation region.And based on aforesaid derivation, the resistance value of transistor 41a and 41b is respectively the inverse of the transduction value of transistor 44a and 44b as can be known.In this preferred embodiment, be with differential amplifier 42 circuit by way of compensation, with according to first and second input signal (both are anti-phase each other), produce respectively and synchronous first, second compensating signal of first, second output signal, add to the grid of transistor 41a and 41b respectively, so that the v of transistor 41a and 41b
GSAll can be near constant, and the resistance value that makes transistor 41a and 41b is near definite value.Moreover, surely transduce bias circuit 43a and 43b can make the transduction value of transistor 44a and 44b not be subjected to the influence of the factors such as voltage source of temperature, element technology and bias circuit respectively, the related resistance value of transistor 41a and 41b that makes also can not be subjected to the influence of these factors, and more increases reliability.
In aforementioned 1A, 2,3,4 figure, also can be without nmos pass transistor, and implement MOS transistor resistance of the present invention with the PMOS transistor.This be in the technical field of the invention tool know usually that the knowledgeable can think easily and, just seldom narration herein.
Fig. 5 is the flow chart according to a preferred embodiment of the linearity modification method of the MOS transistor resistance shown in the present invention.As shown in the figure, this flow process comprises the following step:
Step 51: first MOS transistor that operates in resistance area is provided, and wherein, the drain electrode of this first MOS transistor and source electrode are respectively applied for and receive an input signal and output one output signal;
Step 52: the 3rd MOS transistor that operates in the saturation region is provided, and wherein, the grid of the 3rd MOS transistor and source electrode couple mutually with the grid and the source electrode of first MOS transistor respectively; And
Step 53: produce a compensating signal according to this input signal, send into the grid of first MOS transistor, so that the grid of first MOS transistor and the voltage difference between source electrode are near a constant.
The above is to utilize preferred embodiment to describe the present invention in detail, but not limits the scope of the invention.Generally know this type of skill personage and all can understand, suitably do slightly change and adjustment, will not lose main idea of the present invention place, also do not break away from the spirit and scope of the present invention.
Claims (18)
1. transistor resistance comprises:
One the first transistor operates in resistance area, and the drain electrode of this first transistor and source electrode are respectively applied for and receive one first input signal and output one first output signal; And
One compensating circuit is used for producing one first compensating signal according to this first input signal, sends into the grid of this first transistor, so that the voltage difference between this grid of this first transistor and this source electrode is near a constant.
2. transistor resistance as claimed in claim 1, wherein, the change of this first compensating signal is corresponding with the change of this first output signal.
3. transistor resistance as claimed in claim 2, wherein, this first compensating signal and this first output signal are synchronous voltage signals.
4. transistor resistance as claimed in claim 1 more comprises:
One bias circuit is used for this first transistor is carried out bias voltage.
5. transistor resistance as claimed in claim 4, wherein, this bias circuit comprises the transistor of a diode type of attachment that is coupled to this first transistor.
6. transistor resistance as claimed in claim 1 more comprises:
One transistor seconds operates in resistance area, and the drain electrode of this transistor seconds and source electrode are respectively applied for and receive one second input signal and output one second output signal, and wherein, this second input signal is an inversion signal of this first input signal.
7. transistor resistance as claimed in claim 6, wherein, this compensating circuit produces this first compensating signal and one second compensating signal according to this first input signal and this second input signal, wherein, this second compensating signal is an inversion signal of this first compensating signal, and be admitted to the grid of this transistor seconds, so that the voltage difference between this grid of this transistor seconds and this source electrode is near a constant.
8. transistor resistance as claimed in claim 7, wherein, this compensating circuit is a differential amplifier.
9. transistor resistance as claimed in claim 1 more comprises:
One transistor seconds operates in the saturation region, and the grid of this transistor seconds and source electrode couple mutually with this grid and this source electrode of this first transistor respectively.
10. transistor resistance as claimed in claim 9, wherein, this first and second transistor is on same integrated circuit.
11. transistor resistance as claimed in claim 9, wherein, this first and second transistorized grid has the identical width of essence to the length ratio.
12. transistor resistance as claimed in claim 9 more comprises:
Certain transduction bias circuit is used for this transistor seconds is carried out deciding the transduction bias voltage.
13. a method that improves the linearity of transistor resistance comprises:
One the first transistor that operates in resistance area is provided, and wherein, the drain electrode of this first transistor and source electrode are respectively applied for and receive an input signal and output one output signal; And
Produce a compensating signal according to this input signal, send into a grid of this first transistor, so that the voltage difference between this grid and this source electrode is near a constant.
14. method as claimed in claim 13, wherein, the change of this compensating signal is corresponding with the change of this output signal.
15. method as claimed in claim 13, wherein, this compensating signal and this input signal are synchronous voltage signals.
16. method as claimed in claim 13 more comprises:
One transistor seconds that operates in the saturation region is provided, and wherein, the grid of this transistor seconds and source electrode couple mutually with this grid and this source electrode of this first transistor respectively.
17. method as claimed in claim 16, wherein, this first and second transistorized grid has the identical width of essence to the length ratio.
18. method as claimed in claim 16 more comprises:
This transistor seconds carries out deciding the transduction bias voltage.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA2007101802601A CN101414810A (en) | 2007-10-16 | 2007-10-16 | Transistor resistance and correlation method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA2007101802601A CN101414810A (en) | 2007-10-16 | 2007-10-16 | Transistor resistance and correlation method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN101414810A true CN101414810A (en) | 2009-04-22 |
Family
ID=40595173
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNA2007101802601A Pending CN101414810A (en) | 2007-10-16 | 2007-10-16 | Transistor resistance and correlation method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101414810A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105789330A (en) * | 2014-12-25 | 2016-07-20 | 北大方正集团有限公司 | Semiconductor resistor |
| CN105845738A (en) * | 2015-01-15 | 2016-08-10 | 北大方正集团有限公司 | High-voltage resistor |
| CN109900965A (en) * | 2017-12-07 | 2019-06-18 | 南亚科技股份有限公司 | A kind of measuring method of the contact resistance of MOS transistor |
-
2007
- 2007-10-16 CN CNA2007101802601A patent/CN101414810A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105789330A (en) * | 2014-12-25 | 2016-07-20 | 北大方正集团有限公司 | Semiconductor resistor |
| CN105789330B (en) * | 2014-12-25 | 2019-04-16 | 北大方正集团有限公司 | Semiconductor resistor |
| CN105845738A (en) * | 2015-01-15 | 2016-08-10 | 北大方正集团有限公司 | High-voltage resistor |
| CN105845738B (en) * | 2015-01-15 | 2018-09-14 | 北大方正集团有限公司 | High-tension resistive |
| CN109900965A (en) * | 2017-12-07 | 2019-06-18 | 南亚科技股份有限公司 | A kind of measuring method of the contact resistance of MOS transistor |
| CN109900965B (en) * | 2017-12-07 | 2021-09-21 | 南亚科技股份有限公司 | Method for measuring contact resistance of MOS transistor |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7737790B1 (en) | Cascode amplifier and method for controlling current of cascode amplifier | |
| US9800156B2 (en) | Amplifier circuit and voltage regulator | |
| US6392490B1 (en) | High-precision biasing circuit for a cascoded CMOS stage, particularly for low noise amplifiers | |
| US9483069B2 (en) | Circuit for generating bias current | |
| US20160087633A1 (en) | Differential driver with pull up and pull down boosters | |
| EP1914887B1 (en) | Differential amplifier with current source controlled through differential feedback | |
| CN101431312A (en) | Controllable oscillating system and related method for selectively adjusting currents passing through cross-coupling driving device | |
| JP2007159117A (en) | Low voltage low power class a/b output stage | |
| CN108351662A (en) | Bandgap reference circuit with curvature compensation | |
| JP2011155488A (en) | Differential input stage circuit, operational amplifier including the same, and voltage regulator circuit | |
| WO2012083781A1 (en) | Voltage comparator | |
| CN106712754A (en) | MOS-used adaptive body bias dynamic threshold generator | |
| US20070036242A1 (en) | Receiver capable of increasing operation speed with suppressing increase of power consumption | |
| CN101414810A (en) | Transistor resistance and correlation method | |
| WO2002103909A1 (en) | Gain compensation and bias current control in an lvds circuit | |
| AU2007203544B2 (en) | High gain, high speed comparator operable at low current | |
| JP2007036151A (en) | Semiconductor device with integrated resistive voltage divider circuit | |
| TW201444273A (en) | Integration of signal sampling within transistor amplifier stage | |
| JP2005277554A (en) | Comparator circuit | |
| US7307476B2 (en) | Method for nullifying temperature dependence and circuit therefor | |
| CN103516318A (en) | Receiver circuit | |
| CN107404291B (en) | Bias circuit and low noise amplifier | |
| KR20150123716A (en) | Power supply voltage monitoring circuit, and electronic circuit including the power supply voltage monitoring circuit | |
| TWI325177B (en) | Transistor resistor and associated method | |
| US20180191321A1 (en) | Temperature-compensated equalizer |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C12 | Rejection of a patent application after its publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20090422 |