CN101414457A - Memory data access method and memory using the same - Google Patents
Memory data access method and memory using the same Download PDFInfo
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- CN101414457A CN101414457A CNA2007101524748A CN200710152474A CN101414457A CN 101414457 A CN101414457 A CN 101414457A CN A2007101524748 A CNA2007101524748 A CN A2007101524748A CN 200710152474 A CN200710152474 A CN 200710152474A CN 101414457 A CN101414457 A CN 101414457A
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Abstract
The invention discloses an access method of memory data and a memory using the method. The access method of the memory data comprises the following steps: a write command and a read command from a microprocessor unit are directly input into a memory so as to perform time optimization processing.
Description
Technical field
The present invention relates to a kind of method of data access and use the unit of this method, and particularly relate to a kind of method of memory data access and use the storer of this method.
Background technology
LCD (Liquid Crystal Display in recent years, LCD) based on advantage such as its low power consumption, radiationless line scattering, in light weight and volume be little, be widely adopted mobile phone, personal digital assistant (Personal Digital Assistant, PDA), information products such as computer screen, TV.In addition, because the universalness of mobile phone, network, the digitizing of life, no matter be the information products of portable electronic product or house, office, the wherein lifting of the increase of display sizes and video picture quality, as resolution, contrast etc., all be general requirement at present, and these all rely in visualization data processing extremely fast.Promote the speed of handling visualization data and also just become a present important techniques problem.
The processing of visualization data, be main end (HOST) by the outside by cpu i/f control whole operation, source electrode driver and LCD Panel are used for show image, sweep circuit is chosen whole line pixel according to the address, and supplies its voltage to open.
LCD driver includes a storer, cpu i/f, panel interface ... or the like circuit.Storer promptly receives CPU write command and address date by cpu i/f, and display reading order and address, arrives the panel video picture by the panel interface output pixel data again.
Fig. 1 shows and knownly imports the CPU write command 111 of storer 13 and the flow process of display reading order 112 by main end 11 into by interface 12.Main end 11 sends CPU write command 111 and CPU writes address signal 113, CPU writes data-signal 114, also send display reading order 112 and display reading address signal 115, again memory writer command 121, storer are write by digital control circuit (Digital Control Circuit) 15 and high frequency oscillator 14 that address signal 123, storer write data-signal 124 and memory read command fetch 122, storer reads signals such as address signal 125 and reaches storer 13.
Fig. 2 is the correlation timing figure of Fig. 1, above-mentioned these two orders, and CPU write command 111 and display reading order 112 often might while or quite approaching the generations.CPU write command 111 is sent when t21, and display reading order 112 sends when t22, and t21 and t22 are quite approaching.Known way is to be responsible for these two orders are staggered by digital control circuit 15 and high frequency oscillator 14, and give and these two read write command identical operations times, shown in the memory read command fetch 122 that memory writer command of being told as digital control circuit 15 121 and digital control circuit 15 are told, t21 equals the length of t25 to t26 to the length of t24, and storer will be carried out above-mentioned read write command respectively with the identical time.
Yet, carry out in fact respectively these two read write commands must cost time difference to some extent, write address date order 121 as CPU, storer is carried out and write institute's time spent may be the time span of t21 to the t23 representative, and storer read command signal 122 storeies are carried out and read institute's time spent then should be the time span of t25 to the t26 representative.And t23 to the time span of t25 representative be exactly from storer write finish after to the standby time the memory read operations.
As from the foregoing, utilization digital control circuit and high frequency oscillator can cause waste of time on the data access as the method for interface.
Therefore, be necessary to be improved, reduce waste of time, reach optimized processing of execution time,, and then bigger development space is provided for the liquid crystal video picture with the speed of raising image data processing at the mode of memory data access.
Summary of the invention
Purpose of the present invention is exactly that a kind of method of memory data access is being provided, and to reduce the waste of over head time, realizes execution time optimization ground processing.
Another object of the present invention provides a kind of storer, handles in order to execution time optimization ground.
The present invention proposes a kind of method of memory data access, and the method is directly inputted into a storer with the write command of a CPU and a reading order of a display unit, and this storer can utilize the empty file of not carrying out write operation to carry out read operation.
The present invention also proposes a kind of storer, comprise: an arbitration circuit, when wherein arbitration circuit receives the reading order of write command and display unit, the preferential write operation of using write command to carry out this storer, storer utilize the empty file of the write operation of not carrying out this storer to carry out the read operation of the storer of one or many to use reading order again.
According to preferred embodiment of the present invention, the empty file of the divisible write operation with suitable this storer of embedding of read operation.
The present invention is because of adopting the method for asynchronous memory data access, empty file after can the flexible utilization write operation finishing is carried out read operation, reduce the past in a large number because of relying on digital control circuit, the standby time that occurs after write operation is finished, and then processing with reaching the execution time optimization.
For above and other objects of the present invention, feature and advantage can be become apparent, preferred embodiment cited below particularly, and be described with reference to the accompanying drawings as follows.
Description of drawings
Fig. 1 shows the system block diagrams of known memory data access.
Fig. 2 shows the sequential chart of coherent signal in Fig. 1.
Fig. 3 shows the system block diagrams that is used for asynchronous memory of the embodiment of the invention.
Fig. 4 shows the sequential chart of coherent signal in Fig. 3.
Fig. 5 shows the circuit diagram that is used for asynchronous memory of the embodiment of the invention.
Fig. 6 shows the sequential chart of the coherent signal when input signal has only the CPU write command among Fig. 5.
Fig. 7 shows the sequential chart of the coherent signal when input signal has only the display reading order among Fig. 5.
Fig. 8 shows that input end receives the CPU write command earlier among Fig. 5, the sequential chart of the coherent signal when receiving the display reading order again subsequently.
Fig. 9 shows that input end receives the display reading order earlier among Fig. 5, the sequential chart of the coherent signal when receiving the CPU write command again subsequently.
Figure 10 shows the correlation timing figure that display among Fig. 5 reads the time that can carry out and CPU write cycle.
The reference numeral explanation
11,31: main end
12: interface
13: storer
14: high frequency oscillator
15: digital control circuit
111,311,501:CPU write command signal
511: storer writes status signal
121,521: storer writes signal
112,312,502: the display read command signal
512: storer reads status signal
122,522: the memory read number of winning the confidence
113,123,313,503,541,551:CPU writes address signal
114,124,314,504,542,552:CPU writes data-signal
115,125,315,505: the display reading address signal
32: asynchronous memory
33,57: the impact damper row
51: the command sequence device
52: arbitration circuit
53: random access memory
54: buffer
55: deposit data latching
56: decision circuitry
The repayment signal is finished in the 531:CPU write operation
532: the display read operation is finished the repayment signal
533: data bus
561: judge signal
562: reset signal
T21～t26, t61～t64, t71～t76, t81～t89, t91～t98, t101～t105: time value
CK, RSTB, WR_F, DP_F: end points
Embodiment
Preferred embodiment of the present invention hereinafter is described with reference to the accompanying drawings.
According to preferred embodiment of the present invention, show the system block diagrams of asynchronous memory as Fig. 3, CPU write command 311 is that the data that are used for writing a pixel (for example are 18, depend on what of picture gray scale), display reading order 312 then is the data that are used for reading column of pixels in the storer.If storer is 320 to multiply by 240 size, represents memory size to equal 320 row and multiply by 240 pixels, that is need read the data of 240 pixels continuously.
Among Fig. 3, asynchronous memory 32 is directly from main end 31 input CPU write commands 311, includes that CPU writes address signal 313, CPU writes data-signal 314, and direct input display reading order 312, include display reading address signal 315, export impact damper row 33 again to.Fig. 4 is the sequential chart of CPU write command 311 and display reading order 312 among Fig. 3.
Fig. 5 is the internal circuit diagram of asynchronous memory.In the present embodiment, can omit high frequency oscillator and digital control circuit, this is because asynchronous memory can directly be handled the signal of the main end of input.
Read operation is to utilize the empty file of write operation to carry out.
The meaning of display reading order 502 in Fig. 5 is to remind asynchronous memory to begin to read whole piece pixel column (row pixel) to impact damper row 57.But excessive because of the data volume that reads the whole piece pixel column, easily cause spread of voltage, so must suitably cut apart read operation,,, be filled up to impact damper row 57 via data bus 533 so asynchronous memory can the oneself produce read operation for several times.For explaining orally conveniently, it is example that following examples all produce twice with the oneself.
Below just do more detailed explanation at some possible situations.
Embodiment one, and Fig. 6 shows among Fig. 5 asynchronous memory and has only the CPU of execution write command, and promptly when carrying out the CPU write command, main end does not send under the situation of display reading order the correlation timing figure of described signal.Details as Follows, and please refer to Fig. 5 and Fig. 6.In the time will carrying out the CPU write operation, at first main end can be in Fig. 6 time point t61 send the pulse of a CPU write command 501; Buffer 54 can write data-signal 504 and CPU with CPU according to the positive edge of CPU write command 501 and write address signal 503 and deposit; Simultaneously, at time point t61, command sequence device 51 can write status signal 511 with storer and move high level to, sees Fig. 6; Subsequently, at time point t62, arbitration circuit 52 can write signal 521 with storer and move high level to, causes to deposit data latching 55 and buffer 54 CPU that brings is write data-signal 542 and CPU write address signal 541 and catch; Next, random access memory (Random Access Memory, RAM) 53 just can begin to carry out write operation, at time point t63, finish repayment signal 531 when the write operation of write operation repayment end points (WR_F) and transform to high level, represent write operation to finish from low level.At time point t64, write operation is finished repayment signal 531 when high level transforms to low level, command sequence device 51 can write the storer that precedence record gets off status signal and remove, storer writes status signal 511 and retracts low level, replacement end points RSTB receives reset signal 562, arbitration circuit 52 can be done the operation of resetting earlier, storer writes signal 521 and the memory read number of winning the confidence 522 is low level, then by judging the negative edge of signal 561, trigger pip end CK, the read write command that judges whether other needs to carry out, if do not have, then whole write operation comes to an end.
Embodiment two, and Fig. 7 shows among Fig. 5 when asynchronous memory has only the display of execution reading order, promptly carrying out the display reading order, and main end does not send under the situation of CPU write command the correlation timing figure of described signal.Details as Follows, and please refer to Fig. 5 and Fig. 7.In the time will carrying out the display read operation, at time point t71, at first main end can send the pulse of a display reading order 502; Command sequence device 51 can read status signal 512 with storer and move high level to; Arbitration circuit 52 can be moved the memory read number of winning the confidence 522 to high level subsequently, next random access memory 53 just can begin to carry out the display read operation, at time point t72, finish repayment signal 532 when the display read operation and transform to high level from low level, represent read operation to finish.At time point t73, the display read operation is finished repayment signal 532 when high level transforms to low level; Read owing to only done once, command sequence device 51 does not need that also the storer that precedence record gets off is read status signal and removes, storer reads status signal 512 and remains on former level, arbitration circuit 52 can be done the operation of resetting earlier, and the pressure storer writes signal 521 and the memory read number of winning the confidence 522 is low level; Then by judging the negative edge of signal 561, trigger pip end CK judges whether that other read write command needs to carry out, because storer reads status signal 512 still at high level, so, be pulled to high level again again in the time point t74 memory read number of winning the confidence 522; Next, random access memory 53 is just carried out secondary read operation, at time point t75, finishes repayment signal 532 when the display read operation of read operation repayment end points (DP_F) and transforms to high level from low level, represents read operation to finish.At time point t76, the display read operation is finished repayment signal 532 when high level transforms to low level, read for twice because done, the storer that command sequence device 51 can get off precedence record reads status signal and removes, storer reads status signal 512 and moves low level to, arbitration circuit 52 can be done the operation of resetting, and the pressure storer writes signal 521 and the memory read number of winning the confidence 522 is low level; By judging the negative edge of signal 561, trigger pip end CK judges whether that other read write command needs to carry out then, if do not have, then whole read operation comes to an end.
Embodiment three, and Fig. 8 shows among Fig. 5 when main end sends the CPU write command earlier, sends under the situation of display reading order the correlation timing figure of described signal in the process again.We know that the display read operation can wait the CPU write operation in a single day to finish, and promptly begin to carry out twice that embodiment sets and read, and this promptly utilizes two empty files between the CPU write operation to carry out and reads, and proceeds the CPU write operation after finishing again.Details as Follows, and please refer to Fig. 5 and Fig. 8.At time point t81, send display reading order 502 when main the end, storer reads status signal 512 will move high level to.At time point t82, finish repayment signal 531 when the CPU write operation and transform to high level from low level, represent write operation to finish.At time point t83, the CPU write operation is finished repayment signal 531 when high level transforms to low level, command sequence device 51 can write the storer that precedence record gets off status signal and remove, storer writes status signal 511 and retracts low level, arbitration circuit 52 can be done the operation of resetting, and the pressure storer writes signal 521 and the memory read number of winning the confidence 522 is low level; By judging the negative edge of signal 561, trigger pip end CK judges whether that other read write command needs to carry out then, subsequently, can move the memory read number of winning the confidence 522 to high level at time point t84 arbitration circuit 52, next, random access memory 53 just can begin to carry out read operation; At time point t85, finish repayment signal 532 when the display read operation and transform to high level from low level, represent read operation to finish.At time point t86, the display read operation is finished repayment signal 532 when high level transforms to low level, read owing to only done once, command sequence device 51 does not need that also the storer that precedence record gets off is read status signal and removes, storer reads status signal 512 and remains on former level, arbitration circuit 52 can be done the operation of resetting, and the pressure storer writes signal 521 and the memory read number of winning the confidence 522 is low level; Then by judging the negative edge of signal 561, the read write command that judges whether other needs to carry out, because storer reads status signal 512 still at high level, see signal 512 time point t87, so, be pulled to high level again again in the time point t87 memory read number of winning the confidence 522, next, random access memory 53 is just carried out secondary read operation, at time point t88, finish repayment signal 532 when the display read operation and transform to high level, represent read operation to finish from low level.At time point t89, the display read operation is finished repayment signal 532 when high level transforms to low level, read for twice because done, the storer that command sequence device 51 can get off precedence record reads status signal and removes, storer reads status signal 512 and moves low level to, arbitration circuit 52 can be done the operation of resetting, the pressure storer writes signal 521 and the memory read number of winning the confidence 522 is low level, then by judging the negative edge of signal 561, the read write command that judges whether other needs to carry out, because writing status signal 511, storer is high level, and storer reads status signal 512 and is low level, write so next just can begin to carry out, ablation process such as embodiment one are up to end.
Embodiment four, and Fig. 9 shows to lead among Fig. 5 to hold and sends display reading order 502 earlier, and main end sends under the situation of CPU write command 501 sequential chart of described signal correction again in the process.We know that in a single day display read operations such as CPU write operation meeting are finished and promptly begin to write, and after write operation finishes, second read operation carries out immediately, and this promptly utilizes the empty file of CPU write operation to carry out and reads, and proceeds the CPU write operation after finishing again.Details as Follows, and please refer to Fig. 5 and Fig. 9.At time point t91, when main end sends CPU write command 501, storer writes status signal 511 and will move high level in the case, finishes repayment signal 532 when the display read operation and transforms to high level from low level, represents read operation to finish.At time point t92, the display read operation is finished repayment signal 532 when high level transforms to low level, command sequence device 51 does not need that also the storer that precedence record gets off is read status signal and removes, storer reads status signal 512 and remains on former level, arbitration circuit 52 can be done the operation of resetting, the pressure storer writes signal 521 and the memory read number of winning the confidence 522 is low level, then, at time point t93 by 561 negative edge, trigger pip end CK, the read write command that judges whether other needs to carry out, storer write status signal 511 and storer and read status signal 512 and be high level this moment, but because the priority that writes is higher, write so next just can begin to carry out, process is with embodiment one.At time point t94, finish repayment signal 531 when the CPU write operation and transform to high level from low level, represent write operation to finish.At time point t95, the CPU write operation is finished repayment signal 531 when high level transforms to low level, command sequence device 51 can write the storer that precedence record gets off status signal and remove, storer writes status signal 511 and moves low level to, arbitration circuit 52 can be done the operation of resetting subsequently, the pressure storer writes signal 521 and the memory read number of winning the confidence 522 is low level, then by judging the negative edge of signal 561, the read write command that judges whether other needs to carry out, because writing status signal 511, storer is low level, and storer reads status signal 512 and is high level, so just next can begin to carry out and read process such as embodiment two.In this process, time point t96 master end sends CPU write command 501, and storer writes status signal 511 and moves high level at this moment, at time point t97, finish repayment signal 532 when the display read operation and transform to high level, represent read operation to finish from low level.At time point t98, the display read operation is finished repayment signal 532 when high level transforms to low level, read for twice because done, the storer that command sequence device 51 can get off precedence record reads status signal and removes, storer reads status signal 512 and moves low level to, and do to reset and operate, the pressure storer writes signal 521 and the memory read number of winning the confidence 522 is low level, then by judging the negative edge of signal 561, the read write command that judges whether other needs to carry out, because writing status signal 511, storer is high level, and storer reads status signal 512 and is low level, write so next just can begin to carry out, ablation process such as embodiment one are up to end.
Embodiment five, and Figure 10 shows the correlation timing figure of reading order can be carried out among Fig. 5 time and CPU write cycle.
When the very approaching but display reading order 502 of display reading order 502 and CPU write command 501 takes place earlier, see signal 501 and signal 502 time point t103 and t101, can carry out display reading order 502 earlier this moment, sees signal 522 time point t102.In addition, in Fig. 5, buffer 54 is designed to one deck, that is can only store a CPU write data and address, can not surpass the cycle length that CPU writes so carry out display 522 times that spend of reading, be among Figure 10 t102 to the time span of t105, can not be greater than the time span of t103 among Figure 10 to t104, in case surpass and just to carry out CPU write command 501, can cause the first stroke to exist the CPU of buffer 54 to write address signal 503 and CPU and write data-signal 504 and write address signal 503 and CPU by second CPU and write data-signal 504 coverings and make a mistake.As from the foregoing, the display among the present invention reads the number of plies that the time that can carry out can equal buffer 54 and multiply by the cycle length that CPU writes the address date order.
In sum, the method that is used for memory data access of the present invention, by a cover arbitration and a feedback circuit, can directly import write command and reading order, suitably arrange execution sequence, and will carry out the utilization maximization of empty file, especially shown in embodiment three and example four, thereby realize memory read/write running time optimization, promote the read or write speed of storer greatly.
Though the present invention discloses as above with preferred embodiment; right its is not in order to qualification the present invention, those skilled in the art, under the premise without departing from the spirit and scope of the present invention; when can doing some changes and modification, so protection scope of the present invention should be as the criterion with claim of the present invention.
Claims (13)
1. the method for a memory data access comprises:
One write command and a reading order of one microprocessor unit are inputed to a storer, read to a display unit by storer;
A preferential write operation of using this write command to carry out this storer; And
Utilize the empty file of the write operation of not carrying out this storer to carry out a read operation of this storer to use this reading order.
2. the method for memory data access as claimed in claim 1 further comprises and uses an arbitration circuit to decide this write command to have precedence over this reading order.
3. the method for memory data access as claimed in claim 1 further comprises and cuts apart the empty file of this read operation with the write operation of suitable this storer of embedding.
4. the method for memory data access as claimed in claim 1, this display unit is a display panels.
5. the method for memory data access as claimed in claim 1, this write command is a voltage form.
6. the method for memory data access as claimed in claim 1, this reading order is a voltage form.
7. the method for memory data access as claimed in claim 1, this storer is an asynchronous memory.
8. storer comprises:
One arbitration circuit, when wherein this arbitration circuit receives a reading order of a write command and a display unit, a preferential write operation of using this write command to carry out this storer, this storer utilizes the empty file of the write operation of not carrying out this storer to carry out the read operation of this storer of one or many to use this reading order again.
9. storer as claimed in claim 8, the empty file of the divisible write operation with suitable this storer of embedding of this read operation.
10. storer as claimed in claim 8, this display unit are a display panels.
11. storer as claimed in claim 8, this write command are voltage form.
12. storer as claimed in claim 8, this reading order are voltage form.
13. storer as claimed in claim 8, this storer are an asynchronous memory.
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| CNA2007101524748A CN101414457A (en) | 2007-10-15 | 2007-10-15 | Memory data access method and memory using the same |
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| CNA2007101524748A CN101414457A (en) | 2007-10-15 | 2007-10-15 | Memory data access method and memory using the same |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110245097A (en) * | 2018-03-08 | 2019-09-17 | 爱思开海力士有限公司 | Memory Controller and storage system with Memory Controller |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110245097A (en) * | 2018-03-08 | 2019-09-17 | 爱思开海力士有限公司 | Memory Controller and storage system with Memory Controller |
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