CN101409532B - Hybrid output stage circuit and related method - Google Patents

Hybrid output stage circuit and related method Download PDF

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CN101409532B
CN101409532B CN2007101811403A CN200710181140A CN101409532B CN 101409532 B CN101409532 B CN 101409532B CN 2007101811403 A CN2007101811403 A CN 2007101811403A CN 200710181140 A CN200710181140 A CN 200710181140A CN 101409532 B CN101409532 B CN 101409532B
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CN101409532A (en
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李朝政
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Realtek Semiconductor Corp
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Abstract

本发明提供一种输出装置，用来依据一输入信号以产生一输出信号，包含有：一信号产生电路，用来依据该输入信号产生一第一、第二控制信号；一第一输出级，具有一第一级放大组态用以接收该第一控制信号；以及一第二输出级，具有一第二级放大组态用以接收该第二控制信号，其中该第一级放大组态与该第二级放大组态不相同。

The present invention provides an output device for generating an output signal according to an input signal, comprising: a signal generating circuit for generating a first and a second control signal according to the input signal; a first output stage having a first stage amplification configuration for receiving the first control signal; and a second output stage having a second stage amplification configuration for receiving the second control signal, wherein the first stage amplification configuration is different from the second stage amplification configuration.

Description

混合式输出级电路与相关方法Hybrid output stage circuit and related method

技术领域technical field

本发明涉及一种输出电路，特别涉及一种混合式输出电路。The invention relates to an output circuit, in particular to a hybrid output circuit.

背景技术Background technique

一般来说，运算放大器(operational amplifier)通常为一两级结构的放大器，其包含有一第一级放大电路(亦即放大级)以及一第二级输出电路(亦即输出级)。运算放大器可被分类为A级放大器(Class A)、B级放大器(ClassB)或AB级放大器(Class AB)。请参考图1，图1为现有A级放大器10、B级放大器20以及AB级放大器30与其相对应操作特性(输出电压和驱动电流的关系)的示意图。从图(1a)中可以得知，由于A级放大器10的P-型晶体管Mp在操作时对输入信号Vin的波形为全导通的状态(Imp为P-型晶体管Mp所导通的电流)，即导通角度为360°，因此可以算出A级放大器10的能量转换效率(Power efficiency)小于或等于(＜＝)25％，而从图(1b)可以得知，由于A级放大器10的偏压电流Ibias偏高，才会得到360°的导通角度，然而这亦是造成A级放大器10的能量转换效率偏低的原因，因此，对于一些希望提高能量转换效率的应用中，则比较会使用B级放大器20或AB级放大器30。从图(1c)可以得知，由于B级放大器20的P-型晶体管Mp和N-型晶体管Mn在静态时为刚好载止，在操作时对输入信号Vin的波形为各负责一半的导通状态(Imp为P-型晶体管Mp所导通的电流以及Imn为N-型晶体管MN所导通的电流)，即导通角度为180°，因此可以算出B级放大器20的能量转换效率(Power efficiency)小于或等于(＜＝)78.5％，而图(1d)可以得知，由于B级放大器20的偏压电流Ibias刚好为零，才会得到180°的导通角，而这亦是造成B级放大器20相较于A级放大器10可得到较高能量转换效率的原因，但是，由于在静态时偏压电流Ibias为零使得B级放大器20为关闭的状态，因此输出电压Vo很容易受到噪声的干扰，且输出电压Vo的失真(Distortion)也会比较大。从图(1e)可以得知，由于AB级放大器30的P-型晶体管Mp和N-型晶体管Mn在静态时为少量导通，在操作时对输入信号Vin的波形为各负责一半以上的导通状态(Imp为P-型晶体管Mp所导通的电流以及Imn为N-型晶体管MN所导通的电流)，即导通角度为大于180°，因此，可以算出AB级放大器30的能量转换效率介于A级放大器10和B级放大器20的能量转换效率之间，此外，从图(f)可以得知，由于AB级放大器30的偏压电流Ibias在静态时不为零，因此，若AB级放大器30的P-型晶体管Mp和N-型晶体管Mn面积越大，则静态电流损耗便越大。In general, an operational amplifier (operational amplifier) is usually a two-stage structure amplifier, which includes a first-stage amplifying circuit (ie, amplification stage) and a second-stage output circuit (ie, output stage). Operational amplifiers can be classified as Class A amplifiers (Class A), Class B amplifiers (ClassB), or Class AB amplifiers (Class AB). Please refer to FIG. 1 . FIG. 1 is a schematic diagram of a conventional class A amplifier 10 , class B amplifier 20 and class AB amplifier 30 and their corresponding operating characteristics (relationship between output voltage and driving current). As can be seen from Figure (1a), since the P-type transistor M p of the class A amplifier 10 is fully conducting to the waveform of the input signal Vin during operation (I mp is led by the P-type transistor M p current), that is, the conduction angle is 360°, so it can be calculated that the energy conversion efficiency (Power efficiency) of the Class A amplifier 10 is less than or equal to (<=) 25%, and it can be known from Figure (1b) that due to A Only when the bias current I bias of the class A amplifier 10 is too high can a conduction angle of 360° be obtained, but this is also the reason why the energy conversion efficiency of the class A amplifier 10 is low. Therefore, for some people who wish to improve the energy conversion efficiency In the application, the class B amplifier 20 or the class AB amplifier 30 is more likely to be used. As can be seen from Figure (1c), since the P-type transistor Mp and the N-type transistor Mn of the B-class amplifier 20 are just in static state, they are responsible for half of the waveform of the input signal V in during operation. (I mp is the current conducted by the P-type transistor M p and I mn is the current conducted by the N-type transistor M N ), that is, the conduction angle is 180°, so the class B amplifier can be calculated The energy conversion efficiency (Power efficiency) of 20 is less than or equal to (<=) 78.5%, and Fig. (1d) can know, because the bias current I bias of class B amplifier 20 is exactly zero, just can get 180° conduction and this is also the reason why the class B amplifier 20 can obtain higher energy conversion efficiency compared with the class A amplifier 10, however, the class B amplifier 20 is turned off because the bias current I bias is zero in the static state state, so the output voltage V o is easily disturbed by noise, and the distortion (Distortion) of the output voltage V o will be relatively large. As can be seen from Figure (1e), since the P-type transistor Mp and the N-type transistor Mn of the AB class amplifier 30 are a small amount of conduction in static state, they are responsible for half of the waveform of the input signal V in during operation. Above conduction state (I mp is the current conducted by P-type transistor M p and Imn is the current conducted by N-type transistor M N ), that is, the conduction angle is greater than 180 °, therefore, it can be calculated The energy conversion efficiency of the AB class amplifier 30 is between the energy conversion efficiency of the A class amplifier 10 and the B class amplifier 20, in addition, from the figure (f), it can be known that due to the bias current Ibias of the AB class amplifier 30 in the static state is not zero, therefore, if the area of the P-type transistor Mp and N-type transistor Mn of the AB amplifier 30 is larger, the quiescent current consumption will be larger.

图2所示是现有AB级放大器200的偏压示意图。现有AB级放大器200的偏压方式是利用一电流I0流经一晶体管网络形成的电阻器202(电阻值为Z)来实现。经由适当的选取I0*Z值，可使得不管输出电压Vout为任何值，P-型晶体管Mop1与N-型晶体管Mon1所导通的电流I(Mop1)、I(Mon1)均不会同时为零，而使得抗噪声的能力比较好。另一方面，通过对N-型晶体管Mon1的宽长比(Aspectratio)(W/L)2的选取亦可满足其最大输出电流IN(max)的要求：FIG. 2 is a schematic diagram of a bias voltage of a conventional class AB amplifier 200 . The current biasing method of the class AB amplifier 200 is implemented by using a current I0 to flow through a resistor 202 (resistance value Z) formed by a transistor network. By properly selecting the value of I 0 *Z, no matter what value the output voltage V out is, the conduction currents I (Mop1) and I (Mon1) of the P-type transistor M op1 and the N-type transistor M on1 are the same. will be zero at the same time, which makes the ability to resist noise better. On the other hand, by selecting the aspect ratio (W/L) 2 of the N-type transistor M on1 , the requirement of its maximum output current I N(max) can also be met:

IN(max)＝0.5*Kn*(W/L)2*(Vn1)2 I N(max) ＝0.5*K n *(W/L) 2 *(V n1 ) 2

＝0.5*Kn*X*(Vn1)2，where X＝(W/L)2(1)=0.5*K n *X*(V n1 ) 2 , where X=(W/L) 2 (1)

在上述方程式(1)中，Kn为N-型晶体管导电参数，因此从以上所述可得知现有AB级放大器在静态时仍具有静态耗电的问题。In the above equation (1), K n is the conduction parameter of the N-type transistor, so it can be seen from the above that the existing AB class amplifier still has the problem of static power consumption in static state.

发明内容Contents of the invention

本发明的目的之一在于提供一种混合式输出级电路及相关方法，以解决上述的问题。One of the objectives of the present invention is to provide a hybrid output stage circuit and a related method to solve the above problems.

本发明的目的之一在于提供一种混合式输出级电路及相关方法，以降低静态耗电的问题。One of the objectives of the present invention is to provide a hybrid output stage circuit and a related method to reduce the problem of static power consumption.

本发明的目的之一在于提供一种混合式输出级电路及相关方法，该输出级电路具有好的电流驱动能力。One of the objectives of the present invention is to provide a hybrid output stage circuit and a related method, the output stage circuit has good current driving capability.

本发明的目的之一在于提供一种混合式输出级电路及相关方法，该输出级电路具有更省电的效果。One of the objectives of the present invention is to provide a hybrid output stage circuit and a related method, the output stage circuit has a more power-saving effect.

本发明的目的之一在于提供一种混合式输出级电路及相关方法，该输出级电路具有较高的抗噪声能力。One of the objectives of the present invention is to provide a hybrid output stage circuit and a related method, and the output stage circuit has a higher anti-noise capability.

依据本发明的实施例，提供一种输出装置，用来依据一输入信号以产生一输出信号，包含：一信号产生电路，用来依据该输入信号产生一第一、第二控制信号；一第一输出级，具有一第一级放大组态，用以接收该第一控制信号；以及一第二输出级，具有一第二级放大组态，用以接收该第二控制信号，其中，该第一级放大组态与该第二级放大组态不相同；其中，该第一与该第二输出级相耦接形成一输出端，该输出端输出该输出信号。According to an embodiment of the present invention, an output device is provided for generating an output signal according to an input signal, comprising: a signal generating circuit for generating a first and a second control signal according to the input signal; a first An output stage with a first-stage amplification configuration for receiving the first control signal; and a second output stage with a second-stage amplification configuration for receiving the second control signal, wherein the The first-stage amplification configuration is different from the second-stage amplification configuration; wherein, the first and second output stages are coupled to form an output terminal, and the output terminal outputs the output signal.

依据本发明的实施例，提供一种输出装置，包含：一信号产生电路，用来接收一输入信号，并依据该输入信号以产生一第一、第二控制信号；一第一输出级，用以依据该第一控制信号以输出一输出信号；以及一第二输出级，耦接于该第一输出级，用以依据该第二控制信号以输出该输出信号；其中，当该输入信号是一第一值时，该第一与该第二输出级共同输出一输出信号；当该输入信号是一第二值时，该第二输出级被禁能(disable)。According to an embodiment of the present invention, there is provided an output device, comprising: a signal generating circuit for receiving an input signal and generating a first and a second control signal according to the input signal; a first output stage for to output an output signal according to the first control signal; and a second output stage, coupled to the first output stage, to output the output signal according to the second control signal; wherein, when the input signal is When the input signal is a first value, the first and second output stages jointly output an output signal; when the input signal is a second value, the second output stage is disabled.

依据本发明的实施例，提供一种输出电路，用来产生一输出信号，该输出电路包含：一第一输出级，具有一第一级放大组态，用以接收该第一控制信号；以及一第二输出级，具有一第二级放大组态，用以接收该第二控制信号，其中，该第一级放大组态与该第二级放大组态不相同；其中，该第一与该第二输出级相耦接形成一输出端，该输出端输出该输出信号。According to an embodiment of the present invention, there is provided an output circuit for generating an output signal, the output circuit comprising: a first output stage having a first-stage amplification configuration for receiving the first control signal; and A second output stage has a second-stage amplification configuration for receiving the second control signal, wherein the first-stage amplification configuration is different from the second-stage amplification configuration; wherein the first and The second output stage is coupled to form an output terminal, and the output terminal outputs the output signal.

依据本发明的实施例，提供一种信号输出方法，包含：依据一输入信号产生一控制信号；利用一第一输出级来依据该第一控制信号以产生一输出信号；  以及利用一第二输出级来依据该第二控制信号选择性产生该输出信号；其中，当该输入信号是一第一值时，该第一与该第二输出级共同输出该输出信号；当该输入信号是一第二值时，该第二输出级被禁能(disable)。According to an embodiment of the present invention, a signal output method is provided, including: generating a control signal according to an input signal; using a first output stage to generate an output signal according to the first control signal; and using a second output stage to selectively generate the output signal according to the second control signal; wherein, when the input signal is a first value, the first and second output stages jointly output the output signal; when the input signal is a first value When binary, the second output stage is disabled.

附图说明Description of drawings

图1a-图1f是现有A级放大器、B级放大器以及AB级放大器及其相对应操作特性的示意图。1a-1f are schematic diagrams of conventional class A amplifiers, class B amplifiers and class AB amplifiers and their corresponding operating characteristics.

图2是现有AB级放大器的偏压示意图。Fig. 2 is a schematic diagram of the bias voltage of the conventional class AB amplifier.

图3是本发明输出装置的一实施例的示意图。FIG. 3 is a schematic diagram of an embodiment of the output device of the present invention.

图4是图3所示的输出装置中输入信号的波形图，Fig. 4 is a waveform diagram of an input signal in the output device shown in Fig. 3,

图5是图3所示的输出装置中多个端点的电压电平变化的示意图。FIG. 5 is a schematic diagram of voltage level changes of multiple terminals in the output device shown in FIG. 3 .

附图符号说明Description of reference symbols

    1010     A级放大器Class A amplifier     2020     B级放大器Class B amplifier     30、20030, 200     AB级放大器Class AB amplifier     100100     输出装置output device

    102102     信号产生电路  Signal generating circuit     202202     电阻器 Resistor     10221022     第一输出级The first output stage     10241024     第二输出级  Second output stage     10261026     连出端Even output

具体实施方式Detailed ways

请参考图3，图3所示为本发明输出装置100的一实施例的示意图。输出装置100用来依据一输入信号Sin以产生一输出信号Sout，包含：一信号产生电路102、一第一输出级1022以及一第二输出级1024。信号产生电路102用来依据输入信号Sin产生一第一、第二控制信号；第一输出级1022具有一第一级放大组态，用以接收该第一控制信号；第二输出级1024具有一第二级放大组态，用以接收该第二控制信号，其中，该第一级放大组态与该第二级放大组态不相同；其中，第一与第二输出级1022、1024相耦接形成一输出端1026，输出端1026输出输出信号Sout。其中，第一控制信号包括第一与第二电压信号S1ac、S2ac，第二控制信号包括第三与第四电压信号S3ac、S4ac，信号产生电路102包含第一、第二与第三阻抗元件R1、R2、R3；第一、第二、与第三阻抗元件R1、R2、R3，用来依据接收信号Sin产生第一、第二、第三、第四电压信号S1ac、S2ac、S3ac、S4ac。而且，第三电压信号S3ac的电压电平V3高于第一电压信号S1ac的电压电平V1，以及第二电压信号S2ac的电压电平V2高于第四电压信号S4ac的电压电平V4。一实施例中，第一输出级1022是将一第一P-型晶体管Mop1及一第一N-型晶体管Mon1串联连接并偏压于一AB级(Class AB)放大组态(第一放大组态)，以及第二输出级1024是将一第二P-型晶体管Mop2及一第二N-型晶体管Mon2串联连接并偏压于一B级(Class B)放大组态(第二放大组态)，其连结方式请参考图3所示。一实施例，第一、第二、阻抗元件R1、R2是由晶体管来实施。为了方便描述，第三阻抗元件R3仅由一P-型晶体管和一N-型晶体管构成，然而熟悉此项技艺者应可了解其它型式的晶体管阻抗网络亦可被采用，均属本发明的范畴。另一方面，本发明输出装置100的第一输出级1022和第二输出级1024于输出端点Nout透过输出端1026耦接至一下一级电路，在本实施例中，该下一级电路是用一等效的电阻RL表示。Please refer to FIG. 3 , which is a schematic diagram of an embodiment of an output device 100 of the present invention. The output device 100 is used to generate an output signal S out according to an input signal S in , and includes: a signal generating circuit 102 , a first output stage 1022 and a second output stage 1024 . The signal generating circuit 102 is used to generate a first and a second control signal according to the input signal S in ; the first output stage 1022 has a first stage amplification configuration for receiving the first control signal; the second output stage 1024 has A second-stage amplifying configuration, used to receive the second control signal, wherein the first-stage amplifying configuration is different from the second-stage amplifying configuration; wherein the first and second output stages 1022, 1024 are in phase The coupling forms an output terminal 1026 , and the output terminal 1026 outputs an output signal S out . Wherein, the first control signal includes the first and second voltage signals S 1ac , S 2ac , the second control signal includes the third and fourth voltage signals S 3ac , S 4ac , and the signal generation circuit 102 includes the first, second and second Three impedance elements R 1 , R 2 , R 3 ; the first, second, and third impedance elements R 1 , R 2 , R 3 are used to generate the first, second, third, and third impedance elements according to the received signal S in Four voltage signals S 1ac , S 2ac , S 3ac , S 4ac . Moreover, the voltage level V 3 of the third voltage signal S 3ac is higher than the voltage level V 1 of the first voltage signal S 1ac , and the voltage level V 2 of the second voltage signal S 2ac is higher than the voltage level V 2 of the fourth voltage signal S 4ac The voltage level V 4 . In one embodiment, the first output stage 1022 is a first P-type transistor M op1 and a first N-type transistor M on1 connected in series and biased in an AB-level (Class AB) amplification configuration (first amplifying configuration), and the second output stage 1024 is a second P-type transistor M op2 and a second N-type transistor M on2 connected in series and biased in a B-level (Class B) amplifying configuration (the second Two enlarged configurations), please refer to Figure 3 for the connection method. In one embodiment, the first, second, and impedance elements R 1 , R 2 are implemented by transistors. For the convenience of description, the third impedance element R3 is only composed of a P-type transistor and an N-type transistor, but those skilled in the art should understand that other types of transistor impedance networks can also be used, all of which belong to the present invention category. On the other hand, the first output stage 1022 and the second output stage 1024 of the output device 100 of the present invention are coupled to the next-stage circuit through the output terminal 1026 at the output terminal Nout. In this embodiment, the next-stage circuit Is represented by an equivalent resistance RL .

当本发明输出装置100接收到输入信号Sin时，在端点N1、N2、N3、N4分别对应至电压电平V1、V2、V3、V4。。一实施例，第一P-型晶体管Mop1和第二P-型晶体管Mop2的宽长比(Aspectratio)(W/L)p1和(W/L)p2分别为βp和(X-βp)，而第一N-型晶体管Mon1和第二N-型晶体管Mon2的宽长比(W/L)n1和(W/L)n2则分别为βn和(Y-βn)；请同时参考现有技术中图2的电路图，可以得知本发明的输出装置100的输出级晶体管面积和现有技术的输出级晶体管面积是一样的，即X和Y，因此，本发明输出装置100虽然使用更多的晶体管，但是经由适当设计本发明并不会增加芯片面积。另一方面，由于端点N1、N2、N3、N4上的电压电平V1、V2、V3、V4在输出装置100处于静态时会导通第一P-型晶体管Mop1及第一N-型晶体管Mon1，以及关闭第二P-型晶体管Mop2及第二N-型晶体管Mon2，故能减少静态耗电的情形。请同时参考图2所示的现有AB级放大器200的电路图，由于第一P-型晶体管Mop1的宽长比(W/L)p1小于现有技术中P-型晶体管Mop1的宽长比(W/L)1，以及第一N-型晶体管Mon1的宽长比(W/L)n1小于现有技术中N-型晶体管Mon1的宽长比(W/L)2，因此，本发明输出装置100处于静态时的直流电流小于现有技术。When the output device 100 of the present invention receives the input signal S in , the terminals N1, N2, N3, and N4 respectively correspond to voltage levels V 1 , V 2 , V 3 , and V 4 . . In one embodiment, the aspect ratio (Aspectratio) (W/L) p1 and (W/L) p2 of the first P-type transistor M op1 and the second P-type transistor M op2 are β p and (X-β p ), and the width-to-length ratios (W/L) n1 and (W/L) n2 of the first N-type transistor M on1 and the second N-type transistor M on2 are respectively β n and (Y-β n ) Please refer to the circuit diagram of Fig. 2 in the prior art at the same time, it can be known that the output stage transistor area of the output device 100 of the present invention is the same as the output stage transistor area of the prior art, i.e. X and Y, therefore, the output of the present invention Although the device 100 uses more transistors, the present invention does not increase the chip area through proper design. On the other hand, since the voltage levels V 1 , V 2 , V 3 , V 4 on the terminals N 1 , N 2 , N 3 , N 4 will turn on the first P-type transistor M when the output device 100 is at rest. op1 and the first N-type transistor M on1 , and turn off the second P-type transistor M op2 and the second N-type transistor M on2 , thereby reducing static power consumption. Please also refer to the circuit diagram of the existing AB class amplifier 200 shown in FIG . Ratio (W/L) 1 , and the width-to-length ratio (W/L) n1 of the first N-type transistor M on1 is smaller than the width-to-length ratio (W/L) 2 of the N-type transistor M on1 in the prior art, so , the DC current of the output device 100 in the present invention is smaller than that of the prior art when it is in a static state.

请同时参考图4和图5，图4是图3所示的输出装置100中输入信号Sin的波形图，而图5是图3所示的输出装置100中多个端点N3、N4的电压电平变化的示意图。当输入信号Sin的振幅介于范围Vag1之间时(曲线402)，端点N3的电压电平V3的变化不会低于Vp2(曲线502)，端点N4的电压电平V4的变化不会高于Vn2(曲线504)；因此，此时只有第一P-型晶体管Mop1及第一N-型晶体管Mon1导通，而第二P-型晶体管Mop2及第二N-型晶体管Mon2为关闭，因此第一P-型晶体管Mop1的电流会经由输出端点Nout对该下一级电路充电，而第一N-型晶体管Mon1的电流会经由输出端点Nout对该下一级电路放电。请注意，电压Vp2和Vn2分别为第二P-型晶体管Mop2及第二N-型晶体管Mon2的阈值电压(Threshold voltage)。当输入信号Sin的振幅超出Vag1的范围时(曲线404)，端点N3的电压电平V3的变化会出现低于Vp2(曲线506)的情形，而相对的端点N4的电压电平V4的变化会出现高于Vn2(曲线508)的情形；因此，在时段t1、t2、t3时，第一P-型晶体管Mop1与第二P-型晶体管Mop2会同时导通，而在时段t4、t5、t6时，第一N-型晶体管Mon1与第二N-型晶体管Mon2会同时导通。同理，第一P-型晶体管Mop1和第二P-型晶体管Mop2的电流在时段t1、t2、t3会经由输出端点Nout对该下一级电路充电，而第一N-型晶体管Mon1和第二N-型晶体管Mon2的电流在时段t4、t5、t6会经由输出端点Nout对该下一级电路放电。请同时参考图2所示的现有AB级放大器200的电路图，本发明输出装置100的第一与第二输出级1022、1024在时段t4、t5、t6时的最大驱动电流IN(max)是：Please refer to FIG. 4 and FIG. 5 at the same time. FIG. 4 is a waveform diagram of the input signal S in in the output device 100 shown in FIG. 3 , and FIG. 5 is a plurality of terminals N 3 and N 4 in the output device 100 shown in FIG. Schematic diagram of the voltage level change. When the amplitude of the input signal S in is between the range V ag1 (curve 402), the change of the voltage level V3 of the terminal N3 will not be lower than Vp2 (curve 502), and the voltage level V of the terminal N4 4 will not change higher than V n2 (curve 504); therefore, only the first P-type transistor M op1 and the first N-type transistor M on1 are turned on at this time, while the second P-type transistor M op2 and the second The second N-type transistor M on2 is turned off, so the current of the first P-type transistor M op1 will charge the next stage circuit through the output terminal N out , and the current of the first N-type transistor M on1 will pass through the output terminal N out discharges the next stage circuit. Please note that the voltages V p2 and V n2 are the threshold voltages of the second P-type transistor M op2 and the second N-type transistor M on2 respectively. When the amplitude of the input signal S in exceeds the range of V ag1 (curve 404), the change of the voltage level V3 of the terminal N3 will be lower than Vp2 (curve 506), while the voltage level of the opposite terminal N4 The change of level V 4 will be higher than V n2 (curve 508); therefore, during the period t 1 , t 2 , t 3 , the first P-type transistor M op1 and the second P-type transistor M op2 will be They are turned on at the same time, and during the periods t 4 , t 5 , and t 6 , the first N-type transistor M on1 and the second N-type transistor M on2 are turned on at the same time. Similarly, the currents of the first P-type transistor M op1 and the second P-type transistor M op2 will charge the next stage circuit through the output terminal N out during the period t 1 , t 2 , t 3 , and the first N The currents of the --type transistor M on1 and the second N-type transistor M on2 will discharge the next stage circuit through the output terminal N out during the period t 4 , t 5 , t 6 . Please also refer to the circuit diagram of the existing class AB amplifier 200 shown in FIG. 2 , the maximum driving current I N of the first and second output stages 1022, 1024 of the output device 100 of the present invention during the period t 4 , t 5 , t 6 (max) is:

IN(max)＝0.5*Kn*βn*(V2)2+0.5*Kn*(Y-βn)*(V2-Io*Z)2(2)I N(max) ＝0.5*K n *β n *(V 2 ) 2 +0.5*K n *(Y-β n )*(V 2 -I o *Z) 2 (2)

在上述方程式(2)中，若V2远大于Io*Z，则最大驱动电流IN(max)便近似为：In the above equation (2), if V 2 is much larger than I o *Z, then the maximum drive current I N(max) is approximated as:

IN(max)～＝0.5*Kn*Y*(V2)2(3)I N(max) ～＝0.5*K n *Y*(V 2 ) 2 (3)

在方程式(2)与(3)中，Kn为N-型晶体管导电参数。同理，经由上述教导，熟习此项技艺者亦可轻易地推导出本发明输出装置100的第一与第二输出级1022、1024在时段t1、t2、t3时的最大驱动电流IP(max)。In equations (2) and (3), K n is the conduction parameter of the N-type transistor. Similarly, through the above teachings, those skilled in the art can easily deduce the maximum driving current I of the first and second output stages 1022, 1024 of the output device 100 of the present invention during the period t1 , t2 , t3 P(max) .

由上述公式可以得知，本发明输出级的最大驱动电流IN(max)是和现有技术所提供的最大驱动电流是一样的，因此，本发明输出装置100不仅在静态时维持第一输出级1022处于比现有技术更省电的导通状态，以得到较高的抗噪声能力，而在输入信号Sin振幅增加时亦可以得到和现有技术同样的电流驱动能力。换句话说，本发明输出装置100对输出信号Sout的驱动电流是依据输入信号Sin的振幅来决定的，当输入信号Sin的振幅介于范围Vag1之间时，输出信号Sout的上升和下降是分别由第一P-型晶体管Mop1及第一N-型晶体管Mon1的电流来驱动；而当输入信号Sin的振幅超出Vag1的范围时，输出信号Sout的上升和下降是分别由第一P-型晶体管Mop1、第二P-型晶体管Mop2及第一N-型晶体管Mon1第二N-型晶体管Mon2的电流来驱动。It can be known from the above formula that the maximum drive current I N(max) of the output stage of the present invention is the same as the maximum drive current provided by the prior art. Therefore, the output device 100 of the present invention not only maintains the first output when static The stage 1022 is in an on-state that saves more power than the prior art, so as to obtain higher anti-noise capability, and the same current driving capability as the prior art can be obtained when the amplitude of the input signal S in increases. In other words, the drive current of the output device 100 of the present invention for the output signal S out is determined according to the amplitude of the input signal S in , when the amplitude of the input signal S in is within the range V ag1 , the output signal S out The rise and fall are respectively driven by the currents of the first P-type transistor M op1 and the first N-type transistor M on1 ; and when the amplitude of the input signal S in exceeds the range of V ag1 , the rise and fall of the output signal S out The falling is driven by the currents of the first P-type transistor M op1 , the second P-type transistor M op2 and the first N-type transistor M on1 and the second N-type transistor M on2 respectively.

请注意，本实施例的信号产生电路102中的第一、第二、第三阻抗元件R1、R2、R3亦可由其它型式的阻抗元件所实现，仍属本发明的范畴。Please note that the first, second, and third impedance elements R 1 , R 2 , and R 3 in the signal generating circuit 102 of this embodiment can also be realized by other types of impedance elements, which still belong to the scope of the present invention.

以上所述仅为本发明的较佳实施例，凡依本发明申请专利范围所做的均等变化与修饰，皆应属本发明的涵盖范围。The above descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made according to the scope of the patent application of the present invention shall fall within the scope of the present invention.

Claims (14)

1. output device comprises:
One signal generating circuit is used for receiving an input signal, and according to this input signal to produce first, second control signal;
One first output stage, in order to according to this first control signal to export an output signal; And
One second output stage is coupled to this first output stage, in order to according to this second control signal to export this output signal;
Wherein, this first couples mutually with this second output stage and to form an output, and this output is exported this output signal,
Wherein, when this input signal is one first value, this first with this second output stage export this output signal jointly; When this input signal was one second value, this second output stage was by forbidden energy.
2. output device as claimed in claim 1, wherein, this first output stage includes a first transistor and a transistor seconds, and this first transistor and this transistor seconds are connected in series.
3. output device as claimed in claim 2, wherein, this second output stage includes one the 3rd transistor AND gate 1 the 4th transistor, and the 3rd transistor AND gate the 4th transistor series connects.
4. output device as claimed in claim 3, wherein, this first and this transistor seconds be that bias voltage is that an AB level is amplified configuration, and the 3rd and the 4th transistor is that bias voltage is that a B level is amplified configuration.
5. output device as claimed in claim 1, wherein, this first control signal comprises one first and one second voltage signal, and this second control signal comprises one the 3rd and one the 4th voltage signal, and this generation circuit comprises one first impedance component, one second impedance component and one the 3rd impedance component; This first, this second, with the 3rd impedance component, be used for producing this first, second, third, fourth voltage signal according to this input signal.
6. output device as claimed in claim 5, wherein, this second impedance component is made of at least one transistor.
7. signal output method comprises:
Produce first control signal and second control signal according to an input signal;
Utilize one first output stage to come according to this first control signal to produce an output signal; And
Utilize one second output stage to produce this output signal according to this second control signal selectivity;
Wherein, this first couples mutually with this second output stage and to form an output, and this output is exported this output signal,
Wherein, when this input signal is one first value, this first with this second output stage export this output signal jointly; When this this input signal was one second value, this second output stage was by forbidden energy.
8. method as claimed in claim 7, wherein, this first output stage is that bias voltage is that an AB level is amplified configuration, and this second output stage is that bias voltage is that a B level is amplified configuration.
9. method as claimed in claim 7, wherein, this first output stage includes a first transistor and a transistor seconds, this the first transistor and this transistor seconds are connected in series, wherein, this second output stage includes one the 3rd transistor AND gate 1 the 4th transistor, and the 3rd transistor AND gate the 4th transistor series connects.
10. method as claimed in claim 7, wherein, this first output stage is in order to provide one first electric current, and this second output stage is in order to provide one second electric current, and the current value of this second electric current is greater than the current value of this first electric current.
11. a signal output method comprises:
Utilize one first output stage to come according to an input signal to produce one first electric current; And
Utilize one second output stage to come according to this input signal to produce one second electric current; And
This first electric current of addition and this second electric current are to export an output signal;
Wherein, when this input signal is one first value, this first with this second output stage export this output signal jointly; When this input signal was one second value, this second output stage was by forbidden energy (disable).
12. method as claimed in claim 11, wherein, the current value of this second electric current is greater than the current value of this first electric current.
13. method as claimed in claim 11, wherein, this first output stage includes a first transistor and a transistor seconds, this the first transistor and this transistor seconds are connected in series, wherein, this second output stage includes one the 3rd transistor AND gate 1 the 4th transistor, and the 3rd transistor AND gate the 4th transistor series connects.
14. method as claimed in claim 13, wherein, this first and this transistor seconds be that bias voltage is that an AB level is amplified configuration, and the 3rd and the 4th transistor is that bias voltage is that a B level is amplified configuration.
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4422050A (en) * 1980-07-09 1983-12-20 Nippon Gakki Seizo Kabushiki Kaisha Single-ended push-pull amplifier with two complementary push-pull circuits
US5162753A (en) * 1991-11-27 1992-11-10 At&T Bell Laboratories Amplifier arrangement for use as a line driver
US6788147B1 (en) * 2002-11-05 2004-09-07 National Semiconductor Corporation Operational amplifier with class-AB+B output stage
CN1770622A (en) * 2004-11-05 2006-05-10 株式会社日立国际电气 Amplifier

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4422050A (en) * 1980-07-09 1983-12-20 Nippon Gakki Seizo Kabushiki Kaisha Single-ended push-pull amplifier with two complementary push-pull circuits
US5162753A (en) * 1991-11-27 1992-11-10 At&T Bell Laboratories Amplifier arrangement for use as a line driver
US6788147B1 (en) * 2002-11-05 2004-09-07 National Semiconductor Corporation Operational amplifier with class-AB+B output stage
CN1770622A (en) * 2004-11-05 2006-05-10 株式会社日立国际电气 Amplifier

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