CN101409532B - Mixed output stage circuit and correlation method - Google Patents
Mixed output stage circuit and correlation method Download PDFInfo
- Publication number
- CN101409532B CN101409532B CN2007101811403A CN200710181140A CN101409532B CN 101409532 B CN101409532 B CN 101409532B CN 2007101811403 A CN2007101811403 A CN 2007101811403A CN 200710181140 A CN200710181140 A CN 200710181140A CN 101409532 B CN101409532 B CN 101409532B
- Authority
- CN
- China
- Prior art keywords
- output
- transistor
- signal
- output stage
- input signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Landscapes
- Amplifiers (AREA)
Abstract
The invention provides an output device for generating an output signal according to an input signal. The device comprises a signal generating circuit for generating a first control signal and a second control signal according to the input signal, a first output stage which is provided with a first amplifying configuration and used for receiving the first control signal and a second output stage which is provided with a second amplifying configuration and used for receiving the second control signal; wherein, the first amplifying configuration and the second amplifying configuration are different.
Description
Technical field
The present invention relates to a kind of output circuit, particularly a kind of hybrid output circuit.
Background technology
In general, operational amplifier (operational amplifier) is generally the amplifier of a two-layer configuration, and it includes a first order amplifying circuit (that is amplifying stage) and a second level output circuit (that is output stage).Operational amplifier can be classified as A level amplifier (Class A), B level amplifier (ClassB) or AB level amplifier (Class AB).Please refer to Fig. 1, Fig. 1 is the schematic diagram of existing A level amplifier 10, B level amplifier 20 and AB level amplifier 30 corresponding operating characteristics with it (relation of output voltage and drive current).From figure (1a), can learn, because the P-transistor npn npn M of A level amplifier 10
pWhen operation to input signal V
InWaveform be the state (I of full conducting
MpBe P-transistor npn npn M
pThe electric current of institute's conducting), i.e. conducting angle is 360 °, and the energy conversion efficiency (Power efficiency) that therefore can calculate A level amplifier 10 is less than or equal to (＜=) 25%, and can learn from figure (1b), because the bias current I of A level amplifier 10
BiasHigher, just can obtain 360 ° conducting angle, yet this also is the energy conversion efficiency reason on the low side that causes A level amplifier 10, therefore, wish to improve in the application of energy conversion efficiency for some, then relatively can use B level amplifier 20 or AB level amplifier 30.Can learn from figure (1c), because the P-transistor npn npn M of B level amplifier 20
pWith N-transistor npn npn M
nWhen static state, end for just carrying, when operation to input signal V
InWaveform be responsible for the conducting state (I of half for each
MpBe P-transistor npn npn M
pThe electric current and the I of institute's conducting
MnBe N-transistor npn npn M
NThe electric current of institute's conducting), i.e. conducting angle is 180 °, and the energy conversion efficiency (Power efficiency) that therefore can calculate B level amplifier 20 is less than or equal to (＜=) 78.5%, can learn and scheme (1d), because the bias current I of B level amplifier 20
BiasJust is zero, just can obtains 180 ° the angle of flow, and this also is to cause B level amplifier 20 can obtain the reason of higher-energy conversion efficiency compared to A level amplifier 10, still since when static state bias current I
BiasBe that the zero B level amplifier 20 that makes is closing state, so output voltage V
oBe easy to be subjected to interference of noise, and output voltage V
oDistortion (Distortion) also can be bigger.Can learn from figure (1e), because the P-transistor npn npn M of AB level amplifier 30
pWith N-transistor npn npn M
nBe a small amount of conducting when static state, when operation to input signal V
InWaveform be that each is responsible for conducting state (I over half
MpBe P-transistor npn npn M
pThe electric current and the I of institute's conducting
MnBe N-transistor npn npn M
NThe electric current of institute's conducting), i.e. conducting angle is greater than 180 °, therefore, the energy conversion efficiency that can calculate AB level amplifier 30 is between the energy conversion efficiency of A level amplifier 10 and B level amplifier 20, in addition, can learn, because the bias current I of AB level amplifier 30 from figure (f)
BiasNon-vanishing when static state, therefore, if the P-transistor npn npn M of AB level amplifier 30
pWith N-transistor npn npn M
nArea is big more, and then static current consumption is just big more.
Shown in Figure 2 is the bias voltage schematic diagram of existing AB level amplifier 200.The bias voltage mode of existing AB level amplifier 200 is to utilize an electric current I
0The resistor 202 (resistance value is Z) that the transistor network of flowing through forms is realized.Via the suitable I that chooses
0* no matter the Z value can make output voltage V
OutBe any value, P-transistor npn npn M
Op1With N-transistor npn npn M
On1The electric current I of institute's conducting
(Mop1), I
(Mon1)All can not be zero simultaneously, and make that antimierophonic ability is relatively good.On the other hand, by to N-transistor npn npn M
On1Breadth length ratio (Aspectratio) (W/L)
2Choose and also can satisfy its maximum output current I
N (max)Requirement:
I
N(max)＝0.5*K
n*(W/L)
2*(V
n1)
2
＝0.5*K
n*X*(V
n1)
2，where?X＝(W/L)
2(1)
In aforesaid equation (1), K
nBe N-transistor npn npn conduction parameter, therefore can learn that from the above existing AB level amplifier still has the problem of static power consumption when the static state.
Summary of the invention
One of purpose of the present invention is to provide a kind of mixed output stage circuit and correlation technique, to solve the above problems.
One of purpose of the present invention is to provide a kind of mixed output stage circuit and correlation technique, to reduce the problem of static power consumption.
One of purpose of the present invention is to provide a kind of mixed output stage circuit and correlation technique, and this output-stage circuit has good current driving ability.
One of purpose of the present invention is to provide a kind of mixed output stage circuit and correlation technique, and this output-stage circuit has the effect of more power saving.
One of purpose of the present invention is to provide a kind of mixed output stage circuit and correlation technique, and this output-stage circuit has higher noise resisting ability.
According to embodiments of the invention, a kind of output device is provided, be used for foundation one input signal to produce an output signal, comprise: a signal generating circuit is used for producing first, second control signal according to this input signal; One first output stage has a first order and amplifies configuration, in order to receive this first control signal; And one second output stage, have a second level and amplify configuration, in order to receive this second control signal, wherein, it is inequality with this second level amplification configuration that this first order is amplified configuration; Wherein, this first couples mutually with this second output stage and to form an output, and this output is exported this output signal.
According to embodiments of the invention, a kind of output device is provided, comprise: a signal generating circuit, be used for receiving an input signal, and according to this input signal to produce first, second control signal; One first output stage, in order to according to this first control signal to export an output signal; And one second output stage, be coupled to this first output stage, in order to according to this second control signal to export this output signal; Wherein, when this input signal is one first value, this first with the common output of this second output stage one output signal; When this input signal was one second value, this second output stage was by forbidden energy (disable).
According to embodiments of the invention, a kind of output circuit is provided, be used for producing an output signal, this output circuit comprises: one first output stage has a first order and amplifies configuration, in order to receive this first control signal; And one second output stage, have a second level and amplify configuration, in order to receive this second control signal, wherein, it is inequality with this second level amplification configuration that this first order is amplified configuration; Wherein, this first couples mutually with this second output stage and to form an output, and this output is exported this output signal.
According to embodiments of the invention, a kind of signal output method is provided, comprise: produce a control signal according to an input signal; Utilize one first output stage to come according to this first control signal to produce an output signal; And utilize one second output stage to produce this output signal according to this second control signal selectivity; Wherein, when this input signal is one first value, this first with this second output stage export this output signal jointly; When this input signal was one second value, this second output stage was by forbidden energy (disable).
Description of drawings
Fig. 1 a-Fig. 1 f is the schematic diagram of existing A level amplifier, B level amplifier and AB level amplifier and corresponding operating characteristic thereof.
Fig. 2 is the bias voltage schematic diagram of existing AB level amplifier.
Fig. 3 is the schematic diagram of an embodiment of output device of the present invention.
Fig. 4 is the oscillogram of input signal in the output device shown in Figure 3,
Fig. 5 is the schematic diagram of the voltage level change of a plurality of end points in the output device shown in Figure 3.
The reference numeral explanation
| 10 | A level amplifier |
| 20 | |
| 30、200 | |
| 100 | Output device |
| 102 | |
| 202 | |
| 1022 | |
| 1024 | |
| 1026 | Connect end |
Embodiment
Please refer to Fig. 3, Figure 3 shows that the schematic diagram of an embodiment of output device 100 of the present invention.Output device 100 is used for according to an input signal S
InTo produce an output signal S
Out, comprise: a signal generating circuit 102, one first output stage 1022 and one second output stage 1024.Signal generating circuit 102 is used for according to input signal S
InProduce first, second control signal; First output stage 1022 has a first order and amplifies configuration, in order to receive this first control signal; Second output stage 1024 has a second level and amplifies configuration, and in order to receive this second control signal, wherein, this first order amplifies configuration and this second level amplification configuration is inequality; Wherein, first and second output stage 1022,1024 couples mutually and forms an output 1026, output 1026 output signal output S
OutWherein, first control signal comprises first and second voltage signal S
1ac, S
2ac, second control signal comprises the 3rd and the 4th voltage signal S
3ac, S
4ac, signal generating circuit 102 comprises first, second and the 3rd impedance component R
1, R
2, R
3First, second, with the 3rd impedance component R
1, R
2, R
3, be used for according to received signal S
InProduce first, second, third, fourth voltage signal S
1ac, S
2ac, S
3ac, S
4acAnd, tertiary voltage signal S
3acVoltage level V
3Be higher than the first voltage signal S
1acVoltage level V
1, and the second voltage signal S
2acVoltage level V
2Be higher than the 4th voltage signal S
4acVoltage level V
4Among one embodiment, first output stage 1022 is with one the one P-transistor npn npn M
Op1And one the one N-transistor npn npn M
On1Be connected in series and be biased in an AB level (Class AB) and amplify configuration (first amplifies configuration), and second output stage 1024 is with one the 2nd P-transistor npn npn M
Op2And one the 2nd N-transistor npn npn M
On2Be connected in series and be biased in a B level (Class B) and amplify configuration (second amplifies configuration), its mode of connection please refer to shown in Figure 3.One embodiment, first, second, impedance component R
1, R
2Be to implement by transistor.For convenience of description, the 3rd impedance component R
3Only constitute, also may be utilized, all belong to category of the present invention yet those who are familiar with this art should understand the transistor impedance network of other pattern by a P-transistor npn npn and a N-transistor npn npn.On the other hand, first output stage 1022 of output device 100 of the present invention and second output stage 1024 are in exit point N
OutSee through output 1026 and be coupled to a next stage circuit, in the present embodiment, this next stage circuit is the resistance R with an equivalence
LExpression.
When output device 100 of the present invention receives input signal S
InThe time, correspond to voltage level V respectively at end points N1, N2, N3, N4
1, V
2, V
3, V
4。One embodiment, a P-transistor npn npn M
Op1With the 2nd P-transistor npn npn M
Op2Breadth length ratio (Aspectratio) (W/L)
P1(W/L)
P2Be respectively β
p(X-β
p), and a N-transistor npn npn M
On1With the 2nd N-transistor npn npn M
On2Breadth length ratio (W/L)
N1(W/L)
N2Then be respectively β
n(Y-β
n); Please also refer to the circuit diagram of Fig. 2 in the prior art, can learn that the output stage transistor area of output device 100 of the present invention and the output stage transistor area of prior art are the same, be X and Y, therefore, though output device 100 of the present invention uses more transistor, can't increase chip area via suitable design the present invention.On the other hand, because end points N
1, N
2, N
3, N
4On voltage level V
1, V
2, V
3, V
4Can conducting the one P-transistor npn npn M when output device 100 is in static state
Op1An and N-transistor npn npn M
On1, and close the 2nd P-transistor npn npn M
Op2And the 2nd N-transistor npn npn M
On2So, can reduce the situation of static power consumption.Please also refer to the circuit diagram of existing AB level amplifier 200 shown in Figure 2, because a P-transistor npn npn M
Op1Breadth length ratio (W/L)
P1Less than P-transistor npn npn M in the prior art
Op1Breadth length ratio (W/L)
1, and a N-transistor npn npn M
On1Breadth length ratio (W/L)
N1Less than N-transistor npn npn M in the prior art
On1Breadth length ratio (W/L)
2, therefore, the direct current when output device 100 of the present invention is in static state is less than prior art.
Please also refer to Fig. 4 and Fig. 5, Fig. 4 is input signal S in the output device 100 shown in Figure 3
InOscillogram, and Fig. 5 is a plurality of end points N in the output device 100 shown in Figure 3
3, N
4The schematic diagram of voltage level change.As input signal S
InAmplitude between scope V
Ag1Between the time (curve 402), end points N
3Voltage level V
3Variation can not be lower than V
P2(curve 502), end points N
4Voltage level V
4Variation can not be higher than V
N2(curve 504); Therefore, has only a P-transistor npn npn M this moment
Op1An and N-transistor npn npn M
On1Conducting, and the 2nd P-transistor npn npn M
Op2And the 2nd N-transistor npn npn M
On2For closing, a therefore P-transistor npn npn M
Op1Electric current can be via exit point N
OutTo this next stage circuit charging, and a N-transistor npn npn M
On1Electric current can be via exit point N
OutTo this next stage circuit discharging.Note that voltage V
P2And V
N2Be respectively the 2nd P-transistor npn npn M
Op2And the 2nd N-transistor npn npn M
On2Threshold voltage (Threshold voltage).As input signal S
InAmplitude exceed V
Ag1Scope the time (curve 404), end points N
3Voltage level V
3Variation V can appear being lower than
P2The situation of (curve 506), and the voltage level V of relative end points N4
4Variation V can appear being higher than
N2The situation of (curve 508); Therefore, at period t
1, t
2, t
3The time, a P-transistor npn npn M
Op1With the 2nd P-transistor npn npn M
Op2Conducting simultaneously, and at period t
4, t
5, t
6The time, a N-transistor npn npn M
On1With the 2nd N-transistor npn npn M
On2Conducting simultaneously.In like manner, a P-transistor npn npn M
Op1With the 2nd P-transistor npn npn M
Op2Electric current at period t
1, t
2, t
3Can be via exit point N
OutTo this next stage circuit charging, and a N-transistor npn npn M
On1With the 2nd N-transistor npn npn M
On2Electric current at period t
4, t
5, t
6Can be via exit point N
OutTo this next stage circuit discharging.Please also refer to the circuit diagram of existing AB level amplifier 200 shown in Figure 2, first and second output stage 1022,1024 of output device 100 of the present invention is at period t
4, t
5, t
6The time maximum drive current I
N (max)Be:
I
N(max)＝0.5*K
n*β
n*(V
2)
2+0.5*K
n*(Y-β
n)*(V
2-I
o*Z)
2(2)
In aforesaid equation (2), if V
2Much larger than I
o* Z, then maximum drive current I
N (max)Just be approximately:
I
N(max)～＝0.5*K
n*Y*(V
2)
2(3)
In equation (2) and (3), K
nBe N-transistor npn npn conduction parameter.In like manner, via above-mentioned instruction, have the knack of this skill person and also can derive first and second output stage 1022,1024 of output device 100 of the present invention easily at period t
1, t
2, t
3The time maximum drive current I
P (max)
Can learn the maximum drive current I of output stage of the present invention by above-mentioned formula
N (max)Be that the maximum drive current that is provided with prior art is the same, therefore, output device 100 of the present invention is not only kept first output stage 1022 and is in than the prior art conducting state of power saving more when static state, obtaining higher noise resisting ability, and at input signal S
InAmplitude can also obtain the current driving ability same with prior art when increasing.In other words, 100 couples of output signal S of output device of the present invention
OutDrive current be according to input signal S
InAmplitude decide, as input signal S
InAmplitude between scope V
Ag1Between the time, output signal S
OutRising and decline be respectively by a P-transistor npn npn M
Op1An and N-transistor npn npn M
On1Electric current drive; And as input signal S
InAmplitude exceed V
Ag1Scope the time, output signal S
OutRising and decline be respectively by a P-transistor npn npn M
Op1, the 2nd P-transistor npn npn M
Op2An and N-transistor npn npn M
On1The 2nd N-transistor npn npn M
On2Electric current drive.
Note that first, second, third impedance component R in the signal generating circuit 102 of present embodiment
1, R
2, R
3Also can be realized, still be belonged to category of the present invention by the impedance component of other pattern.
The above only is preferred embodiment of the present invention, and all equalizations of being done according to the present patent application claim change and modify, and all should belong to covering scope of the present invention.
Claims (14)
1. output device comprises:
One signal generating circuit is used for receiving an input signal, and according to this input signal to produce first, second control signal;
One first output stage, in order to according to this first control signal to export an output signal; And
One second output stage is coupled to this first output stage, in order to according to this second control signal to export this output signal;
Wherein, this first couples mutually with this second output stage and to form an output, and this output is exported this output signal,
Wherein, when this input signal is one first value, this first with this second output stage export this output signal jointly; When this input signal was one second value, this second output stage was by forbidden energy.
2. output device as claimed in claim 1, wherein, this first output stage includes a first transistor and a transistor seconds, and this first transistor and this transistor seconds are connected in series.
3. output device as claimed in claim 2, wherein, this second output stage includes one the 3rd transistor AND gate 1 the 4th transistor, and the 3rd transistor AND gate the 4th transistor series connects.
4. output device as claimed in claim 3, wherein, this first and this transistor seconds be that bias voltage is that an AB level is amplified configuration, and the 3rd and the 4th transistor is that bias voltage is that a B level is amplified configuration.
5. output device as claimed in claim 1, wherein, this first control signal comprises one first and one second voltage signal, and this second control signal comprises one the 3rd and one the 4th voltage signal, and this generation circuit comprises one first impedance component, one second impedance component and one the 3rd impedance component; This first, this second, with the 3rd impedance component, be used for producing this first, second, third, fourth voltage signal according to this input signal.
6. output device as claimed in claim 5, wherein, this second impedance component is made of at least one transistor.
7. signal output method comprises:
Produce first control signal and second control signal according to an input signal;
Utilize one first output stage to come according to this first control signal to produce an output signal; And
Utilize one second output stage to produce this output signal according to this second control signal selectivity;
Wherein, this first couples mutually with this second output stage and to form an output, and this output is exported this output signal,
Wherein, when this input signal is one first value, this first with this second output stage export this output signal jointly; When this this input signal was one second value, this second output stage was by forbidden energy.
8. method as claimed in claim 7, wherein, this first output stage is that bias voltage is that an AB level is amplified configuration, and this second output stage is that bias voltage is that a B level is amplified configuration.
9. method as claimed in claim 7, wherein, this first output stage includes a first transistor and a transistor seconds, this the first transistor and this transistor seconds are connected in series, wherein, this second output stage includes one the 3rd transistor AND gate 1 the 4th transistor, and the 3rd transistor AND gate the 4th transistor series connects.
10. method as claimed in claim 7, wherein, this first output stage is in order to provide one first electric current, and this second output stage is in order to provide one second electric current, and the current value of this second electric current is greater than the current value of this first electric current.
11. a signal output method comprises:
Utilize one first output stage to come according to an input signal to produce one first electric current; And
Utilize one second output stage to come according to this input signal to produce one second electric current; And
This first electric current of addition and this second electric current are to export an output signal;
Wherein, when this input signal is one first value, this first with this second output stage export this output signal jointly; When this input signal was one second value, this second output stage was by forbidden energy (disable).
12. method as claimed in claim 11, wherein, the current value of this second electric current is greater than the current value of this first electric current.
13. method as claimed in claim 11, wherein, this first output stage includes a first transistor and a transistor seconds, this the first transistor and this transistor seconds are connected in series, wherein, this second output stage includes one the 3rd transistor AND gate 1 the 4th transistor, and the 3rd transistor AND gate the 4th transistor series connects.
14. method as claimed in claim 13, wherein, this first and this transistor seconds be that bias voltage is that an AB level is amplified configuration, and the 3rd and the 4th transistor is that bias voltage is that a B level is amplified configuration.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2007101811403A CN101409532B (en) | 2007-10-12 | 2007-10-12 | Mixed output stage circuit and correlation method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2007101811403A CN101409532B (en) | 2007-10-12 | 2007-10-12 | Mixed output stage circuit and correlation method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101409532A CN101409532A (en) | 2009-04-15 |
| CN101409532B true CN101409532B (en) | 2011-07-13 |
Family
ID=40572367
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2007101811403A Active CN101409532B (en) | 2007-10-12 | 2007-10-12 | Mixed output stage circuit and correlation method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101409532B (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4422050A (en) * | 1980-07-09 | 1983-12-20 | Nippon Gakki Seizo Kabushiki Kaisha | Single-ended push-pull amplifier with two complementary push-pull circuits |
| US5162753A (en) * | 1991-11-27 | 1992-11-10 | At&T Bell Laboratories | Amplifier arrangement for use as a line driver |
| US6788147B1 (en) * | 2002-11-05 | 2004-09-07 | National Semiconductor Corporation | Operational amplifier with class-AB+B output stage |
| CN1770622A (en) * | 2004-11-05 | 2006-05-10 | 株式会社日立国际电气 | Amplifier |
-
2007
- 2007-10-12 CN CN2007101811403A patent/CN101409532B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4422050A (en) * | 1980-07-09 | 1983-12-20 | Nippon Gakki Seizo Kabushiki Kaisha | Single-ended push-pull amplifier with two complementary push-pull circuits |
| US5162753A (en) * | 1991-11-27 | 1992-11-10 | At&T Bell Laboratories | Amplifier arrangement for use as a line driver |
| US6788147B1 (en) * | 2002-11-05 | 2004-09-07 | National Semiconductor Corporation | Operational amplifier with class-AB+B output stage |
| CN1770622A (en) * | 2004-11-05 | 2006-05-10 | 株式会社日立国际电气 | Amplifier |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101409532A (en) | 2009-04-15 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN100578924C (en) | Processing method for output stage circuit, power amplification circuit and electrical signal | |
| US7884671B2 (en) | Low power operational amplifier | |
| EP2251977A2 (en) | Low-noise, low-power, low drift offset correction in operational and instrumentation amplifiers | |
| TWI502883B (en) | A system for driver amplifier | |
| CN101443996B (en) | Circuit and method for driving bulk capacitance of amplifier input transistors | |
| KR20080109840A (en) | Distributed class g type amplifier switching method related application | |
| CN101471631B (en) | Cmos audio operational amplifier | |
| EP2613437A3 (en) | Multi-stage fully differential amplifier with controlled common mode voltage | |
| CN107623495A (en) | Low noise circuit | |
| US8416969B2 (en) | Amplifier circuit | |
| CN101521489B (en) | Amplifier and class AB amplifier | |
| CN101409532B (en) | Mixed output stage circuit and correlation method | |
| TW200926578A (en) | Circuit for buffering having a coupler | |
| CN100530966C (en) | Receiver of low voltage difference signal | |
| KR100771859B1 (en) | Amplifier having easy current controlling structure | |
| CN105207633B (en) | Power amplifier | |
| CN101958690A (en) | Class-D audio power amplifier circuit | |
| CN102570987A (en) | Audio frequency amplifying circuit with improved noise characteristics | |
| CN201956977U (en) | Audio amplification circuit with improved noise characteristics | |
| CN101404479A (en) | Audio output device and method | |
| CN202364177U (en) | Amplifying circuit | |
| US7583145B2 (en) | Hybrid output stage apparatus and related method thereof | |
| CN101453196A (en) | Amplifier circuit | |
| JP2008205738A (en) | Operational amplifier | |
| CN106849050A (en) | The application of reverse-connection protection circuit, H bridge output driving chips and the driving chip |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |