CN101399193A - Grid structure and method for making non-volatile semi-conductor memory device - Google Patents
Grid structure and method for making non-volatile semi-conductor memory device Download PDFInfo
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- CN101399193A CN101399193A CNA200710046812XA CN200710046812A CN101399193A CN 101399193 A CN101399193 A CN 101399193A CN A200710046812X A CNA200710046812X A CN A200710046812XA CN 200710046812 A CN200710046812 A CN 200710046812A CN 101399193 A CN101399193 A CN 101399193A
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Abstract
The invention provides a method for manufacturing a grid structure, and the method comprises the following steps: a tunneling oxide layer is formed on a semiconductor substrate; discrete metal nano dots are formed on the tunneling oxide layer by chemical vapor deposition; a grid dielectric layer and a conducting layer are sequentially formed on the discrete metal nano dots; the conducting layer, the grid dielectric layer, the discrete metal nano dots and the tunneling oxide layer are etched until the semiconductor substrate is exposed, thus forming the grid structure. The invention also provides a method for manufacturing a nonvolatile semiconductor memory. By the chemical vapor deposition, the forming of the metal nano dots is simple, and the size and density of the metal nano dots can be easily controlled.
Description
Technical field
The present invention relates to field of manufacturing semiconductor devices, relate in particular to the manufacture method of grid structure and non-volatile semiconductor memory.
Background technology
Non-volatile semiconductor memory still can the retention tab internal information after power supply is closed; But, and do not need special high voltage in system's electric erasable and overprogram; Non-volatile semiconductor memory has the advantages that cost is low, density is big.Its particular performances makes it apply to every field widely, comprise embedded system, as PC and peripheral hardware, telecommunications switch, cell phone, network interconnection device, instrument and meter and automobile device, also comprise emerging voice, image, storage series products simultaneously, as digital camera, digital recorder and personal digital assistant.
Non-volatile semiconductor memory, it generally is (Stack-Gate) structure that is designed to have stacked gate, this structure comprises tunnel oxide, be used for store charge floating grid or catch charge layer, silicon oxide/silicon nitride/silicon oxide (Oxide-Nitride-Oxide, ONO) dielectric layer and be used for the control grid of control data access between the grid of structure.
Traditional non-volatility memorizer adopts polysilicon as floating grid, is example with the flash memory, application number be flash memory in 200410033268 the Chinese patent application manufacture craft as shown in Figures 1 to 4.With reference to figure 1, form tunnel oxide 102 with thermal oxidation method on the Semiconductor substrate 100, the material of tunnel oxide 102 is silica or silica-silicon-nitride and silicon oxide (ONO).Form first conductive layer 104 on tunnel oxide 102, the material of described first conductive layer 104 for example is a doped polycrystalline silicon, and the method for its formation for example is Low Pressure Chemical Vapor Deposition (LPCVD); Forming dielectric layer 106 between grid on first conductive layer 104, the material of dielectric layer 106 for example is silica, silica/silicon nitride or silicon oxide/silicon nitride/silicon oxide (ONO) between these grid; The material that forms second conductive layer, 108, the second conductive layers 108 with chemical vapour deposition technique on dielectric layer between grid 106 for example is doping compound crystal silicon and metal silicide; Form cap layer 110 with chemical vapour deposition technique on second conductive layer 108, the material of described cap layer 110 is a silicon nitride.As shown in Figure 2, on cap layer 110, form first photoresist layer 112, through overexposure, developing process, definition control gate patterns; With first photoresist layer 112 is mask, and the etching cap layer 110 and second conductive layer 108 form control grid 108a to exposing dielectric layer 106 between grid.As shown in Figure 3, continue with dielectric layer 106 between dry etching method etch-gate definition floating grid figure; Remove first photoresist layer 112 and cap layer 110; With dielectric layer between grid 106 is mask, and etching first conductive layer 104 and tunnel oxide 102 form floating grid 104a to exposing Semiconductor substrate 100; Constitute grid structure by dielectric layer 106, floating grid 104a and tunnel oxide 102 between control grid 108a, grid.Please refer to Fig. 4, then, is mask with the grid structure, injects ion in Semiconductor substrate 100, forms source/drain 101; Form clearance wall 114 in the grid structure both sides; Carry out follow-up metal connecting line process at last, form non-volatile semiconductor memory.
Continuous increase along with integrated level in the ic manufacturing process, the integration density that promotes non-volatile semiconductor memory has become trend, for the size that makes memory cell is constantly dwindled, it is the floating grid of material as catching that charge layer replaces in the prior art with the polysilicon that employing has discrete nano dot, can reduce the horizontal electric leakage of non-volatility memorizer, reduce the non-volatility memorizer that forms and catch the thickness of charge layer, and improve the storage capacity of memory.
The technical scheme of United States Patent (USP) 6774061 is caught charge layer so that the size of memory cell can be dwindled by the nano single crystal silicon conduct.In addition can also be with metallic nanodots as catching charge layer.The technology that forms metallic nanodots is: form silicon oxide layer on Semiconductor substrate; On silicon oxide layer, form metal level with sputtering method; The Semiconductor substrate that has metal level is carried out short annealing handle, make metal level become the discrete metallic nanodots of orderly distribution.But,, be difficult to allow its reunion form metallic nanodots with the method for annealing for metals such as titanium or titanium nitrides.
Summary of the invention
The problem that the present invention solves provides the manufacture method of a kind of grid structure and non-volatile semiconductor memory, makes the formation metallic nanodots simple.
For addressing the above problem, the invention provides a kind of manufacture method of grid structure, comprising: on Semiconductor substrate, form tunnel oxide; On tunnel oxide, form discrete metallic nanodots with chemical vapour deposition technique; On discrete metallic nanodots, form dielectric layer and conductive layer between grid successively; Dielectric layer between etching conductive layer, grid, discrete metallic nanodots and tunnel oxide form grid structure to exposing Semiconductor substrate.
Optionally, the speed of described chemical vapour deposition (CVD) is 2 dusts/second～4 dust/second, sedimentation time 3 seconds～6 seconds.
Optionally, the diameter of described metallic nanodots is 3nm～6nm.Distance between described adjacent metal nano dot is 3nm～6nm.The material of described metallic nanodots is the metal of available chemical vapour deposition technique deposition.The material of described metallic nanodots is titanium or titanium nitride or tungsten or tungsten nitride or tantalum or tantalum nitride or palladium or molybdenum.
The invention provides a kind of manufacture method of non-volatile semiconductor memory, comprising: on Semiconductor substrate, form tunnel oxide; On tunnel oxide, form discrete metallic nanodots with chemical vapour deposition technique; On discrete metallic nanodots, form dielectric layer and conductive layer between grid successively; Dielectric layer between etching conductive layer, grid, discrete metallic nanodots and tunnel oxide form grid structure to exposing Semiconductor substrate; In the Semiconductor substrate of grid structure both sides, form source/drain; Carry out metal connecting line, form non-volatile semiconductor memory.
Optionally, the speed of described chemical vapour deposition (CVD) is 2 dusts/second～4 dust/second, sedimentation time 3 seconds～6 seconds.
Optionally, the diameter of described metallic nanodots is 3nm～6nm.Distance between described adjacent metal nano dot is 3nm～6nm.The material of described metallic nanodots is the metal of available chemical vapour deposition technique deposition.The material of described metallic nanodots is titanium or titanium nitride or tungsten or tungsten nitride or tantalum or tantalum nitride or palladium or molybdenum.
Compared with prior art, the present invention has the following advantages: form discrete metallic nanodots with chemical vapour deposition technique on tunnel oxide.Because chemical vapour deposition technique has a discontinuous growth period in the initial stage of metallic nanodots growth, by the control deposition rate, can directly obtain the metallic nanodots that disperses, make that to form metallic nanodots simple; Owing to do not need extra heat treatment process, processing step is simplified in addition.
Further, the speed of chemical vapour deposition (CVD) is 2 dusts/second～4 dust/second, sedimentation time 3 seconds～6 seconds.At 2 dusts/second～4 dust/in second, make the discontinuous growth time of metallic nanodots long, is 3 seconds～6 seconds with the rate controlled of chemical vapour deposition (CVD), not only forms metallic nanodots easily, and metal nano spot size and density are better controlled.
Description of drawings
Fig. 1 to Fig. 4 is the schematic diagram that existing technology is made flash memory;
Fig. 5 is the embodiment flow chart that the present invention makes grid structure;
Fig. 6 to Fig. 9 is the embodiment schematic diagram that the present invention makes grid structure;
Figure 10 is the embodiment flow chart that the present invention makes non-volatility memorizer;
Figure 11 to Figure 15 is the embodiment schematic diagram that the present invention makes non-volatility memorizer.
Embodiment
The present invention forms discrete metallic nanodots with chemical vapour deposition technique on tunnel oxide.Because chemical vapour deposition technique has a discontinuous growth period in the initial stage of metallic nanodots growth, by the control deposition rate, can directly obtain the metallic nanodots that disperses, make that to form metallic nanodots simple; Owing to do not need extra heat treatment process, processing step is simplified in addition.
Further, the speed of chemical vapour deposition (CVD) is 2 dusts/second～4 dust/second, sedimentation time 3 seconds～6 seconds.At 2 dusts/second～4 dust/in second, make the discontinuous growth time of metallic nanodots long, is 3 seconds～6 seconds with the rate controlled of chemical vapour deposition (CVD), not only forms metallic nanodots easily, and metal nano spot size and density are better controlled.
Below in conjunction with accompanying drawing the specific embodiment of the present invention is described in detail.
Fig. 5 is the embodiment flow chart that the present invention makes grid structure.As shown in Figure 5, execution in step S101 forms tunnel oxide on Semiconductor substrate; Execution in step S102 forms discrete metallic nanodots with chemical vapour deposition technique on tunnel oxide; Execution in step S103 forms dielectric layer and conductive layer between grid successively on discrete metallic nanodots; Execution in step S104, dielectric layer between etching conductive layer, grid, discrete metallic nanodots and tunnel oxide form grid structure to exposing Semiconductor substrate.
Fig. 6 to Fig. 9 is the embodiment schematic diagram that the present invention makes grid structure.As shown in Figure 6, form tunnel oxide 202 on Semiconductor substrate 200, the material of tunnel oxide 202 is silica, silicon oxide/silicon nitride/silicon oxide (ONO), silicon rich oxide (SRO) or silicon oxynitride (SiON) etc.The technology that tradition forms tunnel oxide 202 is thermal oxidation method, under hot environment, Semiconductor substrate 200 is exposed in the aerobic environment, and forming with the silica is the tunnel oxide 202 of material, and described technology realizes in boiler tube usually; The thickness of tunnel oxide 202 is 50 dusts～70 dusts.
Form discrete metallic nanodots 204 with chemical vapour deposition technique on tunnel oxide 202, the material of described metallic nanodots 204 is the metal of available chemical vapour deposition technique deposition.Concrete example such as titanium or titanium nitride or tungsten or tungsten nitride or tantalum or tantalum nitride or palladium or molybdenum etc.
If 1 formation is to be the metallic nanodots 204 of material with the titanium, when temperature is 640 ℃～660 ℃, the pressure of reative cell is 4Torr～6Torr (1Torr=133.32Pa), feeding hydrogen and the flow that flow is 2800sccm～3200sccm (standard ml/min) toward reative cell is the titanium tetrachloride reaction generation titanium of 40mgm～60mgm (milli Grams Per Minute), wherein deposition rate is 2 dusts/second～4 dust/second, and sedimentation time is 3 seconds～4 seconds.
In the present embodiment, the temperature concrete example is as 640 ℃, 645 ℃, 650 ℃, 655 ℃ or 660 ℃ etc., preferred 650 ℃; Chamber pressure is specially 4Torr, 5Torr or 6Torr etc., preferred 5Torr; Hydrogen flowing quantity concrete example such as 2800sccm, 2900sccm, 3000sccm, 3100sccm or 3200sccm etc., preferred 3000sccm; Titanium tetrachloride is specially 40mgm, 50mgm or 60mgm etc., preferred 50mgm; The deposition rate concrete example is as 2 dust/seconds, 3 dust/seconds or 4 dust/seconds etc., preferred 2.5 dust/seconds; Sedimentation time is specially 3 seconds, 3.5 seconds or 4 seconds etc., preferred 3 seconds.
If 2 formation is to be the metallic nanodots 204 of material with the titanium nitride, when temperature is 670 ℃～690 ℃, the pressure of reative cell is 3Torr～5Torr, feed flow in the chemical vapor deposition stove and be the ammonia of 80sccm～120sccm and titanium tetrachloride reaction generation titanium nitride that flow is 400mgm～500mgm, wherein deposition rate is 2 dusts/second～4 dust/second, and sedimentation time is 5 seconds～6 seconds.
In the present embodiment, the temperature concrete example is as 670 ℃, 675 ℃, 680 ℃, 685 ℃ or 690 ℃ etc., preferred 680 ℃; Chamber pressure is specially 3Torr, 4Torr or 5Torr etc., preferred 4Torr; Hydrogen flowing quantity concrete example such as 80sccm, 90sccm, 100sccm, 110sccm or 120sccm etc., preferred 100sccm; Titanium tetrachloride is specially 400mgm, 420mgm, 440mgm, 450mgm, 460mgm, 480mgm or 500mgm etc., preferred 450mgm; The deposition rate concrete example is as 2 dust/seconds, 3 dust/seconds or 4 dust/seconds etc., preferred 3 dust/seconds; Sedimentation time is specially 5 seconds, 5.5 seconds or 6 seconds etc., preferred 6 seconds.
Adopt density, size, the shape of the metallic nanodots 204 of the described method formation of present embodiment to regulate by the technological parameter of control chemical vapour deposition technique.
In the present embodiment, the diameter of described metallic nanodots 204 is 3nm～6nm, concrete example such as 3nm, 4nm, 5nm or 6nm etc.The distance that described adjacent metal nano dot is 204 is 3nm～6nm, concrete example such as 3nm, 4nm, 5nm or 6nm etc.
In the present embodiment, the thickness of described tunnel oxide 202 is specially 50 dusts, 55 dusts, 60 dusts, 65 dusts or 70 dusts etc., is preferably 60 dusts.
As shown in Figure 7, forming dielectric layer 206 between grid on the discrete metallic nanodots 204, the material of dielectric layer 206 for example is silica, silica/silicon nitride or silicon oxide/silicon nitride/silicon oxide (ONO) etc. between these grid; The silicon oxide layer that requires contact with metallic nanodots 204 because of non-volatile semiconductor memory must possess excellent electrical property, and avoiding under normal voltage, electric leakage or electric too early problem of collapsing take place to be used for the metallic nanodots 204 of store charge; Material with dielectric layer between grid 206 is that silica is an example; form the layer of even silicon oxide layer with Low Pressure Chemical Vapor Deposition (LPCVD); the thickness of described silica is 130 dusts～170 dusts, and concrete thickness is 130 dusts, 140 dusts, 150 dusts, 160 dusts or 170 dusts etc. for example.
Form conductive layer 208 with chemical vapour deposition technique on dielectric layer between grid 206, the material of conductive layer 208 for example is doping compound crystal silicon or metal silicide; Form cap layer 210 with chemical vapour deposition technique on conductive layer 208, the material of described cap layer 210 is a silicon nitride etc.
As shown in Figure 8, on cap layer 210, form first photoresist layer 212 with spin-coating method, through overexposure, developing process, definition control gate patterns; With first photoresist layer 212 is mask, to exposing dielectric layer 206 between grid, forms control grid 208a with dry etching method etching cap layer 210 and conductive layer 208.
As shown in Figure 9, continue with dielectric layer 206 between dry etching method etch-gate, the charge layer figure is caught in definition; Remove first photoresist layer 212 and cap layer 210; With dielectric layer between grid 206 is mask,, forms and catches charge layer 204a to exposing Semiconductor substrate 200 with the discrete metallic nanodots 204 of dry etching method etching and tunnel oxide 202; By dielectric layer 206 between control grid 208a, grid, catch charge layer 204a and tunnel oxide 202 constitutes grid structure.
Present embodiment is by the catch charge layer of discrete metallic nanodots 204 as memory, and storage capacity is higher.
Figure 10 is the embodiment flow chart that the present invention makes non-volatility memorizer.As shown in figure 10, execution in step S201 forms tunnel oxide on Semiconductor substrate; Execution in step S202 forms discrete metallic nanodots with chemical vapour deposition technique on tunnel oxide; Execution in step S203 forms dielectric layer and conductive layer between grid successively on discrete metallic nanodots; Execution in step S204, dielectric layer between etching conductive layer, grid, discrete metallic nanodots and tunnel oxide form grid structure to exposing Semiconductor substrate; Execution in step S205 forms source/drain in the Semiconductor substrate of grid structure both sides; Execution in step S206 carries out metal connecting line, forms non-volatile semiconductor memory.
Figure 11 to Figure 15 is the embodiment schematic diagram that the present invention makes non-volatility memorizer.As shown in figure 11, form tunnel oxide 302 on Semiconductor substrate 300, the material of tunnel oxide 302 is silica, silicon oxide/silicon nitride/silicon oxide (ONO), silicon rich oxide (SRO) or silicon oxynitride (SiON) etc.The technology that tradition forms tunnel oxide 302 is thermal oxidation method, under hot environment, Semiconductor substrate 300 is exposed in the aerobic environment, and forming with the silica is the tunnel oxide 302 of material, and described technology realizes in boiler tube usually; The thickness of tunnel oxide 302 is 50 dusts～70 dusts.
Form discrete metallic nanodots 304 with chemical vapour deposition technique on tunnel oxide 302, the material of described metallic nanodots 304 is the metal of available chemical vapour deposition technique deposition.Concrete example such as titanium or titanium nitride or tungsten or tungsten nitride or tantalum or tantalum nitride or palladium or molybdenum etc.
If 1 formation is to be the metallic nanodots 304 of material with the titanium, when temperature is 640 ℃～660 ℃, the pressure of reative cell is 4Torr～6Torr (1Torr=133.32Pa), feeding hydrogen and the flow that flow is 2800sccm～3200sccm (standard ml/min) toward reative cell is the titanium tetrachloride reaction generation titanium of 40mgm～60mgm (milli Grams Per Minute), wherein deposition rate is 2 dusts/second～4 dust/second, and sedimentation time is 3 seconds～4 seconds.
In the present embodiment, the temperature concrete example is as 640 ℃, 645 ℃, 650 ℃, 655 ℃ or 660 ℃ etc., preferred 650 ℃; Chamber pressure is specially 4Torr, 5Torr or 6Torr etc., preferred 5Torr; Hydrogen flowing quantity concrete example such as 2800sccm, 2900sccm, 3000sccm, 3100sccm or 3200sccm etc., preferred 3000sccm; Titanium tetrachloride is specially 40mgm, 50mgm or 60mgm etc., preferred 50mgm; The deposition rate concrete example is as 2 dust/seconds, 3 dust/seconds or 4 dust/seconds etc., preferred 2.5 dust/seconds; Sedimentation time is specially 3 seconds, 3.5 seconds or 4 seconds etc., preferred 3 seconds.
If 2 formation is to be the metallic nanodots 304 of material with the titanium nitride, when temperature is 670 ℃～690 ℃, the pressure of reative cell is 3Torr～5Torr, feed flow in the chemical vapor deposition stove and be the ammonia of 80sccm～120sccm and titanium tetrachloride reaction generation titanium nitride that flow is 400mgm～500mgm, wherein deposition rate is 2 dusts/second～4 dust/second, and sedimentation time is 5 seconds～6 seconds.
In the present embodiment, the temperature concrete example is as 670 ℃, 675 ℃, 680 ℃, 685 ℃ or 690 ℃ etc., preferred 680 ℃; Chamber pressure is specially 3Torr, 4Torr or 5Torr etc., preferred 4Torr; Hydrogen flowing quantity concrete example such as 80sccm, 90sccm, 100sccm, 110sccm or 120sccm etc., preferred 100sccm; Titanium tetrachloride is specially 400mgm, 420mgm, 440mgm, 450mgm, 460mgm, 480mgm or 500mgm etc., preferred 450mgm; The deposition rate concrete example is as 2 dust/seconds, 3 dust/seconds or 4 dust/seconds etc., preferred 3 dust/seconds; Sedimentation time is specially 5 seconds, 5.5 seconds or 6 seconds etc., preferred 6 seconds.
Adopt density, size, the shape of the metallic nanodots 304 of the described method formation of present embodiment to regulate by the technological parameter of control chemical vapour deposition technique.
In the present embodiment, the diameter of described metallic nanodots 304 is 3nm～6nm, concrete example such as 3nm, 4nm, 5nm or 6nm etc.The distance that described adjacent metal nano dot is 304 is 3nm～6nm, concrete example such as 3nm, 4nm, 5nm or 6nm etc.
In the present embodiment, the thickness of described tunnel oxide 302 is specially 50 dusts, 55 dusts, 60 dusts, 65 dusts or 70 dusts etc., is preferably 60 dusts.
As shown in figure 12, forming dielectric layer 306 between grid on the discrete metallic nanodots 304, the material of dielectric layer 306 for example is silica, silica/silicon nitride or silicon oxide/silicon nitride/silicon oxide (ONO) etc. between these grid; Because of non-volatile semiconductor memory requires and catches the silicon oxide layer that charge layer contact and must possess excellent electrical property, avoiding under normal voltage, electric leakage or electric too early problem of collapsing take place to be used for the charge layer of catching of store charge; Material with dielectric layer between grid 306 is that silica is an example; form the layer of even silicon oxide layer with Low Pressure Chemical Vapor Deposition (LPCVD); the thickness of described silica is 130 dusts～170 dusts, and concrete thickness is 130 dusts, 140 dusts, 150 dusts, 160 dusts or 170 dusts etc. for example.
Form conductive layer 308 with chemical vapour deposition technique on dielectric layer between grid 306, the material of conductive layer 308 for example is doping compound crystal silicon or metal silicide; Form cap layer 310 with chemical vapour deposition technique on conductive layer 308, the material of described cap layer 310 is a silicon nitride etc.
As shown in figure 13, on cap layer 310, form first photoresist layer 312 with spin-coating method, through overexposure, developing process, definition control gate patterns; With first photoresist layer 312 is mask, to exposing dielectric layer 306 between grid, forms control grid 308a with dry etching method etching cap layer 310 and conductive layer 308.
As shown in figure 14, continue with dielectric layer 306 between dry etching method etch-gate, the charge layer figure is caught in definition; Remove first photoresist layer 312 and cap layer 310; With dielectric layer between grid 306 is mask,, forms and catches charge layer 304a to exposing Semiconductor substrate 300 with the discrete metallic nanodots 304 of dry etching method etching and tunnel oxide 302; By dielectric layer 306 between control grid 308a, grid, catch charge layer 304a and tunnel oxide 302 constitutes grid structure.
Present embodiment is by the catch charge layer of discrete metallic nanodots 304 as memory, and storage capacity is higher.
As shown in figure 15, with the grid structure is mask, in Semiconductor substrate 300, inject ion, form source electrode 311 and drain electrode 313, source electrode 311 and 313 the position of draining should guarantee between by control grid 308a, grid dielectric layer 306, catch when applying voltage on the grid structure that charge layer 304a and tunnel oxidation layer 302a form, source electrode 311 and drain and can form conducting channel between 313.Among the embodiment, semiconductor substrate materials is selected p type silicon for use, and source electrode 311 and drain electrode 313 are carried out the low-doped ion injection of N type, injects ion such as arsenic ion, phosphonium ion etc.
Sidewall at grid structure forms clearance wall 314.Described clearance wall 314 can adopt silica, silicon nitride, silicon oxynitride and their combination, clearance wall not only can be used for all around gate structure, prevent from more heavy dose of source electrode and drain to inject too consequently may leak break-through in the generation source near raceway groove, prevent short-channel effect, and can also be used to preventing the electric leakage between grid structure and source electrode and the drain electrode.
Deposition interlayer dielectric layer 316 on Semiconductor substrate 300, described interlayer dielectric layer 316 overlies gate structure, source electrode 311 and drain 313; In interlayer dielectric layer 316, form and run through the contact hole that interlayer dielectric layer exposes drain electrode 313; In the contact hole deposits conductive material, and adopt the method for chemico-mechanical polishing to polish interlayer dielectric layer and electric conducting material.Described electric conducting material is tungsten or poly silicon (poly silicon), plays the effect of turning circuit in circuit.
Though oneself discloses the present invention as above with preferred embodiment, the present invention is defined in this.Any those skilled in the art without departing from the spirit and scope of the present invention, all can do various changes and modification, so protection scope of the present invention should be as the criterion with claim institute restricted portion.
Claims (12)
1. the manufacture method of a grid structure is characterized in that, comprising:
On Semiconductor substrate, form tunnel oxide;
On tunnel oxide, form discrete metallic nanodots with chemical vapour deposition technique;
On discrete metallic nanodots, form dielectric layer and conductive layer between grid successively;
Dielectric layer between etching conductive layer, grid, discrete metallic nanodots and tunnel oxide form grid structure to exposing Semiconductor substrate.
2. according to the manufacture method of the described grid structure of claim 1, it is characterized in that the speed of described chemical vapour deposition (CVD) is 2 dusts/second～4 dust/second, sedimentation time 3 seconds～6 seconds.
3. according to the manufacture method of the described grid structure of claim 1, it is characterized in that the diameter of described metallic nanodots is 3nm～6nm.
4. according to the manufacture method of the described grid structure of claim 3, it is characterized in that the distance between described adjacent metal nano dot is 3nm～6nm.
5. according to the manufacture method of the described grid structure of claim 4, it is characterized in that the material of described metallic nanodots is the metal of available chemical vapour deposition technique deposition.
6. according to the manufacture method of the described grid structure of claim 5, it is characterized in that the material of described metallic nanodots is titanium or titanium nitride or tungsten or tungsten nitride or tantalum or tantalum nitride or palladium or molybdenum.
7. the manufacture method of a non-volatile semiconductor memory is characterized in that, comprising:
On Semiconductor substrate, form tunnel oxide;
On tunnel oxide, form discrete metallic nanodots with chemical vapour deposition technique;
On discrete metallic nanodots, form dielectric layer and conductive layer between grid successively;
Dielectric layer between etching conductive layer, grid, discrete metallic nanodots and tunnel oxide form grid structure to exposing Semiconductor substrate;
In the Semiconductor substrate of grid structure both sides, form source/drain;
Carry out metal connecting line, form non-volatile semiconductor memory.
8. according to the manufacture method of the described non-volatile semiconductor memory of claim 7, it is characterized in that the speed of described chemical vapour deposition (CVD) is 2 dusts/second～4 dust/second, sedimentation time 3 seconds～6 seconds.
9. according to the manufacture method of the described non-volatile semiconductor memory of claim 7, it is characterized in that the diameter of described metallic nanodots is 3nm～6nm.
10. according to the manufacture method of the described non-volatile semiconductor memory of claim 9, it is characterized in that the distance between described adjacent metal nano dot is 3nm～6nm.
11. the manufacture method according to the described non-volatile semiconductor memory of claim 10 is characterized in that, the material of described metallic nanodots is the metal of available chemical vapour deposition technique deposition.
12. the manufacture method according to the described non-volatile semiconductor memory of claim 11 is characterized in that, the material of described metallic nanodots is titanium or titanium nitride or tungsten or tungsten nitride or tantalum or tantalum nitride or palladium or molybdenum.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102709314A (en) * | 2012-05-22 | 2012-10-03 | 上海华力微电子有限公司 | Physically-isolated silicon nanocrystalline double-bit storage structure and preparation method thereof |
| CN102709289A (en) * | 2012-05-21 | 2012-10-03 | 上海华力微电子有限公司 | Physically-isolated silicon nanocrystalline double-bit storage structure and preparation method thereof |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102709289A (en) * | 2012-05-21 | 2012-10-03 | 上海华力微电子有限公司 | Physically-isolated silicon nanocrystalline double-bit storage structure and preparation method thereof |
| CN102709314A (en) * | 2012-05-22 | 2012-10-03 | 上海华力微电子有限公司 | Physically-isolated silicon nanocrystalline double-bit storage structure and preparation method thereof |
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|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| ASS | Succession or assignment of patent right |
Owner name: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING Effective date: 20111124 |
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| C41 | Transfer of patent application or patent right or utility model | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20111124 Address after: 201203 Shanghai City, Pudong New Area Zhangjiang Road No. 18 Co-patentee after: Semiconductor Manufacturing International (Beijing) Corporation Patentee after: Semiconductor Manufacturing International (Shanghai) Corporation Address before: 201203 Shanghai City, Pudong New Area Zhangjiang Road No. 18 Patentee before: Semiconductor Manufacturing International (Shanghai) Corporation |