CN101388733B - Blind separation interference resistant base band processing device for communication system - Google Patents

Abstract

The invention provides a device for processing blind separation anti-interference basebands of communication systems, which mainly comprises a processor, an information receiving unit, an information output unit and an interfere output and a power supply unit, wherein the information receiving unit is mainly two ways of band-interference input-demodulating down-converted signals. Clock signals and control signals are provided to each unit by a sequential and control unit, the collected two ways of independent band-interference signals are inputted into the processor, and then the pre-processing and the blind separation are carried out by the processer, and separated interference noise and signals are transmitted to the output unit by the processor. The device further can be used in a common communication machine, in particular to be adopted in the fields of radars, military affairs and the like, which has no requirements to the signal-to-noise ratio and can keep the good communication quality under the strong interference.

Description

The blind separation interference resistant base band processing device of communication system

Technical field

The present invention relates to the countermeasure set in a kind of communication system, particularly a kind of communication system base band processing device that adopts the Blind Signal Separation method to realize anti-interference process.

Background technology

In communication system, in communication process, often introduce interference signal easily, and this interference signal is at random, unknown, uncontrollable for communication system often.But it directly has influence on communication quality.Traditional Anti-Jamming Technique is supposed that generally which kind of noise interference source is, and signal to noise ratio is had certain requirement, so just can carry out effective anti-interference process.But; Most noises can't be known; The size of noise also is unable to find out under many circumstances; Sometimes the power of noise can because how to carry out anti-interference process for the interference source that has no way of finding out about it, have important effect for the stability, reliability and the communication quality that improve communication system considerably beyond the power of actual communication model.

The blind signal separation theory is one of the popular research topic in current signal processing field; Refer under the situation of not knowing concrete information source and channel; Under promptly so-called " blind " state; The mixed signal (being called Blind Source) of only utilizing information source and being produced through corresponding processing, just can be separated source signal separately (calling blind separation).In communication system, interference source and signal of communication are typical blind piece-rate systems, think the signal that signal of communication and interference source mix to the signal that receiver receives in channel, and it is isolated signal of communication and interference signal just can realize anti-interference process.In secure communication fields such as military affairs, space flight, electronic countermeasuress; These fields receive artificial interference easily; It is significant effectively to resist third-party interference, therefore, is badly in need of being opened to a kind of blind separation interference resistant base band processing device that is applicable to communication system.

Summary of the invention

The objective of the invention is to the deficiency that exists in the prior art; A kind of interference resistant base band processing device based on Blind Signal Separation is provided; Adopt blind separating method, remove the various interference signals that comprise artificial disturbance, improve communication quality and stability effectively.Design of the present invention is: the device of designing, can have artificial or natural interference signal to the signal of communication that communication control processor receives usually, and carry out anti-interference process to the received signal.The baseband signal that incoherent two radio frequencies is received despreading is passed through blind separating method, isolates interference signal and effective signal of communication, the recipient is received receive the original communication information signal as far as possible.The present invention adopts following technical proposals to realize:

The anti-butt tape processing unit of the blind separation of communication system comprises: a processor, blind separating treatment is handled; Signal input and output control unit 1; Data storage, the FLASH memory, input FIFO and output FIFO is characterized in that: the signal of communication that two-way has an interference is input to the input signal collecting unit after through radio-frequency module collection and down-conversion; Again two paths of signals is stored in input FIFO, two paths of signals is separated into interference signal and signal of communication, be input to simultaneously among the output FIFO by the processor adopting blind separating method; At last, the input signal input and output control unit 1 again, through the decision logic of an interference and signal interference signal and signal of communication differentiated, with blind signal of communication output of separating.

In the anti-butt tape processing unit of the blind separation of above-mentioned communication system; Processor adopting TMS320DM6467 digital signal processor; Its data/address bus BED [0..7] and DDRD [0..31] are connected the data wire of data storage and program storage respectively; Its address bus BEA [1..20] and DDRA [0..13] are connected the address wire of data storage and program storage respectively; FIFO is exported in the CE1 connection among its external memory interface EMIFA, CE2 connects input FIFO, and the TMS320DM6467 processor is communicated with the sequential and the control signal of coming from timing control unit respectively and reaches from the next power supply signal of power subsystem; The signal of communication that is disturbed carries out Blind Signal Separation at the TMS320DM6467 processor, and the intermediate data in the separation process is stored in the data storage by data/address bus through the address wire addressing.

In the anti-butt tape processing unit of the blind separation of above-mentioned communication system; Said signal input and output control unit comprises fpga chip EPM240GT100; The input signal collecting unit comprises the AD9862 cake core; Two band interference signals are linked the AUX_ADC_A1 pin and the AUX_ADC_B1 pin of AD9862 cake core through amplifier separately in previous stage; The D of AD9862 cake core [0..11] A, D [0..11] B pin is connected to B.PIN [15..38] pin of the EPM240GT100 cake core in the signal input and output control unit 1, and the signal that comes from timing control unit is transferred on AD9862 cake core and the EPM240GT100 chip; Under clock and control signal effect that timing control unit comes; Two band interference signals are respectively through amplifying input AD9862 chip; Carry out the A/D conversion within it, output to B.PIN [15..38] pin of the EPM240GT100 chip of input signal collection and signal input and output control unit 1 then.

In the anti-butt tape processing unit of the blind separation of above-mentioned communication system; The signal of communication that has interference is made into one road signal through the two paths of signals alternate group and imports in the TMX320DM6467 chip through input FIFO in said EPM240GT100 cake core, in the TMX320DM6467 cake core, carry out Blind Signal Separation; Signal after the TMX320DM6467 chip carries out blind signal separation is transferred to output FIFO; Be input to the EPM240GT100 cake core through the B.PIN of EPM240GT100 [40..55]; After in the EPM240GT100 cake core, isolating interference signal and signal of communication; Signal from the output of B.PIN [58..71] pin of EPM240GT100; Be input to Tx [0..13] pin of AD9862 cake core, in the AD9862 cake core, after the D/A conversion, output to amplifier, be input to terminal equipment through amplifier again.

In the anti-butt tape processing unit of the blind separation of above-mentioned communication system, data storage adopts 7EA41D9GPX type memory, and the FLASH memory adopts AM29V400 type memory; The data/address bus PD [7..O] of AM29V400 connects the data wire of TMx320DM6467 processor; Address bus PA [19..0] connects the address wire of TMX320DM6467 processor; The data/address bus DD [31..0] of data storage 7EA41D9GPX connects the data wire of TMX320DM6467 processor, and the address bus DA [19..0] of 7EA41D9GPX connects the address wire of TMX320DM6467 processor; Aforementioned two memories link to each other with control unit with sequential; When system program is downloaded; Program code is through address wire PA [19..0] addressing; Download among the FIASH memory AM29LN400 through data/address bus PD [7..0]: the intermediate data in the processing procedure then through address bus DA [9..0] addressing, is stored among the data storage 7EA41D9GPX through data/address bus DD [31..0].

The present invention compares with existing communication Anti-Jamming Technique; Have following conspicuous outstanding substantive distinguishing features and significant advantage: this device adopts blind separating method to carry out anti-interference process; Interference signal is used as a signal source to be handled; Requirement to interference signal is lower, even to strong interference signal, this device also can keep excellent communications quality and stability.Adopt blind separation jamproof system, he all is used as a signal source processing to interference source and signal of communication, therefore can more effectively carry out anti-interference process, improves the stability and the communication quality of communication system.

Description of drawings

Fig. 1 is the communication system architecture block diagram in the execution mode;

Fig. 2 is the blind separation interference resistant base band processing device structured flowchart of communication system among Fig. 1;

Fig. 3 is the circuit connecting relation of the TMX320DM6467 digital signal processor in Fig. 2 example;

Fig. 4 is the fpga chip EPM240GT100 circuit connecting relation in Fig. 2 example;

Fig. 5 is SDRAM and the circuit connecting relation of FLASH in Fig. 2 example;

Fig. 6 is the circuit connecting relation that the inputoutput buffer FIFO in Fig. 2 example adopts the IDT72V265 chip;

Fig. 7 is the power module in Fig. 2 example.

Fig. 8 is blind separation process sketch map.

Embodiment

Describe below in conjunction with the accompanying drawing specific embodiments of the invention.

Apparatus of the present invention are accomplished blind separation process at the communication system architecture of accompanying drawing 1 at baseband module, thereby realize anti-interference process.With reference to figure 1; Signal of communication through disturbing adopts two incoherent relatively antennas, receives the signal of aliasing, carries out AD conversion and despreading to received signal through radio-frequency module; Before demodulation, signal is carried out blind separating treatment, the realization interference signal is separated with signal of communication.

Device of the present invention is as shown in Figure 2: this speech sound enhancement device based on Blind Signal Separation mainly (comprises data storage 5 and FL by processor 2, memory cell; ASH memory 6), timing control unit 8, power subsystem 7 and signal input and output control unit 1, and the input and output buffering (promptly importing FIFO3 forms with output FIFO4.

TMX320DM6467 processor 2 links to each other with jtag interface, data storage 5, FLASH memory 6, input buffer 3 (promptly importing FIFO) and output buffer 4 (promptly exporting FIFO) respectively, like Fig. 2, shown in Figure 4.Signal input and output control unit 1 adopts fpga chip EPM240GT100, and its circuit connecting relation is seen Fig. 3, and an end links to each other with the aliasing signal that collects with input buffer 3; Other end output buffer 4 links to each other, and the signal of separating is differentiated and output with disturbing; Timing control unit 8 respectively with input-output unit 1, TMX320DM6467 processor 2, data storage 5, FLASH memory 6, input buffer 3 and output buffer 4.

Under clock signal and control signal effect that timing control unit 8 produces; The two-way aliasing signal of gathering gets into TMX320DM6467 processor 2 after getting into input buffer 3 again, carries out special blind separating treatment at this; Separate into interference signal and signal of communication; Signal output buffer 4 after separating is outputed to signal input and output control unit 1, through 1 differentiation interference signal and signal of communication, with blind signal output of separating.In addition, jtag interface is that system debug is used, and power subsystem 7 then provides needed power supply signal to all unit.

Referring to Fig. 4; The structure of the collection submodule of signal input and output control unit 1 is: the signal after two radio-frequency antenna demodulation is connected to the VIN+A pin and the VIN+B pin of AD9862 cake core; The D of AD9862 cake core [0..11] A; D [0..11] B pin is connected to B.PIN [15..38] pin of EPM240GT100 cake core in the signal input and output control unit 1, is connected on AD9862 cake core and the EPM240GT100 chip from the signal of sequential and control unit 8.

The structure of output sub-module is: the signal after the TMX320DM6467 processor carries out blind signal separation is transferred to FIFO; Be input to the EPM240GT100 cake core in the signal input and output control unit 1 through the B.PIN of EPM240GT100 [40..55]; After in the EPM240GT100 cake core, handling tissue; Signal from the output of B.PIN [58..71] pin of EPM240GT100; Be input to Tx [0..13] pin of AD9862 cake core, in the AD9862 cake core, after the D/A conversion, output to amplifier, be input to terminal equipment through amplifier again.

Referring to Fig. 3, data wire in the data/address bus BED [0..7] of TMX320DM6467 processor 2 and AED [32..63] connected storage unit (data storage 5 and program storage 6); Address wire in address bus BEA [1..20] and AEA [3..22] the connected storage unit (data storage 5 and program storage 6); Pin E2 (DXO) connects output FIFO; The output signal is transferred to B.PIN [40..55] pin of EPM240GT100 cake core through FIFO; The B.PIN of EPM240GT100 cake core [58..71] pin connects Tx [0..13] pin of AD9862 cake core; Link to each other with TMX320DM6467 processor 2 respectively with power supply signal from the sequential of sequential and logic control element 8 and control signal from power subsystem 7.

Under the effect of the sequential of sequential logic control unit 8 and control signal; The digital signal of the B.PIN of EPM240GT100 cake core [58..71] pin output gets into TMX320DM6467 processor 2 through TMX320DM6467 processor 2 pin D2 (DRO) in the signal input and output control unit 1; Carry out special blind separating treatment at this; Separate into interference signal and signal of communication, the signal output buffer 4 after separating is outputed to signal input and output control unit 1; Intermediate data in the blind separation separation process is stored in the memory cell 5,6 by data/address bus through the address bus addressing.

To the sequential of the EPM240GT100 cake core of signal input and output control unit 1, AD9862 cake core and control signal, to the sequential and the control signal of TMS302C6467 processor 2, link to each other with the EPM3128ATC100 chip of timing control unit 8 respectively with 3.3V power supply 10 with control signal to the sequential of memory cell 5,6.

Timing control unit 8 mainly is to whole device clock and control signal to be provided.This unit needs the 3.3V power supply, produces input and output unit EPM240GT100 cake core, the needed sequential of AD9862 cake core and control signal, TMS302C6467 processor 2 needed sequential and control signal and needed sequential of memory cell and control signal.

Referring to Fig. 5, the data/address bus PD [7..O] of the AM29V400 chip of FLASH memory 6 connects the data wire in the TMX320DM6467 processor 2, and address bus PA [19..O] connects the address wire in the TMX320DM6467 processor 2; The data/address bus DD [31..O] of the 7EA41D9GPX chip of data storage 5 connects the data wire in the TMx320DM6467 processor 2, and address bus DA [19..O] connects the address wire in the TMX320DM6467 processor 2.This unit also links to each other with control unit 8 with sequential.

Mainly form with reference to figure 7 power subsystems 7 by this PT6392C power supply chip.The pin of power supply chip PT6392C [4,5,6] connects 5V input power supply, and pin [12,13,14,15] connects 3.3V output, and pin [18,19,20,21] connects 1.2V output.There is external power source 5V to be provided power supply signal, through these unit 10 conversions, needed 3.3V of output device and 1.2V power supply signal to this power subsystem IO.

Referring to Fig. 7; The circuit of the output sub-module of signal input and output control unit 1 is: the pin B.PIN [40..55] of an EPM240GT100 cake core connects from the signal through the FIFO buffering of the E2 output of TMX320DM6467 processor; The B.PIN of EPM240GT100 [58..71] pin links to each other with Tx [0..13] pin of AD9862 cake core; Signal outputs to amplifier after the D/A conversion in the AD9862 cake core, be input to terminal equipment through amplifier again.Link to each other with EPM240GT100 cake core, AD9862 cake core from the signal of sequential and control unit 8.

Under sequential and control signal effect that sequential and control unit 8 provide to this unit 7; Get into EPM240GT100 cake core through FIFO by B.PIN [40..55] pin from the separation signal (digital signal) of the E2 of TMX320DM6467 processor output; After in the EPM240GT100 cake core, carrying out tissue treatment, get into the AD9862 cake core, in the AD9862 cake core, carry out the D/A conversion; Output then, the output signal outputs to voice-output device again after amplifier amplifies.

With reference to accompanying drawing 7, blind separation process is divided into centralization, albefaction and simple component and extracts several steps.

(1) centralization

At first to detected aliasing signal x=(x ₁, x ₂) centralization, through deducting mean vector m=E (x), can make x is one 0 average variable, the signal s=(s that then separates ₁, s ₂) also will be one 0 mean vector, aliasing signal x produces behind the aliasing in transmission course through primary signal s, i.e. x=As, A is the aliasing matrix.

(2) albefaction

Then need carry out albefaction to observation vector x; Target is to obtain a vector

; Its element is incoherent and variance is 1, that is to say

be orthogonal matrix (function E () representes mathematic expectaion)

$E\left(\tilde{x}{\tilde{x}}^T\right)=I$

carried out feature decomposition, can get

$E\left(\tilde{x}{\tilde{x}}^T\right)={\mathrm{EDE}}^T$

Wherein, E is a characteristic vector, and D is the diagonal matrix of characteristic value, D=diag (d ₁, d ₂).Notice,

can utilize sampled value to estimate to obtain, so albefaction can be expressed as

$\tilde{x}=E{D}^{1/2}{E}^{T}x$

Wherein, D ^1/2=diag (d ₁, d ₂).Checking easily $E\left(\tilde{x}{\tilde{x}}^T\right)=I.$

So, obtained a new aliasing matrix

after the albefaction, promptly

$\tilde{x}=E{D}^{1/2}{E}^T\mathrm{As}=\tilde{A}s$

Can find that

also is an orthogonal matrix

$E\left(\tilde{x}{\tilde{x}}^T\right)=\tilde{A}E\left({\mathrm{ss}}^T\right){\tilde{A}}^T=\tilde{A}{\tilde{A}}^T=I$

In fact, albefaction has reduced the dimension of data.

(3) simple component extracts

A) select an initial weight vector w

B) make the adjustment of w self adaptation

w ⁺＝E(xg(w ^Tx))-E(g’(w ^Tx))w

Have for complex signal:

w ⁺＝E(x(w ^Tx)*xg(w ^Tx))-E(g(w ^Tx)+|w ^Tx| ²g’(|w ^Tx| ²))w

C) normalization w

w＝w ⁺/‖w ⁺‖

If do not restrain (be old w and new w upgrade direction inconsistent), then return b) continue.

Iteration is gone down and just can be isolated primary signal s like this, and the present invention adopts special-purpose high performance floating type dsp chip TMx320DM6467 to realize Blind Signal Separation.

Claims (1)

1. the anti-butt tape processing unit of the blind separation of communication system comprises processor (2); Data storage (5); FLASH memory (6); The input signal collecting unit; Input signal to the two-way band disturbs is separated the mediation down-conversion; It is characterized in that this device also comprises signal input and output control unit (1), input FIFO (3) and output FIFO (4), be input to signal input and output control unit (1) after the signal of communication that two-way has an interference passes through radio-frequency module collection and down-conversion; Be stored in input FIFO (3) after two paths of signals comes out from this unit again, adopt blind separating method that two paths of signals is separated into interference signal and signal of communication, be input to simultaneously among the output FIFO (4) by processor (2); At last, transfer to signal input and output control unit (1) again, interference signal and signal of communication are differentiated, with blind signal of communication output of separating through the decision logic of an interference and signal; Processor (2) adopts the TMS320DM6467 processor; The data/address bus BED [0..7] of processor (2) and AED [32..63] are connected the data wire of data storage (5) and program storage (6) respectively; The address bus BEA [1..20] of processor (2) and AEA [3..22] are connected the address wire of data storage (5) and program storage (6) respectively; FIFO (4) is exported in the CE1 connection among its external memory interface EMIFA, CE2 connects input FIFO (3), and TMS320DM6467 processor (2) is communicated with the sequential and the control signal of coming from timing control unit (8) respectively and reaches from the next power supply signal of power subsystem (7); The signal of communication that is disturbed carries out Blind Signal Separation at TMS320DM6467 processor (2), and the intermediate data in the separation process is stored in the data storage (5) by data/address bus through the address wire addressing; Signal input and output control unit (1) comprises fpga chip EPM240GT100; The input signal collecting unit comprises the AD9862 cake core; Two band interference signals are linked the AUX_ADC_A1 pin and the AUX_ADC_B1 pin of AD9862 cake core through amplifier separately in previous stage; The D of AD9862 cake core [0..11] A, D [0..11] B pin are connected to B.PIN [15..38] pin of the EPM240GT100 cake core in the signal input and output control unit (1), and the signal that comes from timing control unit (8) is transferred on AD9862 cake core and the EPM240GT100 chip; Under clock and control signal effect that timing control unit (8) comes; Two band interference signals are respectively through amplifying input AD9862 chip; In the AD9862 chip, carry out the A/D conversion, output to B.PIN [15..38] pin of the EPM240GT100 chip of signal input and output control unit (1) then; The signal of communication that has interference is made into one road signal through in input FIFO (3) the input TMS320DM6467 chip with the two paths of signals alternate group in said EPM240GT100 cake core, in the TMS320DM6467 cake core, carry out Blind Signal Separation; Signal after the TMS320DM6467 chip carries out blind signal separation is transferred to output FIFO (4); Be input to the EPM240GT100 cake core through the B.PIN of EPM240GT100 [40..55]; After in the EPM240GT100 cake core, isolating interference signal and signal of communication; Signal from the output of B.PIN [58..71] pin of EPM240GT100; Be input to Tx [0..13] pin of AD9862 cake core, in the AD9862 cake core, after the D/A conversion, output to amplifier, be input to terminal equipment through amplifier again; Data storage (5) adopts 7EA41D9GPX type memory, and FLASH memory (6) adopts AM29V400 type memory; The data/address bus PD [7..O] of AM29V400 connects the data wire of TMS320DM6467 processor; Address bus PA [19..0] connects the address wire of TMS320DM6467 processor; The data/address bus DD [31..0] of data storage 7EA41D9GPX connects the data wire of TMS320DM6467 processor, and the address bus DA [19..0] of 7EA41D9GPX connects the address wire of TMS320DM6467 processor; Aforementioned two memories link to each other with control unit with sequential; When system program is downloaded; Program code is through address wire PA [19..0] addressing; Download among the FIASH memory AM29LN400 through data/address bus PD [7..0]: the intermediate data in the processing procedure then through address bus DA [9..0] addressing, is stored among the data storage 7EA41D9GPX through data/address bus DD [31..0].

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