CN101379739A - Technology for reducing electromagnetic interference - Google Patents
Technology for reducing electromagnetic interference Download PDFInfo
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- CN101379739A CN101379739A CNA2005800473521A CN200580047352A CN101379739A CN 101379739 A CN101379739 A CN 101379739A CN A2005800473521 A CNA2005800473521 A CN A2005800473521A CN 200580047352 A CN200580047352 A CN 200580047352A CN 101379739 A CN101379739 A CN 101379739A
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Abstract
Methods and systems are provided for reducing EMI by modifying digital signals using power spread signals to generate digital signals having reduced EMI.
Description
Background
Open field
The disclosure relates to the general field of electromagnetic interference and radiated emission, relate in particular to the technology that reduces electromagnetism and radiated emission.
Description of Related Art
Along with performance characteristics/more and more faster microprocessor more and more is integrated in computer, communication equipment and the senior entertainment systems, clock distribution has become in the design of these systems more and more important problem.These strengthen the clock oscillator need incorporate upper frequency usually into because clock speed with the speed of microprocessor processes information be directly proportional.Yet the device of support high-frequency clock and data path is easy to be subjected to the influence of inside and external radiation problem.For example, computer, telecommunications and entertainment systems have responsive audio frequency, video and graphics circuitry, and its performance can be subjected to the influence of inner EMI radiation.In addition, excess internal EMI radiation makes the degrading quality of video, audio frequency and figure, and causes the system sequence mistake.Has the problem that EMI misgivings in the external device (ED) of high clock and data rate have proposed FCC (FCC) compliance argument, because these systems and device usually have the requirement of electromagnetic interference (EMI).
Generally speaking, in order to make the radiation EMI level remain on the expectation level, consider for FCC purpose or inherence, Computer System Design person usually adopts such as slower clock, control rising and trailing edge, utilizes spread spectrum clock that the method for (SSCG) takes place, and/or technology such as shielding.Though in these EMI reduction technology each effective in varying degrees, the restriction that it is also followed separately.
For example, shielding needs to use expensive conductive material to prevent that institute's radiation emitted from leaking into the outside of the shell that is shielded.Yet this has increased the thermal accumlation of computer-internal, and it can be owing to the air-flow or the deficiency in draught that reduce aggravate.
Slower clock, data rising and trailing edge and SSCG etc. other method all cause reducing of sequential allowance and other problem.The sequential allowance reduce for the vital High Speed System of system sequence normally unfavorable.The sequential that realizes the system of SSCG requires further to be subjected to just being based on the restriction of the analog signal generation of frequency modulation with the shake of reduction EMI emission.In addition, these EMI reduction methods are all uncontrollable.That is EMI reduces and can not be programmed under the situation that can influence system sequence sharply.In addition, these methods are neither can prevent fully at computer-internal generation radiation problem.
Therefore, a method that overcomes these problems will be useful.
Brief Description Of Drawings
By with reference to the accompanying drawings, can understand the present invention better, and can make its numerous purposes, feature and advantage apparent for those skilled in the art institute.In different accompanying drawings, use same reference numerals to indicate similar or identical entry.
Fig. 1 is the simplified block diagram that presents according to the general survey of the method for the generation expanding digital clock signal of at least one embodiment of the present disclosure.
Fig. 2 is the chart of explanation according to the distribute power of the frequency component of at least one embodiment of the present disclosure.
Fig. 3 is the block diagram of explanation according to the realization of the sending module of at least one embodiment of the present disclosure.
Fig. 4 is the block diagram of explanation according to an embodiment of the pseudo-random noise generator of at least one embodiment of the present disclosure.
Fig. 5 is for illustrating according to the random digit noise generator of at least one embodiment of the present disclosure or the block diagram of code generator.
Fig. 6 is the block diagram of explanation according to the received power expansion module of this disclosed at least one embodiment.
Fig. 7 is the block diagram of explanation according to another realization of the received power expansion module of at least one embodiment of the present disclosure.
Fig. 8 is this block diagram according to the more specific embodiment of the received power expansion module of at least one embodiment of the present disclosure of explanation.
Fig. 9 is the block diagram of explanation according to another realization of the received power expansion module of at least one embodiment of the present disclosure.
Figure 10 is the block diagram of explanation according to the application that utilizes the power expansion notion of at least one embodiment of the present disclosure.
Figure 11 for explanation according to the generation of at least one embodiment of the present disclosure flow chart through the method for expansion of digital signal.
Figure 12 is the flow chart of explanation according to the EMI reduction method of at least one embodiment of the present disclosure.
Figure 13 is the flow chart when signal satisfies the method for specified criteria of determining according at least one embodiment of the present disclosure.
Figure 14 is the flow chart of explanation according to the method for the transformation digital bit stream of at least one embodiment of the present disclosure.
Figure 15 is the block diagram of explanation according to the expansion of digital signal system that realizes of at least one embodiment of the present disclosure in circuit arrangement.
Figure 16 and 17 is the block diagram that be used for random delay introduced the module of digital signal of explanation according at least one embodiment of the present disclosure.
Figure 18 and 20 is the block diagram of explanation according to the exemplary realization of the noise source of at least one embodiment of the present disclosure.
Figure 19 is the oscillogram of explanation according to the operation of the noise source of Figure 18 of at least one embodiment of the present disclosure.
Figure 21 to 23 is the block diagram of explanation according to the parallel transmission of many power expansion digital signal of at least one embodiment of the present disclosure.
Figure 24 is the oscillogram of explanation according to the operation of the system of Figure 21 of at least one embodiment of the present disclosure.
Figure 25 to 28 is the block diagram of explanation according to the initialization procedure of at least one embodiment of the present disclosure.
Figure 29 is the block diagram of explanation according to the circuit arrangement with power expansion receiver and transmitter of at least one embodiment of the present disclosure.
Specifying of preferred embodiment
In first aspect, this method can comprise uses the first power expansion digital noise signal to transform first digital signal, and uses this first power expansion digital noise signal to transform second digital signal.This method also can be included in the very first time provides first digital signal through transforming exporting first transmission line to, and provides second digital signal through transforming to export second transmission line in second time that is different from this very first time.
In second aspect, this method can comprise uses one or more power expansion digital noise signals to transform a plurality of digital signals, and provides these a plurality of each in transforming digital signal to export a corresponding transmission lines in the plurality of transmission lines to.Providing of at least one subclass of these a plurality of digital signals each can be delayed with respect to the providing of other one or more digital signals in these a plurality of digital signals.
In the third aspect, this system can comprise a power expansion module, this power expansion module comprises a plurality of inputs, in these a plurality of inputs each receives a corresponding digital signal in a plurality of digital signals, and this power expansion module further comprises a plurality of outputs, each output provides the numeral of a corresponding digital signal in these a plurality of digital signals, and wherein this numeral can be represented this corresponding digital signal through a power expansion digital noise signal transformation.This system can further comprise an outlet terminal, this outlet terminal comprises a plurality of inputs, each input operationally is coupled to the corresponding output of this power expansion module, and this outlet terminal further comprises a plurality of outputs, each output corresponding to a corresponding input a numeral that receives via this input is provided a corresponding transmission lines to the plurality of transmission lines.This outlet terminal can operate so that providing with respect to the providing of numeral of other one or more transmission line and be delayed the numeral of one or more in these transmission lines.
In fourth aspect, this method can comprise: operation one digital noise generator is in init state between the very first time and second time; This digital noise generator of operation is in effective status between second time and the 3rd time; Transform a dagital clock signal based on the output of this digital noise generator; And between this very first time and the 3rd time, provide this dagital clock signal through transforming.
In aspect the 5th, this method can comprise reception one digital signal, this digital signal is represented first dagital clock signal in first period, and represent the dagital clock signal through transforming second period after following this first period closely, wherein this dagital clock signal through transforming is through the expression of first dagital clock signal of the first power expansion digital noise signal transformation; Detect this digital signal from representing that this first dagital clock signal is to the transition of representing this dagital clock signal through transforming; Reaching based on detecting this transition uses one in this first dagital clock signal or this dagital clock signal through transforming to come a synchronous local clock.
In aspect the 6th, this system can comprise: a noise source, and it comprises that an output is to provide a power expansion digital noise signal; And a multiplier, it comprises that a first input end that operationally is coupled to the output of this noise source, receives second input of dagital clock signal, an and output that operationally is coupled to transmission line.This system also can comprise a timer, it comprises that a first input end and that receives the control excitation operationally is coupled to the output of this noise source, and wherein this timer can be operated to be activated at first o'clock this noise source of interim operation based on this control and be in init state.
In aspect the 7th, this system can comprise: a noise source, and it comprises an output so that the first power expansion digital noise signal to be provided; And a multiplier, it comprises a first input end and that operationally is coupled to the output of this noise source and operationally is coupled to a transmission line with second input that receives first digital signal, an and output that operationally is coupled to phase-locked loop (PLL).This system also can comprise a clock detector, it comprises that one operationally is coupled to this transmission line with the input that receives this first digital signal, an and output that operationally is coupled to this noise source, wherein this clock detector can be operated so that this noise source is maintained init state, till this clock detector detects transition in this first digital signal.This system can further comprise: this first digital signal first before this transition represents a dagital clock signal, and and the second portion of this first digital signal represent this dagital clock signal through the second power expansion digital noise signal transformation.
In eight aspect, this circuit arrangement can comprise that a circuit substrate, is deployed in the transmission line at this circuit substrate place, and a transmitter that is deployed in this circuit substrate place.This device also can comprise: first noise source, and it comprises an output, this output is in order to provide the first power expansion digital noise signal; And an encoder, it comprises that a first input end that operationally is coupled to the output of this first noise source, receives second input of first digital signal, and one operationally is coupled to this transmission line so that the output of second digital signal to be provided.This encoder can be operated to use this this first digital signal of first power expansion digital noise signal transformation to generate this second digital signal.And this device can further comprise: a receiver, and it is deployed in this circuit substrate place, and comprises that second noise source of separating with this first noise source, this second noise source comprise that an output is to provide the second power expansion digital noise signal; And a decoder, it comprises that a first input end, that operationally is coupled to the output of this second noise source operationally is coupled to this transmission line receiving second input of this second digital signal, and an output that three digital signal is provided.This decoder can be operated to use this this second digital signal of second power expansion digital noise signal transformation to generate this three digital signal, and wherein this three digital signal can be represented this first digital signal.
In aspect the 9th, this device can comprise many delay paths, and each delay path comprises that one receives the input of first digital signal, reaches the delay cell about the different numbers of other delay path in these many delay paths.This device also can comprise: a pseudorandom number generator, and it comprises an output; And a multiplexer, it comprises a control input end, a plurality of signal input part and an output.Each signal input part can operationally be coupled to a corresponding delay path in these many delay paths, and this multiplexer can be operated to select a signal that receives via one of these a plurality of signal input parts to provide to this output based on this control input end.
In aspect the tenth, this method can comprise: more than first digital noise power expansion of time division multiplexing signal is to produce the first digital multiplexing noise signal; Transform first digital signal based on this first digital multiplexing noise signal; And provide this first first digital signal to export a transmission line to through transforming.
In the tenth one side, this method can comprise the digital signal that receives once transforming, and this digital signal through transformation is represented first digital signal through the first digital noise power expansion signal transformation.This method can further comprise: a plurality of digital noise power expansion of time division multiplexing signal is to produce the second digital noise power expansion signal that equals this first digital noise power expansion signal substantially; And transform this digital signal to generate second digital signal of this first digital signal of expression through transforming based on this second digital multiplexing noise signal.
In aspect the 12, this system can comprise more than first noise source, and each noise source has an output so that a digital noise power expansion signal to be provided.This system also can comprise first multiplexer, it has an output, a control input end and a plurality of signal input part, each signal input part operationally is coupled to the output of a corresponding noise source in this more than first noise source, and wherein this first multiplexer can be operated to be provided at the signal that one of these a plurality of signal input parts are located to receive based on a control signal that receives via this control input end to this output.This system can further comprise: first control module, its have an output to provide this control signal to this first multiplexer so that these digital noise power expansion signals that this first multiplexer comes time division multiplexing to be provided by this more than first noise source are provided; And first multiplier, it has one in order to the first input end that receives first digital signal, and second input that operationally is coupled to the output of this first multiplexer, and an output.
In aspect the 13, this method can comprise: use the first power expansion digital noise signal transformation, first digital signal; Use is different from the second power expansion digital noise signal transformation, second digital signal of this first power expansion digital noise signal; Provide this first digital signal to export first transmission line to through transforming; And provide this second digital signal to export second transmission line to through transforming.
In aspect the 14, this system can comprise: first noise source, and it has an output that the first power expansion digital noise signal is provided; And second noise source, it has an output that the second power expansion digital noise signal is provided.This system also can comprise the first power expansion module, it has an input that receives first digital signal, an and input that operationally is coupled to the output of this first this noise source, and an output, this output provides first numeral through this first digital signal of the first power expansion digital noise signal transformation.This method can further comprise the second power expansion module, it has the input that an input and that receives second digital signal operationally is coupled to the output of this second noise source, and an output, this output provides second numeral through this second digital signal of this second power expansion digital noise signal transformation.
In aspect the 15, this method can comprise: receive first digital signal; Receive a plurality of power expansion digital noise signals; Use the part of a part of at least one subclass of these a plurality of power expansion digital noise signals to transform this digital signal successively, till detecting a predetermined sequence in the very first time; And follow closely after this very first time, use and transform this digital signal to generate second digital signal at this very first time employed power expansion digital noise signal.
In aspect the 16, this system can comprise a plurality of noise sources, and each noise source has an output that power expansion digital noise signal is provided.This system also can comprise an input selection module, and this input selects module to have a plurality of inputs, and each input operationally is coupled to the output of a corresponding noise source in these a plurality of noise sources; And an output, it can be operated to be provided in these power expansion digital noise signals that one of these a plurality of inputs locate to receive.This system can further comprise: a signal transformation module, it has an input, that operationally is coupled to the output of this input selection module and operationally couples to receive the input of first digital signal, and an output, this output provides the numeral by this first digital signal of the signal transformation that receives through this input; And a comparison module, it has an output that may be operably coupled to this signal transformation module receiving the input of this numeral, and an output, and this output provides the result's that the part of this numeral and a predetermined sequence are compared indication.This input selects module can operate to select each in these a plurality of inputs so that export successively.
In aspect the 17, this method can comprise first digital signal of reception expression through second digital signal of the first power expansion signal transformation; And control excitation in response to one and transform this first digital signal to produce three digital signal based on the second power expansion signal of a realization first power expansion function, wherein this three digital signal can be represented this second digital signal.
In the tenth eight aspect, this system can comprise first input end to receive first expression of a digital signal, and wherein the power of first of this digital signal expression is expanded with respect to this digital signal based on the first power expansion signal.This system can further comprise a decoder module, it comprises that one is coupled to second input, the 3rd input of this first input end, and one provide first output of second expression of this digital signal in response to the control excitation that receives at the 3rd input end, wherein first expression of this second expression this digital signal that is the second power expansion signal transformation of expression through being substantially equal to this first power expansion signal.
In aspect the 19, this method can comprise: via first transmission line, receive the first power expansion signal that first digital signal of the first power expansion digital noise signal transformation is used in an expression.This method also can comprise uses the second power expansion digital noise signal that is substantially similar to this first power expansion digital noise signal to transform this power expansion signal is substantially similar to this first digital signal with generation second digital signal.This method can further comprise: use the 3rd this second digital signal of power expansion digital noise signal transformation generating the second power expansion signal, and provide this second power expansion signal to export second transmission line to.
In aspect the 20, this circuit arrangement can comprise: one operationally is coupled to the input of first transmission line, and an output that operationally is coupled to second transmission line.This device also can comprise a decoder, this decoder comprises first input end, and this first input end operationally is coupled to the input of this circuit arrangement to receive the power expansion signal of representative through first digital signal of the first power expansion digital noise signal transformation.This device can further comprise: second input, and it receives the second power expansion digital noise signal, and wherein this second power expansion digital noise signal is substantially similar to this first power expansion digital noise signal; And an output, it provides second digital signal that is substantially similar to this first digital signal.This device can further comprise an encoder again, and this encoder comprises: first input end, and its output that operationally is coupled to this decoder is to receive this second digital signal; Second input, it receives the 3rd power expansion digital noise signal; And an output, its output that operationally is coupled to this circuit arrangement for the second power expansion signal so that export this second transmission line to.
An embodiment of the present disclosure provides the method for a kind of gate Direct swquence spread spectrum (GDSSS) clock distribution, and wherein an original clock signal or other digital data signal are divided and expand on a broad spectrum to reduce radiated emission.As used herein, clock is defined as the timing unit based on integrated circuit.In one embodiment, clock signal is through introducing the power expansion signal transformation of little phase shift.These phase shifts can be at random, pseudorandom, nonlinear, based on multinomial series, like that.Different with typical expanding system solution, these frequency hoppings of expansion energy spectrum (EMI) can take place on the frequency of clock.
This paper quotes from term power expansion signal and term noise source widely.Power expansion signal (this paper also is called the digital noise signal) comprises to be expected in the digital signal of this power expansion signal transformation introduces phase shift any with in the various digital signals that reduce this EMI through transforming digital signal.The example of power expansion signal comprises: pseudorandom number noise signal, random digit noise signal, Gaussian digital noise signal, nonlinear extensions signal, multinomial series, and like that.In addition, the power expansion signal can comprise the combination of a plurality of power expansion signals.
As will be from following discloses with apprehensible, noise source comprises can operate any with in the various assemblies that produce one or more power expansion signals or its combination.For purposes of illustration, the noise source that produces the pseudorandom number noise signal can comprise and for example can use linear feedback shift register (LFSR).One noise source that produces random noise signal can comprise for example quadratic residue code sequencer.Provide the noise source of nonlinear extensions signal can comprise for example Golomb code generator.Provide the noise source of multinomial series can comprise for example elliptic curve generator.
Can understand the disclosure best with reference to the specific embodiment that this paper is illustrated.Particularly, Fig. 1 illustrates the block diagram of oblatio according to an embodiment of clock distribution network of the present disclosure system.In order to be easy to discuss, example technique disclosed herein is to describe in the background via single-ended transmission Channel Transmission signal.Yet these technology can be incorporated other signal into and receive and transmission technology, such as the differential pair transmission channel.Therefore, unless otherwise, otherwise the citation of single-ended transmission line or channel also is applicable to differential pair transmission line or channel and can depart from spirit of the present disclosure or category.
In operation, the signal that is denoted as clk/ data 101 is received at input 110 places.For the purpose of discussing, signal clk/ data 101 can be called clock signal 101 or data-signal 101 and discuss being easy to.Can understand, when being called clock 101, this key element represents that one comprises the digital signal of basic fixed frequency.On the contrary, when being called data 101, this key element comprises an above frequency component.
When being received at transmitter power expansion module 112 places, clock/data-signal 101 by with the transformation of power spread signal providing through expansion of digital signal 103 to output 114, this output 114 and then be coupled to transmission line 116.Represent by the line in the chart of Fig. 2 203 through expansion of digital signal 103, its indication is compared with original clock/data, the emission of clock/data-signal 101 (line 201) has been expanded on bigger frequency spectrum (line 203), reduced EMI by this and to the potential for adverse effects such as other frequency spectrum of video spectrum 200.
It is non-wireless transmission medium that transmission line 116 generally is illustrated as, such as the non-wireless transmission medium of lead, printed circuit board trace, coaxial cable, integrated circuit trace or any other form.As mentioned above, it is right that transmission line 116 can comprise the single transmission line that for example is used for carrying spread signal 103 or be used for the differential lines of carrying spread signal 103.
Receiver power expansion module 120 receives through expansion of digital signal 103 and produces clk/ data-signal 105, and this clk/ data-signal 105 is the expression of original clk/ data-signal 101.Look specific implementation, clk/ data-signal 105 can have known phase relationship with clk/ data-signal 103, or can be asynchronous with respect to clk/ data-signal 103.To more preferably understand the specific implementation that is associated with the system of Fig. 1 referring to Fig. 3 to 10.
Fig. 3 explanation is according to a kind of realization of the sending module 142 of an embodiment of the present disclosure.As Fig. 3 finding, sending module 142 comprises input and transforms module 144 and noise source 146.Noise source 156 can comprise any one in the various noise sources that the power expansion signal can be provided.The example of noise source includes but not limited to pseudorandom number noise generator (such as linear feedback shift register or title LFSR), random digit noise generator, multinomial generator, quadratic residue code sequencer or oval curve generator.In another embodiment, noise source 146 can be the Gaussian digital noise generator.Thereby noise source 146 can adopt a series of registers to produce noise states and transform module 144 to input binary stream is provided, as hereinafter with more detailed argumentation.
In operation, clock signal 101 is provided to input via input 110 and transforms module 144.Clock signal 101 also can be provided to noise source 146, as by indicated to the dotted line of noise source 146 from input 110, perhaps can use an independent clock to drive pseudo-random noise generator 146, such as when signal 101 is data-signal.In one embodiment, the noise states 149 of noise source 146 in order to generate a random sequence, it is used for a power expansion digital noise signal that comprises binary data stream usually is provided in output 148, transforms module 144 for input and produces through expansion of digital signal 103 in order to promote self-clock 101.
After the power expansion signal that is provided by noise source 146 was provided, input was transformed module 144 and is transmitted through expanding digital clock signal 103 via output 114 other module in system.In one embodiment, noise source 146 comprises a look-up table.In another embodiment, noise source 146 can be linear feedback shift register (LFSR).In another embodiment, the access of question blank or the status switch of LFSR can carry out gate or control producing any repeat mode of being wanted number by logic, as referring to the further argumentation of Fig. 4.In one embodiment, the number of repeat mode is selected as the even number state so that use phase-locked loop (PLL) circuit that has the even number divider in its feedback loop, and the even number divider is easier to realize than odd number divider.
Fig. 4 illustrates an embodiment of the pseudo-random noise generator 156 (the exemplary realization of noise source 146) that uses gate pseudo random number (PRN) generator 157, and gate pseudorandom number generator 157 can use LFSR to realize.Gating pulse generator 158 is kept counting or state based on the number of the pulse that receives in its input place, and PRN generator 157 searching loops, one sequence state and based on these states output random binaries stream B.In response to the pulse that receives predetermined number, gating pulse generator 158 generates a reset signal to pseudorandom number generator 157, and therefore pseudorandom number generator 157 is reset or is initialised to an initial value, and begins this status switch of searching loop once more.
In one embodiment, gating pulse generator 158 resets pseudorandom number generator 157 to allow to generate the even number state.Gating pulse generator 158 also can be programmable, so that the number by state in the sequence of pseudorandom number generator 157 generations can be by a system (for example, application drives device or system bios) or select by user's (for example, based on program state or by external pin).By the number of change with pseudorandom number generator 157 associated state, just can change the degree that EMI reduces, as described herein.
In this way, what generated can " upwards expand " to the frequency that is higher than original clock 101 through expansion of digital signal 103, or " expansion downwards " is to the frequency that is lower than original clock 101.By promoting upwards expansion and expansion downwards, removable EMI emission makes it away from critical frequencies.
Come the clock pulse of involution/remove module 153 and synthetic by multiplier 159 to produce through expansion of digital signal 103 from the random binary stream of pseudorandom number generator 157.In one embodiment, use XOR (XOR) door to realize multiplier 159.
Fig. 5 illustrates the block diagram 162 of an alternative embodiment of transmitted power expansion module.In one embodiment, grow into 2 such as the code generator life of maximum-length shift register sequence generator or M sequencer 166 (the exemplary realization of noise source)
MThe random code of-1 state, wherein M is the number of register stage 163, trigger 163 or storage unit 163 in the device 166.In another embodiment, to generate length be 2 to last current state to maximum-length shift register sequence generator 166 by decoder 167 is decoded
MThe random code of individual state.For example, if realized four registers or trigger 163 (M=4), then sending 15 bits (for example, 2
MAfterwards-1 bit), this repetitive sequence will be finished, and then begin repetition himself.
If used four registers---for example trigger 163 (M=4)---, and need the even number state, the last current state in these repetitive sequences of decoder 169 decoding then, and insert an extra initial condition and---such as this last current state---, thus this sequence is repeated 2 a state of adding is added into this sequence
MIndividual circulation but not 2
M-1 circulation is used common as the DSSS that uses cdma communication.
Can understand, grow into 2 such as the pseudorandom number generator life of maximum-length shift register sequence generator or m sequencer 166
MThe random code of-1 bit, wherein M is the number with buffer status of feedback connection.The initial code that is loaded on each register 163 is whole 2
MOnce circulate to finish a pseudorandom bit stream in the displacement of-1 subsequence to the bit that shifts left.Register (it typically is one or more, the input of this circuit that is connected in each M trigger 163 and/or one or more XOR gate of output, and be not described among the figure) in M element between feedback circuit guarantee that the state of this M bit when being shifted each time changes, so that this M bit transition is become 2
M-1 pseudorandom repetition bits stream.Therefore, this device before beginning to repeat this sequence once more with searching loop all possible 2
M-1 serial flow bit status.In essence, in this M bit device, per 2
M-1 displacement, the shift register displacement just is back to reset condition or binary value.In practice, M can be any number and is generally number greater than three.
The pseudo random binary stream that multiplier 161 receives from the output of FF4.From of the expression of M bit counter 167 receive clocks 101 at low frequency.Be synthesized at multiplier 161 places to produce in the expression of the clock 101 of the output of counter 167 and pseudo random binary stream through expansion of digital signal 103 from module 166.In case should be through expansion of digital signal 103 by sending such as the illustrated transmitted power expansion module of Fig. 3 to 5, this---such as the module 120,122 or 170 of Fig. 1---locates to be received just in receiver power expansion module through expansion of digital signal 103.
In addition, at least one embodiment, noise source 146 can be configurable, so that use different input codes to use when the generted noise signal.For the purpose of illustrating, the input of each can be connected to the output of a corresponding multiplexer in M trigger 163, wherein each multiplexer with the output of original state or with the output of original state and highest significant position XOR (or XNOR) with noise source as input.Thus, noise signal and therefore EMI signature (signature) can write in one or more register by programming transmitted power expansion module or with a value and change, wherein these register values/this programming has determined to import to the control of multiplexer.Therefore this technology can reduce or eliminate carries out based on the change of making to utilize the needs of new or different noise signals the transmitted power expansion module.Also can understand, the noise source of receiver can be configurable similarly also.
Fig. 6 explanation is in one embodiment corresponding to the received power expansion module 170 of the received power expansion module 120 of Fig. 1.Received power expansion module 170 comprises an input transformation module 174 and a noise source 176.Usually, in all systems as shown in Figure 1, received power expansion module 120 will have the priori of transmitted power expansion module 112.Since the priori of transmitted power expansion module 112, the definite noise source function that received power expansion module 120 known transmitted power expansion modules 112 are realized.
By as realizing in the transmitted power expansion module, in noise source 176, realizing same noise source function, just can recover to be expanded at first to produce clock/data 101 through expansion of digital signal 103.In addition, gained clock 105 can be provided to phase-locked loop (PLL) 175, with generate by the amount that phase-locked loop feedback delay one is equaled insert delay one with original clock 101 synchronously to the clock/data-signals 106 of known phase relationship, it comprises the random number spread signal.
Can understand, received power expansion module 170 generates clock 105 in two steps.First step is an obtaining step, obtains during this first step to expanding the synchronous of clock/data-signal 103.Obtain is by obtaining comparing by the power expansion signal that will import bit stream and noise source 176 on the basis of clock into.If find particular state, random number code or noise states for what mate, then this process continues to determine whether N state+1 also is effectively, otherwise keeps first noise states.If N state is passed through, then proceed to NextState, till having verified all states.Otherwise this process continues first initial condition.Therefore, generate and the noise source 176 that sends expansion module same noise state, just can recover original clock/data 101 in the mode that allows synchronous system operation by providing one.
An advantage of received power expansion module 170 is that any noise of induction also is expanded and is added into the Noise Background of clock signal 105 on the signal 103 of expansion clock/data.The result of this expansion is, any noise pulse on expansion clock/data-signal 103 has very little influence or do not have influence clock recovered 105 or 106.Its favourable part is that under the situation of synchro system, the clock pulse of similar number is identical at the various somes place of system to be desirable.Therefore, by at expansion EMI noise on expansion clock/data-signal 103, just can maintain the clock cyclic number order of transmitted power expansion module place reception and the clock cyclic number order that produces by received power expansion module 170.
Fig. 7 illustrates the another embodiment of received power expansion module 120.Received power expansion module 180 receives through expansion of digital signal 103 at input 118 places that are coupled to marginal detector modulo counter 186.To generate a pulse at its output 181 places, this pulse is used for regenerating original clock 101 as the clock on the output 122 105 by clock recovery module 183 to 186 explanations of marginal detector/modulo counter in the information that receives on expansion of digital signal 103.
Particularly, marginal detector/modulo counter 186 has the priori through expansion of digital signal 103 to receiving.Therefore, marginal detector/modulo counter 186 known through expansion of digital signal 103 in its repetitive sequence, will have what rising clocks along or decline clock edge.For example, for 2
MSequence (wherein M equals 4) based on the initial value that is used for the loading pseudo random number generator, will have the clock transition of fixed number.Therefore, marginal detector/modulo counter 186 comprises a counting device, and it is generating a pulse 187 at every turn when expansion of digital signal 103 counting sequences repeat.For example, suppose for a M value that 12 rising edges altogether will be arranged, then marginal detector modulo counter 186 per 12 clocks are along generating a pulse 187 at output 181 places.
The pulse that generates in output 181 places is provided to and comprises a phase-locked loop and a clock recovery module 183 divided by N counter (not shown), so that regenerate the expression as the original clock 101 of the clock 105 that is illustrated as output 122 places.Yet, will understand, can pick up in the environment of making an uproar of EMI noise through expansion of digital signal 103 therein, the EMI noise can be interpreted as one will cause the unexpected time in the extra rising edge of output 181 places production burst 187.This should cause clock 105 not have fixed frequency, makes thus more to be difficult to realize in synchro system.
The more specific embodiment of the received power expansion module of Fig. 8 key diagram 7.Module 196 common marginal detector/modulo counters 186 corresponding to Fig. 7.Particularly, five triggers 193 are by connected in series, and wherein the most last bit drives reset circuit 194.Reset circuit 194 and then these triggers connected in series 193 (FF1 to FF5) that can reset are so that begin new counting.
Though should be appreciated that, the counter of many types used, but illustrated counter is by operating along the value of asserting of advancing along trigger 193 chains in each effective edge through expansion of digital signal 103 in the module 196.For example, after being caused resetting by reset circuit 194, the value on the output of each trigger 193 will be got not (negated), and meaning promptly, and is zero.Therefore, the multiplier 191 for XOR will provide a low value at its output on the function.First effective edge that after resetting, receives the expansion of digital signal 103 of hanging oneself along the time, will be latched on the output of the first trigger FF1 such as the value of asserting of logic level one.
Because the output of the first trigger FF1 is asserted, therefore existing XOR (XOR) function 191 asserting signal and get signal not that just receiving provides one to assert signal at its output.Through next effective edge of expansion of digital signal 103 after transition, this value of asserting of the output of the first trigger FF1 will be latched in the output of the second trigger FF2, and the value of asserting is latched in the output of the first trigger FF1.Because XOR function 191 has now received two and asserted input, so its output will be got not, will keep this to get for the remainder of this counting sequence denys value.This counting sequence will continue, and receive until the output at trigger five FF5 and assert till the signal, and reset circuit will reset thus, and these have in the trigger 193 of getting value not each.
Can understand, and get not value though marginal detector/modulo counter 196 is described as being reset in one embodiment on its each output, will understand, in other embodiments, reset circuit can be preloaded into a particular value in these triggers 193.In addition, though realized a kind of simple bit counter of advancing, also can realize the counter of other type.
In the above described manner, 191 production bursts 187 (Fig. 7) of XOR module, it is corresponding to the repetition of counting based on an expectation through expansion of digital signal 103 sequences.This pulse 187 is provided to phase detectors 199, this phase detectors 199 and then its output provided to filter 198, this filter 198 and then its output signal provided to VCO 195, this VCO 195 and then its output signal provided to divided by N counter 197 should be fed back phase detectors 199 divided by N counter 197.In this way, can realize that directly relevant with the relative duty cycle of importing pulse into the clock recovery module 183 (Fig. 7) of stabilized wherein is to export clock frequency.
Fig. 9 illustrates the another embodiment of received power expansion module 170.In operation, the received power expansion module of Fig. 9 allows to detect through expansion of digital signal 103, when being detected, is expanded again to recover original clock through the power of expansion of digital signal 103 thus.Yet, when not detecting the existing of digital signal 103, suppose that the just received signal in input 118 places of transforming module 284 in input is the dagital clock signal without expansion, this signal passes through this system but not regenerates through expansion of digital signal 103.
For the operation of the received power expansion module of describing Fig. 9, suppose that this module is initial to occur from the state that resets.When the state that resets certainly occurred, the phase-locked loop that comprises VCO 295 partly was designed to generate one and reasonably approaches the hang oneself output clock of the original clock that expansion of digital signal 103 recovers of expection.Any other module that this clock is provided to noise source 286 and needs to control during start-up course.
Because start-up course, control module 290 remains on a particular state with noise source 286, noise source 286 and then transform module 284 to input a value is provided.For example, logic one (1) can be provided to input and transform module 284 during obtaining sections.Because the received power expansion module of Fig. 9 expecting one have particular signature through expansion of digital signal, so during reset portion is divided, input is transformed module 284 and can be received through expansion of digital signal 103, and by using startup clock that VCO generated to latch corresponding to the sequence through the value of the state of expansion of digital signal 103 that is received.
Just these values or state can be provided to sliding window detector 288 with search one with the predetermined sequence that is associated through expansion of digital signal 103.For example, can have per 16 bit repeating sequences through expansion of digital signal 103, yet, the uniqueness bit sequence that the 288 known existence one of sliding window detector can detect by a subclass that only monitors total bit.Therefore, for example, once may only need to observe three or four bits and just can determine that in fact whether the signal that is receiving contains the signature through expansion of digital signal 103.
When sliding window detector 288 identifies when receiving through expansion of digital signal 103 for certain, signaling control module 290, and make noise source 286 withdraw from and allow its each state of noise source 286 searching loops from resetting.In addition, sliding window detector 288 starts one and generates clock 106 to allow signal from sliding window detector 288 to be passed to phase detectors 299 with the phase-locked loop that allows to comprise element 299,298,295 and 297 to the selection wire of multiplier 291, and this clock 106 is for being expanded to generate the expression through the original clock of expansion of digital signal 103.Notice that in this embodiment, sliding window detector 288 also can be to providing a value divided by N counter 297, this this phase-locked loop of value indication may must be taken advantage of just detected pulse.
Note, because noise source 286 is at all states of generation, and input is transformed module 284 and is being transformed all signals that receive at the expansion of digital signal 103 of hanging oneself, can directly generate clock 106 so module is transformed in input, and walk around sliding window detector 288 and obtain to be used for clock so that this clock to be provided to phase detectors 299.By phase-locked loop feedback delay one is equaled to insert the amount of delay, this clock can be generated as with original clock 101 and have a known phase relationship, it comprises this random number spread signal.
Yet, sliding window detector 288 is never from another embodiment that detects the expection signature through expansion of digital signal 103 therein, can suppose that transforming the just received signal in module 284 places in input is not through expansion of digital signal 103, but real data or the clock signal that should pass through with not changing.In this case, sliding window detector 288 with signaling multiplier 291 this signal is passed to phase detectors 299 at its another input end.Should be appreciated that,, may need to be reprogrammed to allow this signal not passed through with transforming divided by N counter 297 when when the just received clock of input end will be passed to the output of received power expansion module 170.
An advantage that realizes the received power module of the type that Fig. 9 is illustrated is: the known extensions signal can be expanded again to generate an expection clock, or for the situation of wherein wishing not use spread signal, can use ordinary clock and make it pass through this device.
Figure 10 illustrates that one utilizes the concrete application of power expansion notion disclosed herein.To understand, the application of Figure 10 can be numerous application.For example, Figure 10 can represent mainboard, set-top box, camera, printer, audio/video adapter, server or the network equipment.The storage arrangement of Figure 10 is represented RAD, such as dynamic randon access device and static random-access device.When the raising of device speed, during such as use double data speed RAD, the needs that reduce emission also will increase.Particularly, Figure 10 comprises clock driver 302, and it provides cpu clock to (all) CPU 310, and provides the clock or the reference clock that can use for other device such as other CPU, interior slot to chipset 315.The various expressions that chipset 315 can be used for controlling various functions and/or distributes institute's receive clock.
In a specific embodiment, chipset 315 sends a clock 0 to transmitter 320.This transmitter 320 is operated to provide through expansion of digital signal 103 to transmission line 322 in the previous described mode of this paper.In this illustrated specific embodiment, this transmission line 322 comprises such as the trace on the printed circuit board (PCB)s such as mainboard of information processing system.Transmission line 322 is illustrated as and comprises three parts 325,330 and 335.The reason that transmission line 322 is not illustrated as the wall scroll transmission line is, because of socket, connector 340 in existing along this transmission line, so it is discontinuous impedance to take place in the transmission line.This impedance line is discontinuous by transmission line portions 330 expressions.
Because transmission line 330 is discontinuous, the EMI emission can cause receiver 345 places on one of storage arrangement 360 to receive through expanding the expression of making an uproar of clock 103.Can understand, storage arrangement 360 can represent to increase the interior plug-in card of memory of the memory space on the information processing system.In response to receive from transmission line 322 through spread signal 103, receiver 345 will be to expanding through the power of expansion of digital signal 103, to be created on the expression of the original clock signal that transmitter 320 places receive.
As discussed previously, utilize disclosed transmission/receiver to not only reducing the The noise that sends by transmission line 322 as described, and will reduce the The noise that receives by transmission line 322, thereby can provide to memory chip 351 to 359 by the clock signal of receiver 345 generations one cleaning and with it.
Figure 11 is with the method for flow chart formal specification according to a specific embodiment of the present disclosure.At step 402 place, reception one comprises first digital signal of basic fixed frequency.In one embodiment, this first digital signal can be the clock signal that is used for providing to each digital assembly sequencing control.An example of clock signal is trapezoidal substantially waveform.
At step 404 place, based on the first power expansion digital noise signal transformation, first digital signal to produce once expansion of digital signal.Usually, this first power expansion noise signal is provided by a noise source.The example of suitable noise source comprises pseudorandom number generator, pseudorandom Gaussian noise number generator, quadratic residue code sequencer, oval curve generator, nonlinear extensions signal generator, and is like that.By based on power expansion digital noise signal transformation first digital signal, obtain a power be expanded on big frequency spectrum through expansion of digital signal, reduce the influence of EMI thus.
At step 406 place, this is sent out along a non-wireless transmission line through expansion of digital signal.The example of non-wireless transmission line comprises lead, integrated circuit (IC) apparatus trace and printed circuit board trace, and coaxial cable, and is like that.Be provided to receiving system through expansion of digital signal along this non-wireless transmission line.
At step 408 place, receive this through expansion of digital signal from this transmission line at the receiving system place.Then, in step 410, transform this through expansion of digital signal based on the second power expansion signal of a realization second power expansion signal.In one embodiment, the power expansion signal that is utilized in this second power expansion signal and the receiving step 404 is identical.In response to transformation, produce one second digital signal, wherein this second digital signal expression that is first digital signal to this digital signal.
In another embodiment, the power expansion signal that in step 410, utilizes need not utilize with adaptation step in the identical power expansion signal of power expansion signal that utilized.Before disclosed as this paper, can use a counter network to come recovered clock effectively, thus power expansion is back to its primitive form.Similarly, the randomizer that produces identical stochastic regime can be used for transforming through expansion of digital signal to generate second digital signal of expression first signal.
The method of Figure 11 has been represented the progress on prior art, and this progress is and can reduces from the EMI emission via the clock signal of transmission line by expansion harmonic energy on big frequency spectrum.In addition, because institute's clock recovered can be with in any remarkable additional jitter drawing-in system, so clock recovered can be resumed with not introducing extra temporal constraint in this system.
Figure 12 with the flow chart formal specification according to other method of the present disclosure.At step 422 place, reception has first digital signal that an EMI who does not satisfy the EMI target distributes.For example, can receive and notified data or the clock signal of in system, bringing EMI misgivings.In step 424, transform this first digital signal based on a random digit noise signal and have second digital signal of the 2nd EMI distribution of satisfying the EMI target to generate one.An example of EMI target is to be no more than given EMI launching electrical level on a characteristic frequency.By transforming this signal, just can satisfy this EMI and distribute at step 424 place.
At step 426 place, second digital signal is provided to a non-wireless transmission line.The example of non-wireless transmission line comprises electric wire, integrated circuit trace, printed circuit board trace, coaxial cable, and is like that.
At step 428 place, receive this second digital signal from transmission line at the receiving system place.In step 430, transform this second digital signal based on a digital noise signal and have the three digital signal that an EMI distributes basically to generate one.As described earlier in this article, can use the power expansion signal to transform the expression that second digital signal that this power is expanded generates original clock.
Figure 13 is with the method for flow chart formal specification according to an embodiment of the present disclosure.At step 444 place, receive first expression of first clock.At step 444 place, when the power of first signal is expanded based on the first power expansion signal, whether this first signal is satisfied first criterion judge.For example, this first criterion can be: whether first signal causes being similar to a fixed frequency signal of first clock that is generated after its power is expanded.Another example of first criterion will be: whether the process of expanding first signal power causes a stochastic regime sequence of conduct expection stochastic regime sequence.
When judging that this flow process marches to step 446 when step 444 satisfies first criterion.At step 446 place, the power of first signal is expanded to generate secondary signal.This secondary signal is provided to an output node of device to drive other device.In fact, if receive expection through spread signal, then will decode to it, for example, make its power expansion, so that the expression of first clock signal to be provided.
Do not satisfy first criterion if judge first signal, then this flow process marches to step 448, wherein provides one to replace clock signal at output.In one embodiment, a solution of replacing clock signal can be to provide to output node at first signal that step 442 receives, and attempts mat and generates a clock by de-spread (despread) first signal to substitute.Can understand, this specific embodiment favourable be in, it allows extended receiver/sending module to work with the various signals that receive.
Figure 14 is with the method for flow chart formal specification according to a specific embodiment of the present disclosure.At step 452 place, receive and to comprise first digital bit stream with first frequency component of first distribute power.This first digital bit stream can comprise a fixed frequency clock, or comprises the data with first frequency component.
At step 454 place, transform first digital bit stream to produce second digital bit stream based on the first power expansion signal, represent second digital bit stream of this first frequency component with second frequency component with second distribute power.For example, later referring to Fig. 2, the first frequency component of first digital bit stream can be represented by the distribute power 201 of Fig. 2.Can understand, be the occasion of data bit flow at first digital bit stream, and distribute power part 201 will only be represented the unifrequency component that is associated with these data.In case through transforming, the second frequency component with second distribute power is just represented by for example distribute power 203.Be easy to illustrate that distribute power 203 is expanded on the frequency range greater than the frequency range of first digital bit stream.Therefore, realized to produce the bit stream of low EMI emission.
Figure 14 realizes the system of various aspects of the present disclosure with the block diagram formal specification.Can understand, the system of Figure 14 can represent any one in numerous various application.For example, Figure 14 can represent mainboard, set-top box, camera, printer, audio/video adapter, server and/or the network equipment, only enumerates some application herein.
Figure 14 explanation is used for providing to memory 502 and central processor unit (CPU) 505 clock driver 501 of time sequence information.Yet clock driver 501 is not directly to provide fixed frequency signal to memory 502, but is coupled to transmitted power expansion module 521.As described herein, the energy of transmit power module 521 these fixed frequency signals of expansion has the signal that extended power is composed to generate one, and provides this through spread signal to transmission line 523.The receiver module 522 that is coupled to transmission line 523 receives this through spread signal, and the fixed frequency signal of an expression original clock is provided to memory 502.Can understand, receiver module 522 can be the part of storage arrangement 502, and sending module 521 can be the part of clock driver 501.
In a similar fashion, not that clock driver 501 directly is coupled to CPU505, but clock driver is coupled to transmitted power expansion module 541.As described herein, the energy of transmit power module 541 expansion fixed frequency signals has the signal that extended power is composed to generate one, and provides this through spread signal to transmission line 543.The receiver module 542 that is coupled to transmission line 543 receives this through spread signal, and the fixed frequency signal of an expression original clock is provided to CPU505.Can understand, receiver module 542 can be integrated into the part of storage arrangement 502, and sending module 521 can be integrated into the part of clock driver 501.
Data are transmitted between storage arrangement 502 and CPU by the memory bus that comprises bus segment 516,517 and 518.Usually, storage arrangement 502 will represent to send with the data rate that may cause harmful EMI the high-speed memory of data, as double data rate memory.Therefore, in the illustrated embodiment, each bit line of data/address bus will be benefited from expansion technique disclosed herein.For example, bus segment 516 comprises bit line 512, and it is provided to and the corresponding to power expansion device 535 of the disclosure.Because the data on the memory bus are generally bi-directional data, so power expansion 535 will comprise transmitted power expansion module and received power expansion module usually.Will be based on being to carry out that data are read or data are write and controlled which module and be activated from the control signal of memory/CPU.When module 535 is served as sending module, growth data will be sent to module 536 by bit line 513, and this module 536 is configured to receiver module to receive and to handle through growth data.What received will use identical power expansion signal to expand again to provide initial data to CPU through spread data signal.
Can understand, each element that is not a system all needs to realize extended power technology as herein described.For example, the clock signal that provides to power expansion assembly 503 and 504 is illustrated as and is not expanded.Similarly, because control data is not high-speed data usually,, the control information between CPU 505 and the memory is not expanded so being illustrated as.
Figure 15 illustrates the circuit arrangement 600 of realizing reduction EMI technology disclosed herein.This circuit arrangement 600 comprises circuit substrate 601, and is formed at these circuit substrate 601 places and by the transmitter 603 and the receiver 604 of one or more transmission line, 605 electric couplings.Circuit arrangement 600 comprises among the embodiment of circuit board level device therein, circuit substrate 601 can comprise the circuit board such as printed circuit board (PCB) (PCB), transmitter 603 and receiver 604 can comprise for example integrated circuit (IC) device or monolithic system (SOC) separately, and transmission line 605 can comprise for example PCB trace.Circuit arrangement 600 comprises that among the embodiment of IC device or SOC, circuit substrate 601 can comprise ic substrate therein, and transmission line 605 can comprise the IC trace.In embodiment at least, transmission line 605 for the unique communication path between transmitter 603 and the receiver 604 to be easy to realization circuit arrangement 600 in a system.As described below, this can realize, because some information---such as the transition between power expansion state and the normal condition and employed specific noise source or noise code---can be judged from the output that is provided in the transmitter on the transmission line 605 by receiver, thereby eliminate the needs that transmit this information with a separate lines.
In the illustrated embodiment, transmitter 603 comprises: an input, and its receiving digital signals 607 is such as dagital clock signal or digital data signal; And an output, it operationally is coupled to transmission line 605, and being used for provides and will be represented by the power expansion of the digital signal 607 of transmission line 605 transmission to receiver 604.Similarly, receiver 604 comprises: an input, and it operationally is coupled to transmission line 605 and represents with the power expansion of receiving digital signals 607; And an output, it provides digital signal 608, this digital signal 608 expressions or be substantially equal to input end received digital signal 607 at transmitter 603.
As mentioned above, adopt the transmitter and the receiver of technology disclosed herein can utilize the output in same noise source to transform input signal, represent (as the situation of transmitter or encoder) or represent to recover raw digital signal (as the situation of receiver or decoder) from power expansion with the power expansion that generates input signal.This advantage that has is, is easy to realize single noise source and guarantees the employed transformation signal of transmitter and the employed transformation signal of receiver is generally identical.Yet in some implementations, it may be disadvantageous using single noise source.For example, will understand, and need the additional transmissions line to provide the power expansion signal to transmitter and receiver.This additional transmissions line self may be with in the EMI drawing-in system.In addition, look the length of transmission line, crooked can be that betides the power expansion signal at receiver place is difficult to processing or unacceptable.
Therefore, in one embodiment, transmitter 603 and receiver 604 are realized independent noise source.As described, transmitter 603 can comprise noise source 609 provides power expansion signal 610 with the signal transformation module 611 to this transmitter 603, and signal transformation module 611 uses this power expansion signal 610 to transform input data signal 607 by this.Receiver 604 comprises independent noise source 612 provides power expansion signal 613 with the signal transformation module 614 to this receiver 604, and signal transformation module 614 uses this power expansion signal 613 to transform the data-signal that receives via transmission line 605 by this. Signal transformation module 611 and 614 is implemented as XOR gate usually.
For receiver 604 being recovered equal substantially the digital signal 608 of the digital signal 607 that is received by transceiver 603, the power expansion signal 610 and 613 that is provided by noise source 609 and 612 is preferably basically and equates respectively.Therefore, noise source 609 and 612 is preferably similar realization.In addition, initialization module 615 therein noise source 609 and 612 carry out providing identical seed to each noise source 609 and 612 in the initialized example with seed.In illustrated example, circuit arrangement 600 can realize single initialization module 615 with to noise source 609 and 612 both seed input and/or other initialization input are provided, or can be independently initialization module 615 of transmitter 603 and receiver 604 both realizations.
Figure 16 to 20 explanation is according to the various exemplary noise source of at least one embodiment of the present disclosure.As mentioned above, noise source disclosed herein can realize any in the various power expansion signal generators, or its combination, and can not depart from category of the present disclosure or spirit.Although numerous other noise sources of Figure 16 to 20 explanation realize that those skilled in the art can utilize other noise source of using the policy that this paper provided.
Figure 16 and 17 illustrated example noise sources 620, it comprises multiplexer 622 or has other input selector of a plurality of inputs that operationally are coupled to corresponding many delay paths (delay path 624 to 627 in the illustrated example).Describe as Figure 16, each delay path comprises an input to receive supplied with digital signal 628, and at least one subclass of these delay paths comprises the delay cell of different numbers, and each delay cell is provided at the little delay between its input and its output.For example, delay path 624 to 627 comprises zero, one, two and three delay cell 630 respectively.Therefore, each delay path 624 to 627 to multiplexer 622 output identical but the signal of time shift is arranged about the signal of other delay path output.
At the receiving terminal place, the noise source that is substantially similar to noise source 620 can be used for recovering the similar substantially expression of input data signal 628.In this example, the noise source at receiver place preferably realizes delay path identical with transmitter side 624 to 627 and control input generator 632, removes effectively so that the transformation of data-signal 628 being carried out at the transmitter place can be received device.
Figure 17 illustrates the exemplary realization of delay cell 630.In one embodiment, these delay cell 630 each self-contained inverters 635, it has: an input, it operationally is coupled to the input of delay cell 630; And an output, it operationally is coupled to the output of this delay cell.Delay cell 630 can further comprise capacitor 636, its have one be coupled to this delay cell 630 output electrode and be coupled to another electrode of a voltage reference (for example, ground connection).As will be understood, inverter 635 is introduced a delay between its input and its reversed-phase output.Because this inverter makes input signal anti-phase,, on each delay path, use even number delay cell so that the noninverting delay of supplied with digital signal 628 is represented to be output to multiplexer 622 will be favourable so can understand.
Figure 18 and 19 explanations are according to another exemplary noise sources 650 of at least one embodiment of the present disclosure.As described, noise source 650 comprises a plurality of noise sources 651 to 654, and it has an output separately so that a power expansion digital noise signal (being respectively power expansion signal 661 to 664) to be provided.Noise source 651 to 654 can comprise any or its combination in the multiple noise source, and is (for example, LFSR), random noise generator (for example, the quadratic residue code sequencer), polynomial sequence generator, like that such as pseudo-random noise generator.Noise source 650 further comprises multiplexer 655, and it has: a plurality of inputs, and its output that operationally is coupled to noise source 651 to 654 is with received power spread signal 661 to 664; And an output, it provides one of these input power spread signals as output signal 660.Noise source 650 also comprises noise source selector 657 to provide control signal 658 to multiplexer 655, and multiplexer 655 is selected one of these inputs based on control signal 658 by this.
In one embodiment, noise source selector 657 provides control signal 658 to generate power output spread signal 660 with in the time division multiplexing power expansion signal 661 to 644 some or all, and it has some or all the sequence of time portion in the power expansion signal 661 to 644.Therefore, noise source selector 657 can comprise that a timer or counter are to select each in the power expansion signal 661 to 664 in a predetermined period.Noise source 651 to 654 has a limited number of state (such as the situation of LFSR) so that power expansion signal 661 to 664 in the example of repetitive sequence therein, noise source selector 657 can select each power expansion signal 661 to 664 in turn so that select by multiplexer 655 next power expansion signal from different noise sources for output before, some or all in these states are expressed in power output spread signal 660.Be the digital signal that the power output spread signal 660 that receiver can be recovered exactly use noise source 650 is transformed, this receiver is preferably realized substantially similar noise source 650.
An advantage of a plurality of power expansion signals of time division multiplexing is that the single noise source that has repetitive sequence with use is compared, and the periodicity of the harmonic wave in the power output spread signal 660 can be increased.For the purpose of illustrating, Figure 19 describes the sequential chart of two independent noise source (being respectively waveform 681 and 682), the sequential chart of the time division multiplexing combination (waveform 683) of these two noise sources that reach as can be realized by the noise source 650 of Figure 18.Suppose that these two noise sources have the state of similar number (for example, eight states), then the sequence of being exported by these noise sources circulates per eight clocks and carries out repetition (circulation 1 and 2).Therefore, each in these two noise sources has the periodicity of eight clocks circulation.Suppose the clock of 100MHz, each will have the end frequency (underlying frequency) in 12.5MHz in these noise sources.
Yet, by a plurality of power expansion signals of time division multiplexing, can increase the periodicity of gained signal, reduce the end frequency of output signal by this.As described, if the signal of these two noise sources will be combined into the whole sequence of output first noise source, then export the whole sequence of second noise source, then export the whole sequence of first noise source again, the rest may be inferred, then the number of times that repeats himself (that is its periodicity) to circulate before in this time-multiplexed output signal (waveform 683) will be doubled to 16 clocks circulations in illustrated example (circulation 1 ').Therefore, the end of this time-multiplexed output signal will only be 6.25MHz frequently.
Figure 20 explanation according at least one embodiment of the present disclosure be used to identify one and be used to transform or the example technique of the noise source of coded digital signal.Discuss in detail as this paper institute, when via transmission line, thereby in the various noise source any one can be realized reducing its EMI characteristic to transform digital signal by transmitter or encoder.As mentioned above, in at least one embodiment, at the coding at transmitter place and the decoding at the receiver place is reflexive, because coded signal is decoded by using with the identical or substantially similar power expansion signal of raw digital signal that is used to encode, just can be from this encoded data signal recovery original data signal.Therefore, the used identical spread signal of receiver or decoder utilization and transmitter or encoder is decoded normally desirable to coded signal.Yet in some instances, receiver may not be determined the feature (for example, type, seed, state number etc.) of transmitter in order to the noise source of coded digital signal.Therefore, Figure 20 describes noise source detection module 700 with the noise source of sign transmitter in order to the encoded digital signal 702 that receives via for example transmission line 704 is encoded.
Noise source detection module 700 comprises an input port 705, a multiplexer 706, a plurality of noise source 707 to 709, a signal transformation module 710 and a comparison module 712.Input port 705 comprises: an input, and it operationally is coupled to transmission line 704 to receive encoded digital signal 704; And an output, its input to signal transformation module 710 provides encoded digital signal 704.Multiplexer 706 comprises: a plurality of inputs, and its output that operationally is coupled to noise source 707 to 709 is with received power spread signal 717 to 719; And an output, its second input to signal transformation module 710 provides selected in the power expansion signal 717 to 719 signal.In one embodiment, noise source 707 to 709 expection is by a duplicate that one or more noise sources that the transmitter of encoded digital signal 702 uses are provided.Comparison module 712 comprises: an input, and it operationally is coupled to the output of signal transformation module 710 (being embodied as XOR gate usually); And an output, it provides control signal 713 to multiplexer 706, and wherein multiplexer 706 is selected one of power expansion signal 717 to 719 based on control signal 713.
In operation, comparison module 712 guides multiplexer 706 to select one of power expansion signal 717 to 719 to export signal transformation module 710 to.Use is from the output of multiplexer 706, signal transformation module 710 transform through encoded digital signal 702 with generate encoded digital signal 702 once transforming expression 714.Comparison module 712 is analyzed this expression 714 through transforming to determine whether it represents the digital signal of having recovered.If the digital signal that its expression has recovered, think that then comparison module 712 has identified the noise source of using in the transmitter place, therefore, comparison module 712 continues operation multiplexer 706, thereby selected power expansion signal is provided to signal transformation module 710 with decoding encoded digital signal 702.
If comparison module 712 determines not represent that through the expression 714 of transforming one has recovered digital signal that then comparison module 712 guides multiplexer 706 to select another power expansion signal.Signal transformation module 710 uses up-to-date selected power expansion signal to transform encoded digital signal 702, and comparison module 712 determine gained once more whether represent that through transforming expression 714 one has recovered digital signal.In this way, but whether in the test noise source 707 to 709 each is used for the identical or substantially similar noise source of noise source that encoded digital signal 702 is encoded with transmitter to determine it.
In one embodiment, comparison module 712 can further comprise second output so that the indication of the analysis result through transforming expression 714 to be provided.This output can be used for for example preventing when being not that expression will be somebody's turn to do through transforming when having recovered digital signal and be represented that 714 are provided to other assembly of receiving system through transforming expression 714.
The techniques described herein are not limited to along the single transmission line transmission of digital signals.In many examples, can on parallel transmission-line, realize the EMI that reduces.Figure 21 to 24 explanation parallel transmission reduces the various example technique of the digital signal of EMI.
Figure 21 illustrated example system 750, each in a plurality of digital signals are transformed by a power expansion signal by this and are sent out on an independent transmission line.System 750 comprises transmitter 751 (that is, encoder), and it operationally is coupled to receiver 752 (that is, decoder) via plurality of transmission lines 761 to 764, and wherein this plurality of transmission lines 761 to 764 can be implemented as a for example bus.Transmitter 751 comprises power expansion module 753, and it has in order to receive a plurality of inputs of a plurality of digital signal DS1 to DS4, reaches a plurality of outputs of the input that operationally is coupled to transmission line interface 754.This transmission line interface 754 and then have a plurality of outputs, each output operationally is coupled in the transmission line 761 to 764.In one embodiment, power expansion module 753 comprises: in order to one or more noise sources 755 to 758 that one or more power expansion signal is provided, and a plurality of signal transformation modules 765 to 768 (being embodied as XOR gate usually), these a plurality of signal transformation modules have one separately and couple to receive the first input end from one power expansion signal in the noise source 755 to 758, reach second corresponding one input among the receiving digital signals DS1 to DS4.Signal transformation module 765 to 768 uses the input power spread signals to transform corresponding digital signal, and provides digital signal through transforming to transmit via the respective transmissions line to transmission line interface 754.
In one embodiment, use a different power expansion signal to transform among the digital signal DS1 to DS4 each.In another embodiment, can use the equal-wattage spread signal to transform one or more among the digital signal DS1 to DS4.Last realization has the benefit of the total EMI that transmission produced that reduces digital signal DS1 to DS4, then a benefit that realizes having the number of the noise source that reduction will realize at the transmitter place.
For transmitter 751, receiver 752 comprises a transmission line interface 774, and it has a plurality of inputs, and each input operationally is coupled in the transmission line 761 to 764 corresponding one; And a plurality of outputs.Receiver 752 further comprises decoder module 773, it has a plurality of signal transformation modules 775 to 778, each signal transformation module has: first input end, and its output that operationally is coupled to transmission line interface 774 is to receive a corresponding encoded digital signal; And second input, it receives the power expansion signal from one of noise source 780 to 783.Signal transformation module 775 to 778 is used the input power spread signal to transform its encoded digital signal that receives separately and is generated the DS1 ' of decoded digital signal of digital signal DS1 to DS4 that is illustrated in before its coding to DS4 '.Because it is reflexive that the signal transformation process between transmitter 751 and the receiver 752 is preferably, preferably to transform module 765 to 768 employed power expansion signals identical or substantially similar with the respective signal of transmitter 751 to the power expansion signal of signal transformation module 775 to 778 so provide.
Although Figure 21 describes the one-to-one relationship between noise source and the transmission line, should be appreciated that, can use the equal-wattage spread signal to transform two or more among the digital signal DS1 to DS4.Perhaps, can use without the form of transforming and come one or more among the transmission of digital signals DS1 to DS4.Be provided with via for example I/O (I/O) pin, basic input/output (bios), the control input of the form of register input like that can be used for determining will transform which digital signal and by which power signal be transformed.
Figure 22 to 24 trace system 800, digital signal can relative to each other be delayed by this to reduce EMI.The system 800 of Figure 22 comprises the transmitter 801 that is coupled to receiver 802 via plurality of transmission lines 803 to 805.This transmitter 801 comprises: power expansion module 807, and it has a plurality of inputs to receive a plurality of digital signal DS1 to DS3; And a plurality of noise sources 808 to 810, it has a plurality of outputs so that power expansion signal 811 to 813 to be provided respectively.Power expansion module 807 further comprises a plurality of signal transformation modules 815 to 817, and it has separately: an input, one of its receiving digital signals DS1 to DS3; And an input, one of its received power spread signal 811 to 813; And an output, it provides the encoded digital signal.Transmitter 801 further comprises an outlet terminal 820 with a plurality of Postponement modules 821 to 823, each Postponement module has: an input, and its corresponding output end that operationally is coupled to one of signal transformation module 815 to 817 is to receive an encoded digital signal; And an output, it operationally is coupled to one of transmission line 803 to 805 to provide the encoded digital signal to transmission line after a delay of determining based on the input that comes self-dalay control module 825.
Similarly, receiver 802 comprises input terminal 830, and this input terminal 830 has: a plurality of inputs, and it is coupled to transmission line 803 to 805 to receive the encoded digital signal; And a plurality of outputs, it provides the encoded digital signal.Receiver 802 further comprises: decoder module 832, and it has a plurality of noise sources 833 to 835, and these a plurality of noise sources 833 to 835 have a plurality of outputs so that power expansion signal 836 to 838 to be provided respectively; And a plurality of signal transformation modules 839 to 841, each signal transformation module has: an input, and it receives a power expansion signal; One input, it receives an encoded digital signal from input terminal 830; And an output, it provides digital signal DS1 ' to DS3 ', and these digital signals represent to use the encoded digital signal of input spread signal transformation.In at least one embodiment, each in the power expansion signal 836 to 838 is identical or substantially similar with its corresponding signal in power expansion signal 811 to 813, so that digital signal DS1 ' is to DS3 ' expression digital signal DS1 to DS3.
As above mentioned, the outlet terminal 820 of transmitter 801 can comprise Postponement module 821 to 823 to postpone providing one or more in these encoded digital signals to transmission line 803 to 805.As hereinafter more detailed argumentation, the delay of introducing in each signal can change between signal.Therefore, postpone not change under the situation about adjusting at this point, digital signal DS1 ' to DS3 ' may not be time alignment.In some instances, this dislocation is for using digital signal DS1 ' may have very little importance or inessential to the assembly of DS3 '.Yet, in other example, such as when power expansion signal 836 to 838 during with its corresponding signal 811 to 813 time alignments, it may be desirable before the encoded digital signal that is received by signal transformation module 839 to 841 house of correction the encoded digital signal that these received being aimed at again.Therefore, in one embodiment, input terminal 830 comprises a plurality of Postponement modules 843 to 845, and it has separately: an input, and it operationally is coupled to one of transmission line 803 to 805; An and output, it operationally is coupled to one of signal transformation module 839 to 841 so that a delay expression of the encoded digital signal that receives via this transmission line to be provided, the wherein retardation input that can be received based on for example self-dalay control module 846, this delay control module 846 can be identical with the delay control module 825 of transmitter 801 or be separated.Perhaps, the output that Postponement module can be coupled to signal transformation module 839 to 841 with transform by signal transformation module 839 to 841 signal DS1 ' to DS3 ' afterwards, with these signals DS1 ' to DS3 ' time alignment.
Figure 23 explanation can be by the exemplary delay module 860 of system's 800 realizations.This Postponement module 860 comprises many delay paths 861 to 864, each bar at least one subclass of these delay paths have one or more delay cell 865 (being similar to the delay cell 630 of Figure 16 and 17) with at a supplied with digital signal when the input of this delay path is transferred to the output of this delay path, postpone to introduce in this supplied with digital signal one.As described, delay path 861 to 864 preferably has the delay cell of different numbers, thereby causes introducing along each path the variation of the amount of the delay in the supplied with digital signal.
In operation, postpone control 825 and can set one or more in the Postponement module 821 to 823, so that its by the encoded digital signal of the one or more outputs in the signal transformation module 815 to 817 on the transmission line 803 to 805 by parallel transmission before, certain retardation is introduced in these encoded digital signals.When comparing with the undelayed identical coded signal transmission of parallel transmission, this delay causes the EMI characteristic through reducing usually.This is especially correct during by parallel transmission by two or above transmission line when identical coded signal.By adjusting the aligning of these signals, total EMI characteristic can reduce by the possibility that reduces parallel signal transition simultaneously.
Figure 24 illustrates the oscillogram of the exemplary operation of a trace system 800.In order to be easy to discuss, suppose that digital signal DS1 to DS3 is a same signal, and transform by the equal-wattage spread signal, but on transmission line 803 to 805 independence and parallel transmission.Can understand, under the situation that does not have among one or more in the digital signal DS1 to DS3 of this example to postpone, because digital signal DS1 to DS3 simultaneously and transition in the same manner, so will be three times approximately by any EMI who launches separately in the transmission line 803 to 805 by total EMI of transmission line 803 to 805 emissions.Yet, if postponing 874 for example is introduced among the digital signal DS2 via transmission line 804 transmission, then may be reduced in the number of simultaneous same type transition among digital signal DS1 and the digital signal DS2, reduce EMI thus by the combined transmit of digital signal DS1 and DS2.When digital signal DS2 is delayed with respect to digital signal DS3, can between digital signal DS1 and DS3, realize an EMI characteristic that similarly reduces.
In addition, look some characteristic, on the transmission line that replaces, can realize same delay such as the degree closer to each other of transmission line 803 to 805.For example, suppose that transmission line 804 is deployed between transmission line 803 and 805, the signal DS1 and the DS3 that are transmitted respectively by transmission line 803 and 805 can realize same delay, and can realize different the delay so that make digital signal DS2 from digital signal DS1 and DS3 skew by the digital signal DS2 of transmission line 804 transmission, and the skew between digital signal DS1 and the DS3 may need not misgivings like this because of its relative distance between transmission line 803 and 805.
In another embodiment, delay control 825 may command one provide the noise source (not shown) to transmitter and receiver.In this example, the output of these delay control 825 these noise sources of may command is so that introduce a time shift in this noise source.Therefore, the control of the delay in this example 825 can be embodied as one and have the shift register that output is fed to the tap of transmitter and receiver.
As above describe in detail, the digital signal of transmitting between transmitter and receiver can be represented dagital clock signal, and PLL or other clock synchronization apparatus are synchronized to this dagital clock signal.In numerous examples, institute's transmission of digital signals can from expression without dagital clock signal (this paper is called " the normal mode ") transition of transforming to expression through transforming or the dagital clock signal (this paper is called " XEMI pattern ") of coding, or vice versa.Figure 25 to 28 explanation is used to identify these transition so that the example technique of correspondingly suitably synchronous PLL or other clock synchronization apparatus.As described in detail below, in one embodiment, after realizing phase locking, take place one overtimely with non-expansion clock, it is controlled to the transition of XEMI pattern.Make the pattern of entering so that the highest significant position of the encoder of transmitter is disabled, thereby create out a pattern that is not present in normal " state " of noise source.This pattern is convenient to enter the XEMI pattern in predictable mode, thereby if the impulsive noise incident on some noises of on the transmission line or receiver inside causes the clock mistake sampling to the receiver input, then the vacation of having got rid of in advance to the XEMI pattern enters., the mistake sampling do not have this feature if taking place, meaning promptly causes the noise event of clock edge time shift (meaning is promptly located X amount of jitter forward or backwards about the normal edge of clock), then receiver clock internal sample circuit can be perceived as this " entering " XEMI pattern, and starts its noise source.At this moment, receiver clock no longer is locked to input signal usually, so system's possible errors ground operation.By using an AD HOC (making clock keep one state or several clock cycle of " 0 " state), receiver can determine that transmitter enters the XEMI pattern.Therefore, first clock (its owing to receiver noise source do not open as yet be out-phase) is suppressed to prevent that this PLL from losing locking about the input of the phase-frequency detector to PLL.Because this only takes place once when entering and withdrawing from the XEMI pattern, thus usually there is the minimum jitter influence in a clock, and, therefore do not expect that there is any unexpected operation in this system because system does not withdraw from the electrification reset state as yet.Use a reason of uniqueness state to be, usually do not exist whether there being a plurality of error events to betide control in the transmission of clock, and therefore may (although possibility is little) cause receiver to be thought mistakenly the situation that withdraws from having taken place repeatedly to enter in this system.
Figure 25 illustrates transmitter 900, and it has: clock source 901, this clock source 901 have an output so that dagital clock signal 902 to be provided; Noise source 903, it provides power expansion signal 904; And signal transformation module 905, it has: one receives the input of dagital clock signal 902 and the input of a received power spread signal 904, and one provides an expression to use the output of the encoded clock signal 906 of the dagital clock signal 902 that power expansion signal 904 transforms.Transmitter 900 further comprises initialization module 908, and it has one and operationally is coupled to the output of noise source 903 with the operation of controlling this noise source 903.
With apprehensible, synchronously to a clock and before stablizing, need several clocks circulations usually as those skilled in the art at PLL.Therefore, for example maybe may cause this PLL to carry out the instability locking by what transmitter 900 carried out from may cause the PLL at receiver place can not suitably be locked to this clock signal without transformation clock signal to direct transition after the power supply through transforming clock signal.Therefore, at least one embodiment, initialization module 908 provides a control signal to maintain init state to make noise source 903 during initial phase 910 to noise source 903.During this initial phase 910, the output of noise source 904 preferably is maintained at constant logical value (for example, logical value " zero ") so that clock signal 902 is outputted as clock signal 906 with the form without transformation.Therefore, the receiver of a receive clock signal 906 can be with its PLL synchronously to clock signal 906, and this clock signal 906 is represented during initialization period 910 without the clock signal of transforming 902.
After initialization period 910, the PLL of expection receiver is synchronized to this without the clock signal of transforming 902 and stable.Number or time in the past that initialization module 908 can use timer or counter 909 to measure the clock circulation are carried out timing to this initialization period.When initialization period finished, initialization module 908 guided noise source 903 transition to effective status 911 (transition 912), and noise source 903 is exported non-constant power expansion signal by this, and is such as pseudo-random signal, random signal, polynomial sequence, like that.Therefore, transform clock signal 905 to produce encoded clock signal 906 by noise source 904 present non-constant outputs.See below that Figure 26 and 27 discusses, in one embodiment, receiver detects clock signal 906 from without transforming clock signal to the transition 912 of encoded clock signal, and initialization also starts its noise source, and this encoded clock signal of correspondingly decoding.
Figure 26 and 27 explanations transition 912 (Figure 25) and the correspondingly various exemplary realization of the receiver of PLL synchronously in order to detect clock signal 906.The receiver 920 of Figure 26 comprises: mode detection module 922, and it has the output that an input and via transmission line receive clock signal 906 provides control and configuration information; One noise source 924, it has the output that an input and that receives this control and configuration information provides power expansion signal 925; And a signal transformation module 926, it has the input of a receive clock signal 906, the input and of a received power spread signal 925 provides the output of decoding clock signal 927.Receiver 920 further comprises PLL928, and it has one and receives the input and of decoding clock signal 927 and provide one synchronously to the output of the clock signal 929 of clock signal 927.
In at least one embodiment, mode detection module 922 can be operated to detect clock signal 906 certainly without transforming clock signal to the transition 912 of encoded clock signal.Before this transition, mode detection module 922 can make noise source 924 be maintained at init state, thus use make power expansion signal 925 for constant logical value clock signal 906 by signal transformation module 926 with without forms of modification output as clock signal 927.PLL928 is by this synchronously to clock signal 927, and thus effectively synchronously to clock signal 906, this clock signal 906 is represented clock signal 902 (Figure 25) during init state.Follow closely after the transition 912, but mode detection module 922 initialization noise sources 924 and guide noise source 924 to enter effective status use exporting non-constant power expansion signal 925 to signal transformation module 926.Therefore, use 925 pairs of non-constant power expansion signals encoded clock signal 906 decode generating clock signal 927, it is illustrated in the clock signal 902 before the coding during the effective status.
Figure 27 explanation has the similar receiver 930 of mode detection module 922, noise source 924, signal transformation module 926 and PLL928.Yet, be not direct control noise source 924, in one embodiment, mode detection module 922 provides control signal to multiplexer 932, this multiplexer 932 is input with clock signal 906 and clock signal 927, and has an output that is coupled to the input of PLL928.Detecting clock signal 906 based on mode detection module 922, to be in normal mode still be the XEMI pattern, and this mode detector module 922 guides multiplexers 932 to select one of clocks 906 or 927 to export PLL to.When being in normal mode, clock signal 906 expressions are the clock signal 902 without forms of modification, and because noise source 924 is not directly by 922 controls of mode detector module in this example, so the clock signal 927 by 926 outputs of signal transformation module may not represented clock signal 902, therefore operates multiplexer 932 with clock signal 906.On the contrary, when being in the XEMI pattern, the version of code of clock signal 906 expression clock signals 902, and therefore the decoded version of clock signal 927 expression clock signals 902 operates multiplexer to provide clock signal 927 to export PLL928 to.Mode detection module 922 this transition of any detection in can be in every way.For example, mode detection module 922 can be realized a state machine, uses the concrete pattern that detects this transition of expression and indicates this transition to take place thus.
Referring to Figure 28, its explanation one is used at institute's transmit clock signal from normal mode to the transition of XEMI pattern or keep the technology of PLL locking during to normal mode transition from the XEMI pattern.As mentioned above, receiver receives an input clock signal usually, and determines that this input clock signal is still encoded clock signal not of encoded clock signal (XCLK).As discussed below, receiver can have detection transition to encoded clock signal and start it and treat ability with the synchronous noise source of the noise source of transmitter from the normal clock signal.On the contrary, receiver also can have and detects input clock signal and control oneself encoded clock signal to the transition of encoded clock signal not and therefore cut out or stop to utilize the ability of its noise source decoding input clock signal.
As shown in Figure 28, PLL synchronization module 960 can be reached in order to the markers variation by decoder and correspondingly adjust the PLL Synchronization routines.PLL synchronization module 960 comprises: aim at Postponement module 962, it has one and receives reference clock signal 963 () input for example, the clock signal 927 among Figure 26, and an output that delay clock signals 964 is provided; Trailing edge counter 965, it has two inputs that this delay clock signals 964 of reception reaches from the feedback signal 966 of PLL961, and an output; Pulse suppressor 968, it has an input that operationally is coupled to the output of trailing edge counter 965, and an output; And PLL961, it has phase detectors 969, and these phase detectors 969 have an input that operationally is coupled to the output of pulse suppressor 968, and an input that receives by the feedback signal 966 of PLL core 970 outputs.
In at least one embodiment, the rising edge in phase detectors use benchmark and the feedback clock signal is followed the tracks of the phase place of clock signal.Therefore, transmitter has been eliminated some the redundant trailing edges in the clock of source and has been used trailing edge in the encoded clock signal and phase place that rising edge is passed on this clock signal.Therefore receiver inserts the trailing edge of received signal again, so that phase detectors use correct transition to follow the tracks of the phase place in long-range clock source.
Aim at Postponement module 962 and be used for positioning reference clock signal 966, so that it can carry out reliable samples by trailing edge detector 965.This trailing edge detector 965 sampling reference clock signals 966 are with the trailing edge of losing of the beginning that identifies the transition of indication between normal mode and XEMI pattern.Trailing edge detector 965 can comprise a D-latch, the state of the reference clock signal 963 on the rising edge of its seizure feedback clock signal 966.This trailing edge of losing will cause the edge mismatch (meaning promptly, when expectation one rising edge, trailing edge comes across on the benchmark pin) to the input of phase detectors 969 usually.Because trailing edge is not used by phase detectors 969,, thereby cause PLL961 to leave locking potentially so the corresponding rising edge on the feedback clock signal 966 will cause phase detectors 969 to proofread and correct the rising edge of counter-rotating.Therefore, when the disappearance of trailing edge is lowered by when detector 965 detects, pulse suppressor 968 suppresses the rising edge to two inputs of phase detectors 969.In one embodiment, by suppressing rising edge the high period that only allows rising edge to come across sampling clock.In one embodiment, edge counter 967 is used for checking by trailing edge detector 965 detected pattern transition signatures.It is not to be caused by the error of sampling during normal clock that edge counter 967 is guaranteed by trailing edge detector 965 detected sequences.Be generally the result who does not have the reference signal of transition at the nominal falling edge by trailing edge detector 965 detected true transition sequences.
In embodiment at least, when powering up or during initialization, PLL961 responds the input clock with normal mode in a usual manner.This PLL961 follows the tracks of this and imports clock into and final one " locking " signal that generates has been realized phase place and frequency lock to indicate it.This locking signal and then cause the charge pump (not shown) of PLL961 to limit it can converging or the maximum current electric charge in source, thus any incoming frequency perturbation is minimized to PLL output clock frequency.Therefore, during " chokes pattern ", PLL961 and to input clock in phase change general wide scope and react.
On the contrary, when the output clock is detected as the XEMI pattern and when the transition of XEMI pattern is finished, discharges this locking signal, remove restriction by this, and allow the charge pump of PLL to operate in a usual manner by this employed maximum current electric charge of charge pump.When transition between normal clock and XEMI reduction transmit clock pattern, this technology helps to minimize any pulse jitter.
Now, the exemplary circuit device 980 of realizing transmitter and receiver has been described according at least one embodiment of the present disclosure referring to Figure 29.This circuit arrangement 980 comprises integrated circuit or monolithic system, it has: an input that operationally is coupled to circuit arrangement 980 (for example, one or more single-ended or differential pair inputs) receiver 982, an and transmitter 984 that operationally is coupled to an output (for example, one or more single-ended or differential pair outputs) of circuit arrangement 980.Circuit arrangement 980 can further comprise output and PLL986 between the transmitter 984 and the scaler 988 that is coupled to receiver 982.In one embodiment, receiver 982 comprises noise source 990 and signal transformation module 992, and it has an input that operationally is coupled to the output of noise source 990.In one embodiment, transmitter 984 comprises noise source 994 and signal transformation module 996, and this signal transformation module 996 has an input that operationally is coupled to the output of this noise source 994.Notice that noise source 990 and 994 can comprise same noise source or different noise source.
In one embodiment, power expansion signal 997 is provided to circuit arrangement 980.The power expansion signal that use is provided by noise source 990, signal transformation module 992 are transformed power expansion signals 997 to recover a spread signal or claim normal signal 998 not, and it can represent for example data-signal or dagital clock signal.This normal signal 998 is input to PLL986, and can use scaler 988 to zoom to higher the output of this PLL988 or lower frequency.The output of scaler 988 is input to signal transformation module 996, and the power expansion signal that uses noise source 994 to be provided is thus transformed to generate power expansion signal 999 it, and it is by circuit arrangement 980 outputs.Therefore, can understand, circuit arrangement 980 can be signed so that further reduce EMI or realize some EMI characteristic or target in order to the fundamental frequency of zoom power spread signal or in order to the EMI that changes the power expansion signal.
Can use various functions and assembly in realizing to use such as the processor of a data processor or a plurality of processing unit.This data processor can be microprocessor, microcontroller, microcomputer, digital signal processor, state machine, logical circuit and/or based on operational order or handle any device of digital information in a predefined manner.Generally speaking, various functions and the system by block representation is easy to use one or more listed realization technology of this paper to realize by those skilled in the art.
When using the data processor of issuing command, this instruction can be stored in the memory.This memory can be single memory device or a plurality of storage arrangement.This storage arrangement can be any device of ROM device, random access memory device, magnetic tape storage, diskette file, harddisk memory, external tape and/or storage of digital information.Note, when data processor is realized its one or more function via state machine or logical circuit, the memory that stores command adapted thereto can be built in the circuit that comprises state machine and/or logical circuit, or because use combinational logic to carry out this function, so that it can be is unnecessary.This processor can be system, or the part of system, and is such as the device that computer, PDA(Personal Digital Assistant), hand-held computing device, cable set top box, internet are enabled, such as cell phone, like that.
Claims (131)
1. method comprises:
Use the first power expansion digital noise signal transformation, first digital signal;
Use the described first power expansion digital noise signal transformation, second digital signal;
Provide first digital signal to export first transmission line in the very first time through transforming; And
Provide second digital signal to export second transmission line in second time that is different from the described very first time through transforming.
2. the method for claim 1 is characterized in that, described first power expansion digital noise signal and the described second power expansion digital noise signal are same signal.
3. the method for claim 1 is characterized in that, the described first power expansion digital noise signal is different signals with the described second power expansion digital noise signal.
4. method as claimed in claim 1 is characterized in that, further comprises:
Use the 3rd power expansion digital noise signal transformation three digital signal; And
Provide three digital signal to export the 3rd transmission line in the 3rd time through transforming.
5. method as claimed in claim 4 is characterized in that, described second transmission line is deployed between described first transmission line and described the 3rd transmission line.
6. method as claimed in claim 5 is characterized in that, the described very first time and described the 3rd time are basically simultaneously.
7. method as claimed in claim 1 is characterized in that, further comprises:
Receiving described first digital signal of indication and described second digital signal will be in the control excitation that divides other time to be provided.
8. method as claimed in claim 7 is characterized in that, described control excitation comprises at least one via basic input/output setting, the register value of one or more pins receptions of circuit arrangement or in the middle of importing.
9. method comprises:
Use individual or a plurality of digital signals of a plurality of power expansion digital noise signal transformations;
Provide described a plurality of each in transforming digital signal to export a corresponding transmission lines in the plurality of transmission lines to;
Providing of at least one subclass of wherein said a plurality of digital signals each with respect to the providing of one or more other digital signals in described a plurality of digital signals is delayed.
10. method as claimed in claim 9, it is characterized in that, first subclass of the one or more formations in described a plurality of digital signal uses one first power expansion digital noise signal to transform, and second subclass of the one or more formations in described a plurality of digital signal uses second a power expansion digital noise signal that is different from the described first power expansion digital noise signal to transform.
11. method as claimed in claim 10 is characterized in that, the transmission line of transmission line and the digital signal that is used to transmit described first subclass that is used to transmit the digital signal of described second subclass interweaves.
12. method as claimed in claim 9 is characterized in that, each in described a plurality of digital signals uses predetermined power expanding digital noise signal to transform.
13. a system comprises:
The power expansion module, it comprises a plurality of inputs, in described a plurality of input each receives a corresponding digital signal in a plurality of digital signals, and further comprise a plurality of outputs, each output provides a numeral of a corresponding digital signal in described a plurality of digital signal, and wherein said numeral is the described corresponding digital signal of having represented by a power expansion digital noise signal transformation; And
Outlet terminal, it comprises a plurality of inputs, each input operationally is coupled to the corresponding output of described power expansion module, and further comprise a plurality of outputs, each output provides a numeral via described input reception corresponding to a corresponding input with a corresponding transmission lines in plurality of transmission lines;
Wherein said outlet terminal can be operated with will providing with respect to the providing of numeral of one or more other transmission line and postpone the numeral of one or more in the described transmission line.
14. system as claimed in claim 13 is characterized in that, described power expansion digital noise signal comprises pseudo-random noise signal.
15. system as claimed in claim 13 is characterized in that, described power expansion digital noise signal comprises the Gaussian noise signal.
16. system as claimed in claim 13, it is characterized in that described outlet terminal can be operated to be modified in based on control excitation by described outlet terminal first numeral is provided and with the delay of second numeral between second transmission line provides to first transmission line.
17. system as claimed in claim 16, wherein said control excitation comprises at least one via basic input/output setting, the register value of one or more pins receptions of circuit arrangement or in importing.
18. a method comprises:
The operand word noise generator is in init state between the very first time and second time;
The described digital noise generator of operation is in effective status between described second time and the 3rd time;
Dagital clock signal is transformed in output based on described digital noise generator; And
Dagital clock signal through transforming was provided between the described very first time and described the 3rd time.
19. method as claimed in claim 18 is characterized in that, the usage counter in period between the described very first time and described second time is measured.
20. method as claimed in claim 18 is characterized in that, operate described digital noise generator be in init state comprise the configuration described digital noise generator so that constant output to be provided.
21. method as claimed in claim 18 is characterized in that, operate described digital noise generator be in described effective status comprise the operation described digital noise generator so that the pseudorandom number signal to be provided.
22. method as claimed in claim 18 is characterized in that, operate described digital noise generator be in described effective status comprise the operation described digital noise generator so that the nonlinear extensions signal to be provided.
23. method as claimed in claim 18 is characterized in that, operate described digital noise generator be in described effective status comprise the operation described digital noise generator so that a quadratic residue code sequence to be provided.
24. method as claimed in claim 18 is characterized in that, operate described digital noise generator be in described effective status comprise the operation described digital noise generator so that polynomial value progression to be provided.
25. method as claimed in claim 18 is characterized in that, the beginning of the described very first time is based on the electrification reset excitation.
26. method as claimed in claim 18 is characterized in that, further comprises:
The described digital noise generator of operation is in init state between described the 3rd time and the 4th time;
Dagital clock signal is transformed in output based on described digital noise generator; And
Dagital clock signal through transforming was provided between described the 3rd time and described the 4th time.
27. a method comprises:
Receiving digital signals, described digital signal at first o'clock interim expression first dagital clock signal and the interim expression in second o'clock after following described first period closely through transforming dagital clock signal, wherein said dagital clock signal through transforming is the expression by described first dagital clock signal of the first power expansion digital noise signal transformation;
Detect described digital signal from representing that described first dagital clock signal is described through transforming the transition of dagital clock signal to representing; And
Use described first dagital clock signal or a described next synchronous local clock in transforming dagital clock signal based on detecting described transition.
28. method as claimed in claim 27 is characterized in that, synchronous described local clock comprises:
Before detecting described transition that described local clock is synchronous to described digital signal;
Use the described dagital clock signal of the second power expansion digital noise signal transformation to produce second dagital clock signal of described first dagital clock signal of expression; And
In response to detecting described transition that described local clock is synchronous to described second dagital clock signal.
29. method as claimed in claim 28 is characterized in that, the described second power expansion digital noise signal is substantially equal to the described first power expansion digital noise signal.
30. method as claimed in claim 27, it is characterized in that, the described transition of described digital signal represented by the predetermined variation in the bit mode of described digital signal, and detects described transition and comprise described predetermined variation in the described bit mode that detects in the described digital signal.
31. method as claimed in claim 29 is characterized in that, the described predetermined variation in the described bit mode detects by detecting the edge of losing in the described digital signal.
32. method as claimed in claim 30 is characterized in that, the described predetermined variation in the described bit mode uses sliding window to detect.
33. a system comprises:
Noise source, it comprises the output that power expansion digital noise signal is provided;
Multiplier, it comprises: operationally be coupled to the first input end of the described output of described noise source, second input of reception dagital clock signal, and operationally be coupled to the output of transmission line; And
Timer, it comprises first input end that receives the control excitation and the output that operationally is coupled to described noise source, and wherein said timer can be operated to be activated at first o'clock described noise source of interim operation based on described control and be in init state.
34. system as claimed in claim 33 is characterized in that, when being in described init state, and described noise source output steady state value.
35. system as claimed in claim 33 is characterized in that, described timer further can be operated with second o'clock described noise source of interim operation after following described first period closely and be in effective status.
36. system as claimed in claim 35 is characterized in that, when being in described effective status, described noise source is exported described power expansion digital noise signal.
37. system as claimed in claim 33 is characterized in that, described power expansion digital noise signal comprises the pseudorandom number noise signal.
38. system as claimed in claim 33 is characterized in that, described power expansion digital noise signal comprises the nonlinear extensions signal.
39. system as claimed in claim 33 is characterized in that, described power expansion digital noise signal comprises the quadratic residue code sequence.
40. system as claimed in claim 33 is characterized in that, described power expansion digital noise signal comprises polynomial sequence.
41. system as claimed in claim 33 is characterized in that, described control excitation comprises reset signal.
42. a system comprises:
Noise source, it comprises the output that the first power expansion digital noise signal is provided;
Multiplier, it comprises the first input end of the described output that operationally is coupled to described noise source and operationally is coupled to transmission line with second input that receives first digital signal and the output that operationally is coupled to phase-locked loop (PLL); And
Clock detector, it comprises and operationally is coupled to described transmission line with the input that receives described first digital signal and operationally be coupled to the output of described noise source, wherein said clock detector can be operated to keep described noise source and be in init state, until described clock detector detect in described first digital signal transition is arranged till;
The first of wherein said first digital signal before described transition represents a dagital clock signal, and the second portion of described first digital signal is represented the described dagital clock signal by the second power expansion digital noise signal transformation.
43. system as claimed in claim 42 is characterized in that, when being in described init state, and described noise source output steady state value.
44. system as claimed in claim 42 is characterized in that, described clock detector further can be operated to discharge described noise source in response to detecting described transition from described init state.
45. system as claimed in claim 42, it is characterized in that, the described transition of described digital signal is represented by the predetermined variation in the bit mode in the described digital signal, and described clock detector detects described transition based on the described predetermined variation in the described bit mode that detects in the described digital signal.
46. system as claimed in claim 45 is characterized in that, the described predetermined variation in the described bit mode detects by the edge of losing that detects in the described digital signal.
47. system as claimed in claim 42 is characterized in that, described power expansion digital noise signal comprises the pseudorandom number noise signal.
48. system as claimed in claim 42 is characterized in that, described power expansion digital noise signal comprises the nonlinear extensions signal.
49. system as claimed in claim 42 is characterized in that, described power expansion digital noise signal comprises the quadratic residue code sequence.
50. system as claimed in claim 42 is characterized in that, described power expansion digital noise signal comprises polynomial sequence.
51. a circuit arrangement comprises:
Circuit substrate;
Be deployed in the transmission line at described circuit substrate place;
Be deployed in the transmitter at described circuit substrate place, and it comprises:
First noise source, it comprises the output that the first power expansion digital noise signal is provided; And
Encoder, it comprises: operationally be coupled to the first input end of the described output of described first noise source, second input of reception first digital signal, and operationally being coupled to described transmission line so that the output of second digital signal to be provided, wherein said encoder can be operated to use described first digital signal of the described first power expansion digital noise signal transformation to generate described second digital signal; And
Be deployed in the receiver at described circuit substrate place, and it comprises:
With second noise source that described first noise source is separated, described second noise source comprises the output that the second power expansion digital noise signal is provided; And
Decoder, it comprises: operationally be coupled to the first input end of the described output of the described second described noise source, operationally be coupled to described transmission line to receive second input of described second digital signal, and provide the output of a three digital signal, wherein said decoder can be operated to use the described second power expansion digital noise signal to transform described second digital signal to generate described three digital signal, and wherein said three digital signal is represented described first digital signal.
52. circuit arrangement as claimed in claim 51 is characterized in that, described circuit substrate comprises printed circuit board (PCB).
53. circuit arrangement as claimed in claim 52 is characterized in that, described transmitter is integrated in first integrated circuit (IC) apparatus, and described receiver is integrated in second integrated circuit (IC) apparatus of separating with described first integrated circuit (IC) apparatus.
54. circuit arrangement as claimed in claim 51 is characterized in that, described circuit substrate comprises ic substrate.
55. a device comprises:
Many delay paths, each delay path prolong and comprise the input that receives first digital signal and about the delay cell of the different numbers of other delay path in described many delay paths;
Pseudorandom number generator, it comprises output; And
Multiplexer, it comprises control input end, a plurality of signal input part and an output, wherein each signal input part operationally is coupled to a corresponding delay path in described many delay paths, and described multiplexer can be operated to select signal via a reception in described a plurality of signal input parts to provide to described output based on described control input.
56. device as claimed in claim 55 is characterized in that, described digital signal comprises dagital clock signal.
57. device as claimed in claim 55 is characterized in that, described delay cell comprises that one operationally is coupled to the inverter of capacitor.
58. device as claimed in claim 57 is characterized in that, further comprises the noise generator that operationally is coupled to described delay cell, wherein said noise generator can be operated to enable described delay cell.
59. a method comprises:
More than first digital noise power expansion of time division multiplexing signal is to produce the first digital multiplexing noise signal;
Transform first digital signal based on the described first digital multiplexing noise signal; And
Provide described first first digital signal to export transmission line to through transforming.
60. method as claimed in claim 59 is characterized in that, the described a plurality of digital noise power expansion signals of time division multiplexing comprise:
Select the first digital noise power expansion signal in described a plurality of digital noise power expansion signal;
The very first time part of the very first time part of the described first digital noise power expansion signal as described digital multiplexing noise signal is provided;
Select the second digital noise power expansion signal of described a plurality of digital noise power expansion signals; And
Second time portion of the very first time part of the described second digital noise power expansion signal as described digital multiplexing noise signal is provided.
61. method as claimed in claim 60, it is characterized in that, the described first digital noise power expansion signal comprises N state, and the described very first time of the described first digital noise power expansion signal partly comprises a sequence of each formation in the described N state.
62. method as claimed in claim 61, it is characterized in that, the described second digital noise power expansion signal comprises M state, and the described very first time of the wherein said second digital noise power expansion signal partly comprises a sequence of each formation in M the state such as described.
63. method as claimed in claim 59 is characterized in that, at least one in described a plurality of digital noise power expansion signals comprises pseudo-random noise generator.
64. method as claimed in claim 59 is characterized in that, at least one in described a plurality of digital noise power expansion signals comprises the nonlinear extensions signal generator.
65. method as claimed in claim 59 is characterized in that, at least one in described a plurality of digital noise power expansion signals comprises the quadratic residue code sequencer.
66. method as claimed in claim 59 is characterized in that, at least one in described a plurality of digital noise power expansion signals comprises multinomial generator.
67. method as claimed in claim 59 is characterized in that, further comprises:
Receive described first first digital signal via described transmission line through transformation;
More than second digital noise power expansion of time division multiplexing signal is to produce the second digital multiplexing noise signal;
Transform described first first digital signal to generate second digital signal of described first digital signal of expression based on the described second digital multiplexing noise signal through transforming.
68. as the described method of claim 67, it is characterized in that, further comprise:
Phase-locked loop is synchronous to described second digital signal.
69., it is characterized in that the described second digital multiplexing noise signal is substantially equal to the described first digital multiplexing noise signal as described method as described in the claim 67.
70. a method comprises:
The digital signal of reception through transforming describedly represented first digital signal by one first digital noise power expansion signal transformation through transforming digital signal;
The a plurality of digital noise power expansion of time division multiplexing signal is substantially equal to the second digital noise power expansion signal of the described first digital noise power expansion signal with generation;
Transform described through transforming digital signal to generate second digital signal of described first digital signal of expression based on the described second digital multiplexing noise signal.
71. as the described method of claim 70, it is characterized in that, further comprise:
Phase-locked loop is synchronous to described second digital signal.
72. as the described method of claim 71, it is characterized in that, the described first digital noise power expansion signal comprises N state, and the described very first time of the described first digital noise power expansion signal partly comprises a sequence of each formation in N the state such as described.
73. as the described method of claim 72, it is characterized in that, the described second digital noise power expansion signal comprises M state, and the described very first time of the described second digital noise power expansion signal partly comprises each the sequence in the described M state.
74., it is characterized in that at least one in described a plurality of digital noise power expansion signals comprises pseudo-random noise generator as the described method of claim 70.
75., it is characterized in that at least one in described a plurality of digital noise power expansion signals comprises the nonlinear extensions signal generator as the described method of claim 70.
76., it is characterized in that at least one in described a plurality of digital noise power expansion signals comprises the quadratic residue code sequencer as the described method of claim 70.
77., it is characterized in that at least one in described a plurality of digital noise power expansion signals comprises multinomial generator as the described method of claim 70.
78. a system comprises:
More than first noise source, each noise source has the output that digital noise power expansion signal is provided;
First multiplexer, it has output, control input end and a plurality of signal input part, each signal input part operationally is coupled to the output of a corresponding noise source in more than first noise source such as described grade, and wherein said first multiplexer can be operated to be provided at the signal that one of described a plurality of signal input parts place receives based on the control signal that receives via described control input end to described output;
First control module, it has provides described control signal to described first multiplexer and so that operate described first multiplexer described digital noise power expansion signal that is provided by more than first noise source such as described grade is carried out time-multiplexed output; And
First multiplier, it has the first input end that receives one first digital signal, operationally is coupled to second input of the described output of described first multiplexer and output.
79., it is characterized in that at least one in described a plurality of noise sources comprises pseudo-random noise generator as the described system of claim 78.
80., it is characterized in that at least one in described a plurality of noise sources comprises the nonlinear extensions signal generator as the described system of claim 78.
81., it is characterized in that at least one in described a plurality of noise sources comprises the quadratic residue code sequencer as the described system of claim 78.
82. 78 system is characterized in that as claimed in claim, at least one in described a plurality of noise sources comprises multinomial generator.
83. 78 system is characterized in that as claimed in claim, further comprises:
Transmission line, it operationally is coupled to the described output of described first multiplexer;
More than second noise source, each noise source has the output that digital noise power expansion signal is provided;
Second multiplexer, it has output, control input end and a plurality of signal input part, each signal input part operationally is coupled to the output of a corresponding noise source in described more than second noise source, and wherein said second multiplexer can be operated to be provided at the signal that one of described a plurality of signal input parts are located to receive based on a control signal that receives via described control input end to described output;
Second control module, it has provides described control signal to described second multiplexer and so that operate described second multiplexer described digital noise power expansion signal that is provided by more than second noise source such as described grade is carried out time-multiplexed output; And
Second multiplier, it has and operationally is coupled to described transmission line receiving second input that by the first input end of second digital signal of described first multiplier output, operationally is coupled to the described output of described second multiplexer, and output;
Wherein the signal of being exported by described second multiplexer is substantially equal to the signal by described first multiplexer output.
84. a method comprises:
Use the first power expansion digital noise signal transformation, first digital signal;
Use is different from the second power expansion digital noise signal transformation, second digital signal of the described first power expansion digital noise signal;
Provide first digital signal to export first transmission line to through transforming; And
Provide second digital signal to export second transmission line to through transforming.
85. as the described method of claim 84, it is characterized in that, further comprise:
Receive described first digital signal via described first transmission line through transforming;
Receive described second digital signal via described second transmission line through transforming;
Use described first digital signal of the 3rd power expansion digital noise signal transformation to generate the three digital signal of described first digital signal of expression through transforming; And
Use described second digital signal of the 4th power expansion digital noise signal transformation to generate the 4th digital signal of described first digital signal of expression through transforming.
86. as the described method of claim 85, it is characterized in that, described the 3rd power expansion digital noise signal is substantially equal to the described first power expansion digital noise signal, and described the 4th power expansion digital noise signal is substantially equal to the described second power expansion digital noise signal.
87., it is characterized in that described first digital signal is a dagital clock signal as the described method of claim 85, and described method comprises further with phase-locked loop synchronously to described three digital signal.
88., it is characterized in that at least one in described first power expansion digital noise signal or the described second power expansion digital noise signal comprises pseudo-random noise signal as the described method of claim 84.
89., it is characterized in that at least one in described first power expansion digital noise signal or the described second power expansion digital noise signal comprises the nonlinear extensions signal as the described method of claim 84.
90., it is characterized in that at least one in described first power expansion digital noise signal or the described second power expansion digital noise signal comprises the quadratic residue code sequence as the described method of claim 84.
91., it is characterized in that at least one in described first power expansion digital noise signal or the described second power expansion digital noise signal comprises polynomial sequence as the described method of claim 84.
92. a system comprises:
First noise source, it has the output that the first power expansion digital noise signal is provided;
Second noise source, it has the output that the second power expansion digital noise signal is provided;
The first power expansion module, it has the input that receives one first digital signal, and operationally be coupled to the input of described output of described first noise source, and provide output by first numeral of described first digital signal of the described first power expansion digital noise signal transformation; And
The second power expansion module, the input that it has the input that receives one second digital signal and operationally is coupled to the described output of described second noise source, and output by second numeral of described second digital signal of the described second power expansion digital noise signal transformation is provided.
93. as the described system of claim 92, it is characterized in that, further comprise:
First transmission line, it operationally is coupled to the described output of the described first power expansion module;
Second transmission line, it operationally is coupled to the described output of the described second power expansion module;
The 3rd noise source, it has the output that the 3rd power expansion digital noise signal that is substantially equal to the described first power expansion digital signal is provided;
The 4th noise source, it has the output that the 4th power expansion digital noise signal that is substantially equal to the described second power expansion digital signal is provided;
The 3rd power expansion module, it has and operationally is coupled to described first transmission line to receive the input of described first numeral, reach the input of the described output that operationally is coupled to described the 3rd noise source, and output by the 3rd numeral of described first numeral of described the 3rd power expansion digital noise signal transformation is provided, wherein said the 3rd numeral is the expression of described first digital signal; And
The 4th power expansion module, it has and operationally is coupled to described second transmission line to receive the input of described second numeral, reach the input of the described output that operationally is coupled to described the 4th noise source, and output by the 4th numeral of described second numeral of described the 4th power expansion digital noise signal transformation is provided, wherein said the 4th numeral is the expression of described second digital signal.
94. the described system of claim 93, it is characterized in that, described first digital signal is a clock signal, and described system further comprises phase-locked loop, the output that it has the input of the described output that operationally is coupled to described the 3rd power expansion module and the three digital signal that is synchronized with described first digital signal basically is provided.
95., it is characterized in that at least one in described first noise source or described second noise source comprises pseudo-random noise generator as the described system of claim 92.
96., it is characterized in that at least one in described first noise source or described second noise source comprises the nonlinear extensions signal generator as the described system of claim 92.
97., it is characterized in that at least one in described first noise source or described second noise source comprises the quadratic residue code sequence as the described system of claim 92.
98., it is characterized in that at least one in described first noise source or described second noise source comprises the polynomial sequence generator as the described system of claim 92.
99. a method comprises:
Receive first digital signal;
Receive a plurality of power expansion digital noise signals;
Use the part at least one subclass of described a plurality of power expansion digital noise signals to transform described digital signal successively, till detecting predetermined sequence in the very first time; And
Follow closely after the described very first time, use and transform described digital signal to generate second digital signal at employed described power expansion digital noise signal of the described very first time.
100. as the described method of claim 99, it is characterized in that, further comprise:
Use described second digital signal to come synchronous pll.
A kind of system comprises:
A plurality of noise sources, each noise source have an output that power expansion digital noise signal is provided;
Module is selected in input, it has a plurality of inputs, each input operationally is coupled to the described output of a corresponding noise source in described a plurality of noise source, and has one and can operate to be provided at the output of one of described power expansion digital noise signal that one of described a plurality of inputs place receives;
The signal transformation module, it has and operationally is coupled to described input and selects the input of the described output of module, operationally couple receiving the input of first digital signal, and the output by the numeral of described first digital signal of the signal transformation that receives via described input is provided; And
Comparison module, it has the described output that may be operably coupled to described signal transformation module receiving the input of described numeral, and the part of described numeral and the output of the indication of the comparative result of predetermined sequence are provided;
Wherein said input selects module can operate to select in described a plurality of input each with output successively.
A kind of method comprises:
Receive first digital signal, its expression is by second digital signal of one first power expansion signal transformation; And
In response to control excitation based on described first digital signal of the second power expansion signal transformation that realizes the described first power expansion function to produce three digital signal, wherein said three digital signal is represented described second digital signal.
As the described method of claim 102, it is characterized in that, further comprise:
Determine whether described three digital signal is the expression of described second digital signal.
As the described method of claim 103, it is characterized in that, further comprise:
When definite described three digital signal is the expression of described second digital signal, provide described three digital signal to clock distribution network.
As the described method of claim 103, it is characterized in that, further comprise:
When definite described three digital signal is not the expression of described second digital signal, prevent from described three digital signal is dispensed to clock distribution network.
As described method as described in the claim 102, it is characterized in that, receive described first digital signal and comprise via a transmission line and receive described first digital signal.
A kind of system comprises:
First input end, first expression of its receiving digital signals, the power of the described expression of wherein said digital signal is expanded with respect to described digital signal based on the first power expansion signal; And
Decoder module, it comprises second input, the 3rd input that is coupled to described first input end, reach first output that second expression of described digital signal is provided in response to the control excitation that receives at described the 3rd input end, wherein said second expression is described first expression of representing by the described digital signal of the second power expansion signal transformation that is substantially equal to the described first power expansion signal.
As the described system of claim 107, it is characterized in that, further comprise clock distribution network, described clock distribution network has input, and described input operationally is coupled to the described output of described decoder module to distribute described second expression of described digital signal.
A kind of method comprises:
Receive the first power expansion signal that first digital signal of the first power expansion digital noise signal transformation is used in expression via first transmission line;
Use is substantially similar to the second power expansion digital noise signal of the described first power expansion digital noise signal and transforms described power expansion signal is substantially similar to described first digital signal with generation second digital signal;
Use described second digital signal of the 3rd power expansion digital noise signal transformation to generate the second power expansion signal; And
Provide the described second power expansion signal to export second transmission line to.
110. as the described method of claim 109, it is characterized in that, further be included in and transform described second digital signal described second digital signal of convergent-divergent before.
111., it is characterized in that the described first power expansion signal is received and transforms at the circuit arrangement place as the described method of claim 109, and the described second power expansion signal is by described circuit arrangement transformation and provide for output.
112., it is characterized in that described circuit arrangement is one of integrated circuit or monolithic system as the described method of claim 111.
113., it is characterized in that described the 3rd power expansion digital noise signal is substantially similar to the described second power expansion digital noise signal as the described method of claim 109.
114., it is characterized in that at least one in described second power expansion digital noise signal or described the 3rd power expansion digital noise signal comprises the pseudorandom number signal as the described method of claim 109.
115., it is characterized in that at least one in described second power expansion digital noise signal or described the 3rd power expansion digital noise signal comprises the nonlinear extensions signal as the described method of claim 109.
116., it is characterized in that at least one in described second power expansion digital noise signal or described the 3rd power expansion digital noise signal comprises the quadratic residue code sequence as the described method of claim 109.
117., it is characterized in that at least one in described second power expansion digital noise signal or described the 3rd power expansion digital noise signal comprises polynomial value progression as the described method of claim 109.
118. a circuit arrangement comprises:
Operationally be coupled to the input of first transmission line;
Operationally be coupled to the output of second transmission line;
Decoder, it comprises:
First input end, its described input that operationally is coupled to described circuit arrangement is to receive the power expansion signal of expression by first digital signal of the first power expansion digital noise signal transformation;
Second input, it receives one second power expansion digital noise signal, and the wherein said second power expansion digital noise signal is substantially similar to the described first power expansion digital noise signal; And
Output, it provides second digital signal that is substantially similar to described first digital signal; And
Encoder, it comprises:
First input end, its described output that operationally is coupled to described decoder is to receive described second digital signal;
Second input, it receives the 3rd power expansion digital noise signal; And
Output, its described output that operationally is coupled to described circuit arrangement is to provide the second power expansion signal to export described second transmission line to.
119. as the described circuit arrangement of claim 118, it is characterized in that, further comprise:
First noise source, it has the output of described second input that operationally is coupled to described decoder; And
Second noise source, it has the output of described second input that operationally is coupled to described encoder.
120., it is characterized in that the described second power expansion digital noise signal is substantially similar to described the 3rd power expansion digital noise signal as the described circuit arrangement of claim 118.
121., it is characterized in that described first noise source and described second noise source are a same noise source as the described circuit arrangement of claim 120.
122. as the described circuit arrangement of claim 118, it is characterized in that, further comprise phase-locked loop, described phase-locked loop has the input of the described output that operationally is coupled to described decoder and operationally is coupled to the output of the described first input end of described encoder.
123. as the described circuit arrangement of claim 122, it is characterized in that, further comprise scaler, described scaler has the input of the described output that operationally is coupled to described phase-locked loop and operationally is coupled to the output of the described first input end of described encoder.
124., it is characterized in that at least one in described second power expansion digital noise signal or described the 3rd power expansion digital noise signal comprises the pseudorandom number signal as the described circuit arrangement of claim 118.
125., it is characterized in that at least one in described second power expansion digital noise signal or described the 3rd power expansion digital noise signal comprises the nonlinear extensions signal as the described circuit arrangement of claim 118.
126., it is characterized in that at least one in described second power expansion digital noise signal or described the 3rd power expansion digital noise signal comprises the quadratic residue code sequence as the described circuit arrangement of claim 118.
127., it is characterized in that at least one in described second power expansion digital noise signal or described the 3rd power expansion digital noise signal comprises polynomial value progression as the described circuit arrangement of claim 118.
128., it is characterized in that described circuit arrangement comprises one of integrated circuit or monolithic integrated circuit device as the described circuit arrangement of claim 118.
129. as the described circuit arrangement of claim 118, it is characterized in that, the described input that operationally is coupled to described first transmission line further operationally is coupled to the 3rd transmission line, and wherein said first transmission line and described the 3rd transmission line are represented the first differential pair transmission channel.
130. as the described circuit arrangement of claim 129, it is characterized in that, the described output that operationally is coupled to described second transmission line further operationally is coupled to the 4th transmission line, and wherein said second transmission line and described the 4th transmission line are represented the second differential pair transmission channel.
131. as the described circuit arrangement of claim 118, it is characterized in that, the described output that operationally is coupled to described second transmission line further operationally is coupled to the 4th transmission line, and wherein said second transmission line and described the 4th transmission line are represented the differential pair transmission channel.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| PCT/US2005/043349 WO2006060499A2 (en) | 2004-12-03 | 2005-12-01 | Techniques for reduced emi |
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| Publication Number | Publication Date |
|---|---|
| CN101379739A true CN101379739A (en) | 2009-03-04 |
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| CNA2005800473521A Pending CN101379739A (en) | 2005-12-01 | 2005-12-01 | Technology for reducing electromagnetic interference |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102467146A (en) * | 2010-11-18 | 2012-05-23 | 罗伯特·博世有限公司 | Method for suppressing interference |
| CN101719799B (en) * | 2009-12-02 | 2013-03-20 | 中兴通讯股份有限公司 | Device and method for reducing radiation of equipment |
| CN104753607A (en) * | 2013-12-31 | 2015-07-01 | 鸿富锦精密工业（深圳）有限公司 | Method for eliminating interference signal of mobile device and electronic device |
| CN109345996A (en) * | 2018-12-05 | 2019-02-15 | 惠科股份有限公司 | Timing controller, display driving assembly and display device |
| CN114600374A (en) * | 2019-10-13 | 2022-06-07 | 超飞跃有限公司 | Harmonic distortion reduction by dithering |
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2005
- 2005-12-01 CN CNA2005800473521A patent/CN101379739A/en active Pending
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101719799B (en) * | 2009-12-02 | 2013-03-20 | 中兴通讯股份有限公司 | Device and method for reducing radiation of equipment |
| CN102467146A (en) * | 2010-11-18 | 2012-05-23 | 罗伯特·博世有限公司 | Method for suppressing interference |
| US9423792B2 (en) | 2010-11-18 | 2016-08-23 | Robert Bosch Gmbh | Method for suppressing interference |
| CN104753607A (en) * | 2013-12-31 | 2015-07-01 | 鸿富锦精密工业（深圳）有限公司 | Method for eliminating interference signal of mobile device and electronic device |
| CN104753607B (en) * | 2013-12-31 | 2017-07-28 | 鸿富锦精密工业（深圳）有限公司 | Eliminate the method and electronic equipment of mobile device interference signal |
| CN109345996A (en) * | 2018-12-05 | 2019-02-15 | 惠科股份有限公司 | Timing controller, display driving assembly and display device |
| WO2020113683A1 (en) * | 2018-12-05 | 2020-06-11 | 惠科股份有限公司 | Timing control chip, display driving assembly, and display apparatus |
| CN114600374A (en) * | 2019-10-13 | 2022-06-07 | 超飞跃有限公司 | Harmonic distortion reduction by dithering |
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