CN101364584A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
CN101364584A
CN101364584A CNA2008101298489A CN200810129848A CN101364584A CN 101364584 A CN101364584 A CN 101364584A CN A2008101298489 A CNA2008101298489 A CN A2008101298489A CN 200810129848 A CN200810129848 A CN 200810129848A CN 101364584 A CN101364584 A CN 101364584A
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CN
China
Prior art keywords
lower bolster
semiconductor chip
pad
described lower
electrically connected
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Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
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CNA2008101298489A
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Chinese (zh)
Inventor
川岛庆一
吉田直人
细见刚
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Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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Publication of CN101364584A publication Critical patent/CN101364584A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601—Structure
    • H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48257—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01031—Gallium [Ga]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/1026—Compound semiconductors
    • H01L2924/1032—III-V
    • H01L2924/10329—Gallium arsenide [GaAs]

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Abstract

The invention relates to a semiconductor device capable of reducing noise index without changing exterior shape. The semiconductor device comprises a source frame having a die pad; a linear gate frame having a bonding pad; a semiconductor chip mounted on the die pad; wires which electrically connect a source terminal of the semiconductor chip to the die pad and electrically connect a gate terminal of the semiconductor chip to the bonding pad; and resin which seals the die pad, the bonding pad, the semiconductor chip, and the wires. The die pad is spaced from the bonding pad and diagonal to an extending direction of the gate frame, in the vicinity of the bonding pad.

Description

Semiconductor device
Technical field
The present invention relates to not change the semiconductor device that external shape just can reduce noise figure and increase gain.
Background technology
The semiconductor chip that will be formed with high frequency element such as GaAs FET is installed in source electrode framework (source frame) and goes up and carry out resin-sealed semiconductor device and be utilized (for example, referring to Patent Document 1).
Patent documentation 1 spy opens clear 61-16554 communique
Figure 20 is the plane graph that existing semiconductor devices is shown, and Figure 21 is the stereogram that existing semiconductor devices is shown.Source electrode framework 1 has lower bolster (die pad) 2 at central portion.On this lower bolster 2, semiconductor chip 3 is installed.In addition, rectilinear grid framework 4 and drain electrode framework 5 are provided with discretely with source electrode framework 1.This grid framework 4 and drain and 5 have pad (bonding pad) 6,7 respectively.To make pad 6,7 upsets (upset) with 2 one-tenth conplane modes of lower bolster of source electrode framework 1.
In addition, be electrically connected, with the drain terminal 10 and pad 7 electrical connections of semiconductor chip 3, with the gate terminal 11 and pad 6 electrical connections of semiconductor chip 3 by the source terminal 9 and the lower bolster 2 of a plurality of leads 8 with semiconductor chip 3.And lower bolster 2, pad 6,7, semiconductor chip 3 and a plurality of lead 8 are by model resin (mold resin) 12 sealings.
In existing semiconductor devices, lower bolster 2 is cut into rectangle, and pad 6 is cut along the shape of lower bolster 2.Thus, the interval of source electrode framework 1 and grid framework 4 is narrower, and both opposed areas become big.Consequently, the electric capacity between source electrode framework 1 and the grid framework 4 becomes big.And, from following mathematical expression (1), (2) as can be known, the problem that noise figure NF can increase when having the capacitor C gs increase between source electrode framework 1 and the grid framework 4.
(formula 1)
NF = 1 + ω f T A · · · ( 1 )
(formula 2)
f T ∝ 1 C gs · · · ( 2 )
Wherein, NF is a noise figure, and ω is an angular frequency, f TBe current gain blocking frequency, A is a constant, and Cgs is an electric capacity between source gate.
For the noise figure that makes semiconductor device reduces, change the external shape of semiconductor device, make the interval of source electrode framework 1 and grid framework 4 become big, and the opposed area that reduces both get final product.But from the dimensional standardization of semiconductor device or the aspect of manufacturing cost, it is difficult changing external shape.
In addition, according to following mathematical expression (3) as can be known, for the gain (maximum available gain (MAG)) that makes semiconductor device increases, the capacitor C dg that reduces between source electrode framework 1 and the grid framework 4 gets final product.
(formula 3)
MAG = B Cdg ( k - k 2 - 1 ) · · · ( 3 )
Herein, MAG is maximum available gain (MAG), and k is the coefficient of stability, and B is a constant, and Cdg is an electric capacity between the drain electrode grid.
In order to reduce Cdg, the electric coupling between grid drain electrode is died down.This need make between gate-source, and capacitor C ds increases between capacitor C gs and drain-source.By (1) formula, when Cgs increased, noise figure increased.Therefore, if Cds is increased, can not increase noise figure and can increase gain.
For Cds is increased, change the external shape of semiconductor device, the opposed area increase of source electrode framework 1 and drain electrode framework 5 is got final product.But from the dimensional standardization of semiconductor device or the aspect of manufacturing cost, it is difficult changing external shape.
Summary of the invention
The present invention carries out in order to solve aforesaid problem, and its first purpose provides a kind of semiconductor device that external shape just can reduce noise figure that do not change.
Second purpose of the present invention provides a kind of semiconductor device that external shape just can increase gain that do not change.
The semiconductor device of first invention is characterised in that to have: the source electrode framework with lower bolster; Rectilinear grid framework has the pad that separates with described lower bolster; Be installed in the semiconductor chip on the described lower bolster; A plurality of leads are electrically connected the source terminal of described semiconductor chip and described lower bolster, and the gate terminal and the described pad of described semiconductor chip is electrically connected; Resin, with described lower bolster, described pad, described semiconductor chip and described a plurality of lead sealing, wherein said lower bolster is being cut on the direction that the bearing of trend with respect to described grid framework tilts near the described pad.
The semiconductor device of second invention is characterised in that to have: the source electrode framework with lower bolster; Rectilinear drain electrode framework has the pad that separates with described lower bolster; Be installed in the semiconductor chip on the described lower bolster; A plurality of leads are electrically connected the source terminal of described semiconductor chip and described lower bolster, and the drain terminal and the described pad of described semiconductor chip is electrically connected; Resin, with described lower bolster, described pad, described semiconductor chip and described a plurality of lead sealing, the width of wherein said drain electrode framework broadens at described pad place.
The semiconductor device of the 3rd invention is characterised in that to have: the source electrode framework with lower bolster; The drain electrode framework has the pad that separates with described lower bolster; Be installed in the semiconductor chip on the described lower bolster; A plurality of leads will be electrically connected the source terminal of described semiconductor chip and the drain terminal and the described pad of electrical connection of described lower bolster and described semiconductor chip; Resin, with described lower bolster, described pad, described semiconductor chip and described a plurality of lead sealing, wherein said lower bolster " コ " shape ground surrounds the peripheral part of described pad.
The semiconductor device of the 4th invention is characterised in that to have: the source electrode framework with lower bolster; The drain electrode framework has the pad that separates with described lower bolster; Be installed in the semiconductor chip on the described lower bolster; A plurality of leads are with the source terminal of described semiconductor chip with described lower bolster is electrically connected and the drain terminal and the described pad of described semiconductor chip is electrically connected; Resin, with described lower bolster, described pad, described semiconductor chip and described a plurality of lead sealing, wherein said pad " L " shape ground surrounds the peripheral part of described lower bolster.
The semiconductor device of the 5th invention is characterised in that to have: the source electrode framework with lower bolster; The drain electrode framework has the pad that separates with described lower bolster; Be installed in the semiconductor chip on the described lower bolster; A plurality of leads are with the source terminal of described semiconductor chip with described lower bolster is electrically connected and the drain terminal and the described pad of described semiconductor chip is electrically connected; Resin, with described lower bolster, described pad, described semiconductor chip and described a plurality of lead sealing, wherein said lower bolster and the opposed part of described pad are interdigital structure.
The semiconductor device of the 6th invention is characterised in that to have: the source electrode framework with lower bolster; The drain electrode framework has the pad that separates with described lower bolster; Be installed in the semiconductor chip on the described lower bolster; A plurality of leads are with the source terminal of described semiconductor chip with described lower bolster is electrically connected and the drain terminal and the described pad of described semiconductor chip is electrically connected; Resin, with described lower bolster, described pad, described semiconductor chip and described a plurality of lead sealing, wherein said pad configuration is above described lower bolster.
The semiconductor device of the 7th invention is characterised in that to have: the source electrode framework with lower bolster; The drain electrode framework separates with described lower bolster; Be installed in the semiconductor chip on the described lower bolster; A plurality of leads are with the source terminal of described semiconductor chip with described lower bolster is electrically connected and the drain terminal and the described pad of described semiconductor chip is electrically connected; Resin, with described lower bolster, described pad, described semiconductor chip and described a plurality of lead sealing, wherein said drain electrode chassis configuration is below described lower bolster.
The semiconductor device of the 8th invention is characterised in that to have: the source electrode framework with lower bolster; The drain electrode framework has the pad that separates with described lower bolster; Be installed in the semiconductor chip on the described lower bolster; A plurality of leads are with the source terminal of described semiconductor chip with described lower bolster is electrically connected and the drain terminal and the described pad of described semiconductor chip is electrically connected; Resin, with described lower bolster, described pad, described semiconductor chip and described a plurality of lead sealing, wherein said lower bolster extends below described pad.
The semiconductor device of the 9th invention is characterised in that to have: the source electrode framework with lower bolster; The drain electrode framework has the pad that separates with described lower bolster; Be installed in the semiconductor chip on the described lower bolster; A plurality of leads are with the source terminal of described semiconductor chip with described lower bolster is electrically connected and the drain terminal and the described pad of described semiconductor chip is electrically connected; Resin, with described lower bolster, described pad, described semiconductor chip and described a plurality of lead sealing, wherein said lower bolster and the opposed part of described pad are extended downwards.
The semiconductor device of the tenth invention is characterised in that to have: the source electrode framework with lower bolster; Rectilinear grid framework has the pad that separates with described lower bolster; Be installed in the semiconductor chip on the described lower bolster; A plurality of leads are with the source terminal of described semiconductor chip with described lower bolster is electrically connected and the gate terminal and the described pad of described semiconductor chip is electrically connected; Resin, with described lower bolster, described pad, described semiconductor chip and described a plurality of lead sealing, the width of wherein said grid framework broadens at described pad place.
The semiconductor device of the 11 invention is characterised in that to have: the source electrode framework with lower bolster; The grid framework has the pad that separates with described lower bolster; Be installed in the semiconductor chip on the described lower bolster; A plurality of leads are with the source terminal of described semiconductor chip with described lower bolster is electrically connected and the gate terminal and the described pad of described semiconductor chip is electrically connected; Resin, with described lower bolster, described pad, described semiconductor chip and described a plurality of lead sealing, wherein said lower bolster " コ " shape ground surrounds the peripheral part of described pad.
The semiconductor device of the 12 invention is characterised in that to have: the source electrode framework with lower bolster; The grid framework has the pad that separates with described lower bolster; Be installed in the semiconductor chip on the described lower bolster; A plurality of leads are with the source terminal of described semiconductor chip with described lower bolster is electrically connected and the gate terminal and the described pad of described semiconductor chip is electrically connected; Resin, with described lower bolster, described pad, described semiconductor chip and described a plurality of lead sealing, wherein said pad " L " shape ground surrounds the peripheral part of described lower bolster.
The semiconductor device of the 13 invention is characterised in that to have: the source electrode framework with lower bolster; The grid framework has the pad that separates with described lower bolster; Be installed in the semiconductor chip on the described lower bolster; A plurality of leads are with the source terminal of described semiconductor chip with described lower bolster is electrically connected and the gate terminal and the described pad of described semiconductor chip is electrically connected; Resin, with described lower bolster, described pad, described semiconductor chip and described a plurality of lead sealing, wherein said lower bolster and the opposed part of described pad are interdigital structure.
The semiconductor device of the 14 invention is characterised in that to have: the source electrode framework with lower bolster; The grid framework has the pad that separates with described lower bolster; Be installed in the semiconductor chip on the described lower bolster; A plurality of leads are with the source terminal of described semiconductor chip with described lower bolster is electrically connected and the gate terminal and the described pad of described semiconductor chip is electrically connected; Resin, with described lower bolster, described pad, described semiconductor chip and described a plurality of lead sealing, wherein said pad configuration is above described lower bolster.
The semiconductor device of the 15 invention is characterised in that to have: the source electrode framework with lower bolster; The grid framework separates with described lower bolster; Be installed in the semiconductor chip on the described lower bolster; A plurality of leads are with the source terminal of described semiconductor chip with described lower bolster is electrically connected and the gate terminal and the described pad of described semiconductor chip is electrically connected; Resin, with described lower bolster, described pad, described semiconductor chip and described a plurality of lead sealing, wherein said grid chassis configuration is below described lower bolster.
The semiconductor device of the 16 invention is characterised in that to have: the source electrode framework with lower bolster; The grid framework has the pad that separates with described lower bolster; Be installed in the semiconductor chip on the described lower bolster; A plurality of leads are with the source terminal of described semiconductor chip with described lower bolster is electrically connected and the gate terminal and the described pad of described semiconductor chip is electrically connected; Resin, with described lower bolster, described pad, described semiconductor chip and described a plurality of lead sealing, wherein said lower bolster described pad below extend.
The semiconductor device of the 17 invention is characterised in that to have: the source electrode framework with lower bolster; The grid framework has the pad that separates with described lower bolster; Be installed in the semiconductor chip on the described lower bolster; A plurality of leads are with the source terminal of described semiconductor chip with described lower bolster is electrically connected and the gate terminal and the described pad of described semiconductor chip is electrically connected; Resin, with described lower bolster, described pad, described semiconductor chip and described a plurality of lead sealing, wherein said lower bolster and the opposed part of described pad are extended downwards.
According to first invention, do not change the noise figure that external shape just can reduce semiconductor device.According to second～the 17 invention, do not change external shape and just can increase gain.
Description of drawings
Fig. 1 is the plane graph that the semiconductor device of embodiment of the present invention 1 is shown.
Fig. 2 is the plane graph that the semiconductor device of embodiment of the present invention 2 is shown.
Fig. 3 is the plane graph that the semiconductor device of embodiment of the present invention 3 is shown.
Fig. 4 is the plane graph that the semiconductor device of embodiment of the present invention 4 is shown.
Fig. 5 is the plane graph that the semiconductor device of embodiment of the present invention 5 is shown.
Fig. 6 is the plane graph that the semiconductor device of embodiment of the present invention 6 is shown.
Fig. 7 is the stereogram that the semiconductor device of embodiment of the present invention 7 is shown.
Fig. 8 is the stereogram that the semiconductor device of embodiment of the present invention 8 is shown.
Fig. 9 is the stereogram that the semiconductor device of embodiment of the present invention 9 is shown.
Figure 10 is the stereogram that the semiconductor device of embodiment of the present invention 10 is shown.
Figure 11 is the plane graph that the semiconductor device of embodiment of the present invention 11 is shown.
Figure 12 is the plane graph that the semiconductor device of embodiment of the present invention 12 is shown.
Figure 13 is the plane graph that the semiconductor device of embodiment of the present invention 13 is shown.
Figure 14 is the plane graph that the semiconductor device of embodiment of the present invention 14 is shown.
Figure 15 is the plane graph that the semiconductor device of embodiment of the present invention 15 is shown.
Figure 16 is the stereogram that the semiconductor device of embodiment of the present invention 16 is shown.
Figure 17 is the stereogram that the semiconductor device of embodiment of the present invention 17 is shown.
Figure 18 is the stereogram that the semiconductor device of embodiment of the present invention 18 is shown.
Figure 19 is the stereogram that the semiconductor device of embodiment of the present invention 19 is shown.
Figure 20 is the plane graph that existing semiconductor devices is shown.
Figure 21 is the stereogram that existing semiconductor devices is shown.
Embodiment
Execution mode 1
Fig. 1 is the plane graph that the semiconductor device of embodiment of the present invention 1 is shown.Source electrode framework 1 has lower bolster 2 at central portion.On this lower bolster 2, semiconductor chip 3 is installed.On semiconductor chip 3, form high frequency elements such as GaAs FET.In addition, rectilinear grid framework 4 and drain electrode framework 5 are provided with discretely with source electrode framework 1.This grid framework 4 and drain electrode framework 5 have pad 6,7 respectively.
In addition, be electrically connected, with the drain terminal 10 and pad 7 electrical connections of semiconductor chip 3, with the gate terminal 11 and pad 6 electrical connections of semiconductor chip 3 by the source terminal 9 and the lower bolster 2 of a plurality of leads 8 with semiconductor chip 3.And lower bolster 2, pad 6,7, semiconductor chip 3 and a plurality of lead 8 are sealed by model resin 12 (resin).
In the present embodiment, for lower bolster 2, near pad 6, on the direction that the bearing of trend with respect to grid framework 4 tilts, be cut.That is,, near pad 6, be cut to direction away from grid framework 4 for lower bolster 2.And, for pad 6, near lower bolster 2, with lower bolster 2 along inclined direction the cutting partial parallel be cut.
According to said structure, can make the interval of source electrode framework 1 and grid framework 4 become big, both opposed areas are reduced.Therefore, because the electric capacity between source electrode framework 1 and the grid framework 4 is reduced, the noise figure of semiconductor device is reduced so do not change external shape.
Execution mode 2
Fig. 2 is the plane graph that the semiconductor device of embodiment of the present invention 2 is shown.It is big that the width of drain electrode framework 5 becomes at pad 7 places.And lower bolster 2 and pad 7 opposed parts are cut on the incline direction with respect to drain electrode framework 5 bearing of trends respectively.Other structures are identical with execution mode 1.
According to said structure, the opposed area of source electrode framework 1 and drain electrode framework 5 is increased.Therefore, because the electric capacity between source electrode framework 1 and the drain electrode framework 5 is increased, the noise figure of semiconductor device is reduced so do not change external shape.Other effects are identical with execution mode 1.
Execution mode 3
Fig. 3 is the plane graph that the semiconductor device of embodiment of the present invention 3 is shown.It is big that the width of drain electrode framework 5 becomes at pad 7 places.And lower bolster 2 and pad 7 opposed parts are cut steppedly.Other structures are identical with execution mode 1.
According to said structure, the opposed area of source electrode framework 1 and drain electrode framework 5 is further increased than execution mode 2.Therefore, gain is further increased.Other effects are identical with execution mode 1.
Execution mode 4
Fig. 4 is the plane graph that the semiconductor device of embodiment of the present invention 4 is shown.2 one-tenth " コ " shapes of lower bolster are surrounded the peripheral part of pad 7.Other structures are identical with execution mode 1.
According to said structure, the opposed area of source electrode framework 1 and drain electrode framework 5 is increased.Therefore, because the electric capacity between source electrode framework 1 and the drain electrode framework 5 is increased, just can not increase gain so do not change external shape.Other effects are identical with execution mode 1.
Execution mode 5
Fig. 5 is the plane graph that the semiconductor device of embodiment of the present invention 5 is shown.7 one-tenth " L " shapes of pad are surrounded the peripheral part of lower bolster 2.Other structures are identical with execution mode 1.
According to said structure, the opposed area of source electrode framework 1 and drain electrode framework 5 is increased.Therefore, because the electric capacity between source electrode framework 1 and the drain electrode framework 5 is increased, just can not increase gain so do not change external shape.Other effects are identical with execution mode 1.
Execution mode 6
Fig. 6 is the plane graph that the semiconductor device of embodiment of the present invention 6 is shown.Lower bolster 2 and pad 7 opposed parts are interdigital (inter-digital) structures.Other structures are identical with execution mode 1.
According to said structure, the opposed area of source electrode framework 1 and drain electrode framework 5 is increased.Therefore, because the electric capacity between source electrode framework 1 and the drain electrode framework 5 is increased, just can not increase gain so do not change external shape.Other effects are identical with execution mode 1.
Execution mode 7
Fig. 7 is the stereogram that the semiconductor device of embodiment of the present invention 7 is shown.Pad 7 is configured in the top of lower bolster 2.Other structures are identical with execution mode 1.
According to said structure, the opposed area of source electrode framework 1 and drain electrode framework 5 is increased.Therefore, because the electric capacity between source electrode framework 1 and the drain electrode framework 5 is increased, just can not increase gain so do not change external shape.Other effects are identical with execution mode 1.
Execution mode 8
Fig. 8 is the stereogram that the semiconductor device of embodiment of the present invention 8 is shown.Drain electrode framework 5 is configured in the below of lower bolster 2.And, the pad 7 of drain electrode framework 5 is not set, the drain terminal 10 of drain electrode framework 5 and semiconductor chip 3 is by wire-bonded.Other structures are identical with execution mode 1.
According to said structure, the opposed area of source electrode framework 1 and drain electrode framework 5 is increased.Therefore, because the electric capacity between source electrode framework 1 and the drain electrode framework 5 is increased, just can not increase gain so do not change external shape.Other effects are identical with execution mode 1.
Execution mode 9
Fig. 9 is the stereogram that the semiconductor device of embodiment of the present invention 9 is shown.Lower bolster 2 extends below pad 7.Other structures are identical with execution mode 1.
According to said structure, the opposed area of source electrode framework 1 and drain electrode framework 5 is increased.Therefore, because the electric capacity between source electrode framework 1 and the drain electrode framework 5 is increased, just can not increase gain so do not change external shape.Other effects are identical with execution mode 1.
Execution mode 10
Figure 10 is the stereogram that the semiconductor device of embodiment of the present invention 10 is shown.Lower bolster 2 and pad 7 opposed parts are extended downwards.Other structures are identical with execution mode 1.
According to said structure, the opposed area of source electrode framework 1 and drain electrode framework 5 is increased.Therefore, because the electric capacity between source electrode framework 1 and the drain electrode framework 5 is increased, just can not increase gain so do not change external shape.Other effects are identical with execution mode 1.
Execution mode 11
Figure 11 is the plane graph that the semiconductor device of embodiment of the present invention 11 is shown.The width of grid framework 4 broadens at pad 6 places.And lower bolster 2 and pad 6 opposed parts are cut on the bearing of trend incline direction with respect to grid framework 4 respectively.Other structures are identical with execution mode 1.
According to said structure, the opposed area of source electrode framework 1 and grid framework 4 is increased.Therefore, because the electric capacity between source electrode framework 1 and the grid framework 4 is increased, just can not increase gain so do not change external shape.
Execution mode 12
Figure 12 is the plane graph that the semiconductor device of embodiment of the present invention 12 is shown.It is big that the width of grid framework 4 becomes at pad 6 places.And lower bolster 2 and pad 6 opposed parts are cut steppedly.Other structures are identical with execution mode 1.
According to said structure, the opposed area of source electrode framework 1 and grid framework 4 is further increased than execution mode 2.Therefore, gain is further increased.
Execution mode 13
Figure 13 is the plane graph that the semiconductor device of embodiment of the present invention 13 is shown.2 one-tenth " コ " shapes of lower bolster are surrounded the peripheral part of pad 6.Other structures are identical with execution mode 1.
According to said structure, the opposed area of source electrode framework 1 and grid framework 4 is increased.Therefore, because the electric capacity between source electrode framework 1 and the grid framework 4 is increased, just can not increase gain so do not change external shape.
Execution mode 14
Figure 14 is the plane graph that the semiconductor device of embodiment of the present invention 14 is shown.6 one-tenth " L " shapes of pad are surrounded the peripheral part of lower bolster 2.Other structures are identical with execution mode 1.
According to said structure, the opposed area of source electrode framework 1 and grid framework 4 is increased.Therefore, because the electric capacity between source electrode framework 1 and the grid framework 4 is increased, just can not increase gain so do not change external shape.
Execution mode 15
Figure 15 is the plane graph that the semiconductor device of embodiment of the present invention 15 is shown.Lower bolster 2 and pad 6 opposed parts are interdigital structure.Other structures are identical with execution mode 1.
According to said structure, the opposed area of source electrode framework 1 and grid framework 4 is increased.Therefore, because the electric capacity between source electrode framework 1 and the grid framework 4 is increased, just can not increase gain so do not change external shape.
Execution mode 16
Figure 16 is the stereogram that the semiconductor device of embodiment of the present invention 16 is shown.Pad 6 is configured in the top of lower bolster 2.Other structures are identical with execution mode 1.
According to said structure, the opposed area of source electrode framework 1 and grid framework 4 is increased.Therefore, because the electric capacity between source electrode framework 1 and the grid framework 4 is increased, just can not increase gain so do not change external shape.
Execution mode 17
Figure 17 is the stereogram that the semiconductor device of embodiment of the present invention 17 is shown.Grid framework 4 is configured in the below of lower bolster 2.And, the pad 6 of grid framework 4 is not set, the gate terminal 11 of grid framework 4 and semiconductor chip 3 is by wire-bonded.Other structures are identical with execution mode 1.
According to said structure, the opposed area of source electrode framework 1 and grid framework 4 is increased.Therefore, because the electric capacity between source electrode framework 1 and the grid framework 4 is increased, just can not increase gain so do not change external shape.
Execution mode 18
Figure 18 is the stereogram that the semiconductor device of embodiment of the present invention 18 is shown.Lower bolster 2 extends below pad 6.Other structures are identical with execution mode 1.
According to said structure, the opposed area of source electrode framework 1 and grid framework 4 is increased.Therefore, because the electric capacity between source electrode framework 1 and the grid framework 4 is increased, just can not increase gain so do not change external shape.
Execution mode 19
Figure 19 is the stereogram that the semiconductor device of embodiment of the present invention 19 is shown.Lower bolster 2 and pad 6 opposed parts extend to the below.Other structures are identical with execution mode 1.
According to said structure, the opposed area of source electrode framework 1 and grid framework 4 is increased.Therefore, because the electric capacity between source electrode framework 1 and the grid framework 4 is increased, just can not increase gain so do not change external shape.

Claims (22)

1. a semiconductor device is characterized in that,
Have: source electrode framework with lower bolster; Rectilinear grid framework has the pad that separates with described lower bolster; Be installed in the semiconductor chip on the described lower bolster; A plurality of leads are electrically connected the source terminal of described semiconductor chip and described lower bolster, and the gate terminal and the described pad of described semiconductor chip is electrically connected; Resin, with described lower bolster, described pad, described semiconductor chip and described a plurality of lead sealing,
Described lower bolster is being cut on the direction that the bearing of trend with respect to described grid framework tilts near the described pad.
2. according to the semiconductor device of claim 1, it is characterized in that,
Described pad near described lower bolster with described lower bolster the partial parallel of incline direction cutting be cut.
3. a semiconductor device is characterized in that,
Have: source electrode framework with lower bolster; Rectilinear drain electrode framework has the pad that separates with described lower bolster; Be installed in the semiconductor chip on the described lower bolster; A plurality of leads are electrically connected the source terminal of described semiconductor chip and described lower bolster, and the drain terminal and the described pad of described semiconductor chip is electrically connected; Resin, with described lower bolster, described pad, described semiconductor chip and described a plurality of lead sealing,
The width of described drain electrode framework broadens at described pad place.
4. according to the semiconductor device of claim 3, it is characterized in that,
Described lower bolster and the opposed part of described pad are cut on the direction that the bearing of trend with respect to described drain electrode framework tilts respectively.
5. according to the semiconductor device of claim 3, it is characterized in that,
Described lower bolster and the opposed part of described pad are cut steppedly.
6. a semiconductor device is characterized in that,
Have: source electrode framework with lower bolster; The drain electrode framework has the pad that separates with described lower bolster; Be installed in the semiconductor chip on the described lower bolster; A plurality of leads are electrically connected the source terminal of described semiconductor chip and described lower bolster, and the drain terminal of described semiconductor chip and described pad will be electrically connected; Resin, with described lower bolster, described pad, described semiconductor chip and described a plurality of lead sealing,
Described lower bolster " コ " shape ground surrounds the peripheral part of described pad.
7. a semiconductor device is characterized in that,
Have: source electrode framework with lower bolster; The drain electrode framework has the pad that separates with described lower bolster; Be installed in the semiconductor chip on the described lower bolster; A plurality of leads are electrically connected the source terminal of described semiconductor chip and described lower bolster, and the drain terminal and the described pad of described semiconductor chip is electrically connected; Resin, with described lower bolster, described pad, described semiconductor chip and described a plurality of lead sealing,
Described pad " L " shape ground surrounds the peripheral part of described lower bolster.
8. a semiconductor device is characterized in that,
Have: source electrode framework with lower bolster; The drain electrode framework has the pad that separates with described lower bolster; Be installed in the semiconductor chip on the described lower bolster; A plurality of leads are electrically connected the source terminal of described semiconductor chip and described lower bolster, and the drain terminal and the described pad of described semiconductor chip is electrically connected; Resin, with described lower bolster, described pad, described semiconductor chip and described a plurality of lead sealing,
Described lower bolster and the opposed part of described pad are interdigital structure.
9. a semiconductor device is characterized in that,
Have: source electrode framework with lower bolster; The drain electrode framework has the pad that separates with described lower bolster; Be installed in the semiconductor chip on the described lower bolster; A plurality of leads are electrically connected the source terminal of described semiconductor chip and described lower bolster, and the drain terminal and the described pad of described semiconductor chip is electrically connected; Resin, with described lower bolster, described pad, described semiconductor chip and described a plurality of lead sealing,
Described pad configuration is above described lower bolster.
10. a semiconductor device is characterized in that,
Have: source electrode framework with lower bolster; The drain electrode framework separates with described lower bolster; Be installed in the semiconductor chip on the described lower bolster; A plurality of leads are electrically connected the source terminal of described semiconductor chip and described lower bolster, and the drain terminal and the described pad of described semiconductor chip is electrically connected; Resin, with described lower bolster, described pad, described semiconductor chip and described a plurality of lead sealing,
Described drain electrode chassis configuration is below described lower bolster.
11. a semiconductor device is characterized in that,
Have: source electrode framework with lower bolster; The drain electrode framework has the pad that separates with described lower bolster; Be installed in the semiconductor chip on the described lower bolster; A plurality of leads are electrically connected the source terminal of described semiconductor chip and described lower bolster, and the drain terminal and the described pad of described semiconductor chip is electrically connected; Resin, with described lower bolster, described pad, described semiconductor chip and described a plurality of lead sealing,
Described lower bolster extends below described pad.
12. a semiconductor device is characterized in that,
Have: source electrode framework with lower bolster; The drain electrode framework has the pad that separates with described lower bolster; Be installed in the semiconductor chip on the described lower bolster; A plurality of leads are electrically connected the source terminal of described semiconductor chip and described lower bolster, and the drain terminal and the described pad of described semiconductor chip is electrically connected; Resin, with described lower bolster, described pad, described semiconductor chip and described a plurality of lead sealing,
Described lower bolster and the opposed part of described pad are extended downwards.
13. a semiconductor device is characterized in that,
Have: source electrode framework with lower bolster; Rectilinear grid framework has the pad that separates with described lower bolster; Be installed in the semiconductor chip on the described lower bolster; A plurality of leads are electrically connected the source terminal of described semiconductor chip and described lower bolster, and the gate terminal and the described pad of described semiconductor chip is electrically connected; Resin, with described lower bolster, described pad, described semiconductor chip and described a plurality of lead sealing,
The width of described grid framework broadens at described pad place.
14. the semiconductor device according to claim 13 is characterized in that,
Described lower bolster and the opposed part of described pad are cut on the direction that the bearing of trend with respect to described grid framework tilts respectively.
15. the semiconductor device according to claim 13 is characterized in that,
Described lower bolster and the opposed part of described pad are cut steppedly.
16. a semiconductor device is characterized in that,
Have: source electrode framework with lower bolster; The grid framework has the pad that separates with described lower bolster; Be installed in the semiconductor chip on the described lower bolster; A plurality of leads are electrically connected the source terminal of described semiconductor chip and described lower bolster, and the gate terminal and the described pad of described semiconductor chip is electrically connected; Resin, with described lower bolster, described pad, described semiconductor chip and described a plurality of lead sealing,
Described lower bolster " コ " shape ground surrounds the peripheral part of described pad.
17. a semiconductor device is characterized in that,
Have: source electrode framework with lower bolster; The grid framework has the pad that separates with described lower bolster; Be installed in the semiconductor chip on the described lower bolster; A plurality of leads are electrically connected the source terminal of described semiconductor chip and described lower bolster, and the gate terminal and the described pad of described semiconductor chip is electrically connected; Resin, with described lower bolster, described pad, described semiconductor chip and described a plurality of lead sealing,
Described pad " L " shape ground surrounds the peripheral part of described lower bolster.
18. a semiconductor device is characterized in that,
Have: source electrode framework with lower bolster; The grid framework has the pad that separates with described lower bolster; Be installed in the semiconductor chip on the described lower bolster; A plurality of leads are electrically connected the source terminal of described semiconductor chip and described lower bolster, and the gate terminal and the described pad of described semiconductor chip is electrically connected; Resin, with described lower bolster, described pad, described semiconductor chip and described a plurality of lead sealing,
Described lower bolster and the opposed part of described pad are interdigital structure.
19. a semiconductor device is characterized in that,
Have: source electrode framework with lower bolster; The grid framework has the pad that separates with described lower bolster; Be installed in the semiconductor chip on the described lower bolster; A plurality of leads are electrically connected the source terminal of described semiconductor chip and described lower bolster, and the gate terminal and the described pad of described semiconductor chip is electrically connected; Resin, with described lower bolster, described pad, described semiconductor chip and described a plurality of lead sealing,
Described pad configuration is above described lower bolster.
20. a semiconductor device is characterized in that,
Have: source electrode framework with lower bolster; The grid framework separates with described lower bolster; Be installed in the semiconductor chip on the described lower bolster; A plurality of leads are electrically connected the source terminal of described semiconductor chip and described lower bolster, and the gate terminal and the described pad of described semiconductor chip is electrically connected; Resin, with described lower bolster, described pad, described semiconductor chip and described a plurality of lead sealing,
Described grid chassis configuration is below described lower bolster.
21. a semiconductor device is characterized in that,
Have: source electrode framework with lower bolster; The grid framework has the pad that separates with described lower bolster; Be installed in the semiconductor chip on the described lower bolster; A plurality of leads are electrically connected the source terminal of described semiconductor chip and described lower bolster, and the gate terminal and the described pad of described semiconductor chip is electrically connected; Resin, with described lower bolster, described pad, described semiconductor chip and described a plurality of lead sealing,
Described lower bolster described pad below extend.
22. a semiconductor device is characterized in that,
Have: source electrode framework with lower bolster; The grid framework has the pad that separates with described lower bolster; Be installed in the semiconductor chip on the described lower bolster; A plurality of leads are electrically connected the source terminal of described semiconductor chip and described lower bolster, and the gate terminal and the described pad of described semiconductor chip is electrically connected; Resin, with described lower bolster, described pad, described semiconductor chip and described a plurality of lead sealing,
Described lower bolster and the opposed part of described pad are extended downwards.
CNA2008101298489A 2007-08-10 2008-08-07 Semiconductor device Pending CN101364584A (en)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP2007209043 2007-08-10
JP2007209043 2007-08-10
JP2007328904 2007-12-20
JP2008105528 2008-04-15

Publications (1)

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CN101364584A true CN101364584A (en) 2009-02-11

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Country Status (1)

Country Link
CN (1) CN101364584A (en)

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