CN101359676B - Multi- phase change memory array and multi-digit phase change memory - Google Patents
Multi- phase change memory array and multi-digit phase change memory Download PDFInfo
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Abstract
Disclosed is a multi-bit phase transition memory array which comprises a plurality of multi-phase variable memories, each of which is composed of a first bit line, a second bit line, a first phase transition material layer, a second phase transition material layer and a switch element. The first phase transition material layer is coupled between the first bit line and the second bit line; the second phase transition material layer is coupled with a source electrode line; and the switch element is coupled through the source electrode or the drain electrode thereof between the first phase transition material layer and the second phase transition material layer, with the grid coupled to the bit lines. The first phase transition material layer and the second phase transition material layer have different amorphous resistances and different amorphous currents.
Description
Technical field
The present invention is relevant for Ovonics unified memory, particularly relevant for the multidigit Ovonics unified memory.
Background technology
Growth along with the portable applications product, make the demand of nonvolatile memory that the trend that day by day increases be arranged, the Ovonics unified memory technology has been regarded as the non-volatile memory technologies of next from generation to generation potentialization owing to have competitive characteristics such as speed, power, capacity, reliability, process integration degree and cost.
Figure 1A and 1B are the structure chart of the disclosed traditional multidigit Ovonics unified memory of U.S. patent application case US2005/0112896A1, its with GST as the phase change memory material, this multidigit Ovonics unified memory is made up of multilayer GST material layer and multiple layer metal layer crossover, each GST material layer is the interlayer of two metal levels, though the resistance coefficient of each GST material layer is identical, but because its height h1＞h2＞h3＞h4, and A1＜A2＜A3＜A4, make R1＞R2＞R3＞R4, and crystallization electric current I set1＜Iset2＜Iset3＜Iset4 that it is required, if give Iset1＜I＜Iset2, has only material layer GST1 crystallization, as Iset2＜I＜Iset3, has only material layer GST1 with the GST2 crystallization, as Iset3＜I＜Iset4, has only material layer GST1, GST2 is with the GST3 crystallization, if Iset4＜I, all GST material layers crystallization all then, wherein, I is the electric current that is applied, apply the size of electric current by control, the multidigit Ovonics unified memory can be distinguished 4 kinds of crystallization states, therefore single Ovonics unified memory just can obtain 2 storage capacity, and when applying electric current I greater than Ireset4, all GST material layers all are returned to non-crystalline state, that is the remember condition of this Ovonics unified memory is erased.
Summary of the invention
A kind of multidigit phase-change memory array, this multidigit phase-change memory array comprises a plurality of multidigit Ovonics unified memories, each multidigit Ovonics unified memory comprises first bit line and second bit line, first phase-change material layer, second phase-change material layer and switch element, this first phase-change material layer is coupled between this first bit line and this second bit line, this second phase-change material layer is coupled to source electrode line, this switch element is coupled between this first phase-change material layer and this second phase-change material layer by its source/drain electrode, and its grid is coupled to word line, wherein, this first phase-change material layer has different decrystallized attitude resistance values with this second phase-change material layer, and different decrystallized attitude electric currents.
For above-mentioned and other purposes of the present invention, feature and advantage can be become apparent, cited below particularlyly go out preferred embodiment, and cooperate appended graphicly, be described in detail below.
Description of drawings
Figure 1A and 1B are the structure chart of the disclosed traditional multidigit Ovonics unified memory of U.S. patent application case US2005/0112896A1.
Fig. 2 A is depicted as the schematic diagram according to the multidigit phase-change memory array of one embodiment of the invention.
Fig. 2 B to 2E is the structural section figure according to the multidigit Ovonics unified memory shown in Fig. 2 A.
The main element symbol description
BL1, BL2, BL3～first bit line;
BL1 ', BL2 ', BL3 '～second bit line;
GST1～first phase-change material layer;
GST2～second phase-change material layer;
TN～metal oxide semiconductor transistor;
SL1, SL2, SL3～source electrode line;
WL1, WL2, WL3, WL4～word line;
N+～source/drain electrode;
20～interface layer.
Embodiment
Fig. 2 A is depicted as the schematic diagram according to the multidigit phase-change memory array of one embodiment of the invention, this multidigit phase-change memory array comprises a plurality of multidigit Ovonics unified memories, each multidigit Ovonics unified memory comprises one first bit line (BL1, BL2, BL3) with one second bit line (BL1 ', BL2 ', BL3 '), one first phase-change material layer GST1, one second a phase-change material layer GST2 and a switch element TN, for example, this switch element is a metal oxide semiconductor transistor, this first phase-change material layer GST1 is coupled to this first bit line (BL1, BL2, BL3) with this second bit line (BL1 ', BL2 ', BL3 ') between, this second phase-change material layer GST2 is coupled to one source pole line (SL1, SL2, SL3), this metal oxide semiconductor transistor TN is coupled between this first phase-change material layer GST1 and this second phase-change material layer GST2 by its source/drain electrode, and its grid is coupled to a word line (WL1, WL2, WL3, WL4), wherein, this first phase-change material layer GST1 has different decrystallized attitude resistance values with this second phase-change material layer GST2, and different decrystallized attitude electric currents.This second bit line (BL1 ', BL2 ', BL3 ') can be coupled between this first phase-change material layer GST1 and this metal oxide semiconductor transistor TN.
Fig. 2 B is the structural section figure according to the multidigit Ovonics unified memory shown in Fig. 2 A, this multidigit Ovonics unified memory comprises one first bit line BL1 and one second bit line BL1 ', one first phase-change material layer GST1, one second a phase-change material layer GST2 and a metal oxide semiconductor transistor TN, this first phase-change material layer GST1 is coupled between this first bit line BL1 and this second bit line BL1 ', this second phase-change material layer GST2 is coupled to one source pole line SL1, this metal oxide semiconductor transistor TN is coupled between this first phase-change material layer GST1 and this second phase-change material layer GST2 by its source/drain electrode N+, and its grid is controlled by a word line, wherein, this first phase-change material layer GST1 has different decrystallized attitude resistance values with this second phase-change material layer GST2, and different decrystallized attitude electric currents.This second bit line BL1 ' can be coupled between this first phase-change material layer GST1 and this metal oxide semiconductor transistor TN.
Shown in Fig. 2 B, the layout area A2 of this second phase-change material layer GST2 is greater than the layout area A1 of this first phase-change material layer GST1, therefore make the decrystallized attitude electric current I reset1 of this first phase-change material layer GST1 less than the decrystallized attitude electric current I reset2 of this second phase-change material layer GST2, the decrystallized attitude resistance value Rreset1 of this first phase-change material layer GST1 is greater than the decrystallized attitude resistance value Rreset2 of this second phase-change material layer GST2 simultaneously, when this multidigit Ovonics unified memory is programmed (program), for example be to apply electric current and metal oxide semiconductor transistor is opened in bit line, and apply an electric current in this first bit line BL1 or this second bit line BL1 ' by this grid; If apply an electric current I, and Iset2＜I in this first bit line BL1, can flow through this first phase-change material layer GST1 and this second phase-change material layer GST2 of electric current I then, wherein, Iset2 is the crystallization attitude electric current of GST2.Reach degree owing to apply electric current I with this second phase-change material layer GST2 crystallization, therefore this first phase-change material layer GST1 and this second phase-change material layer GST2 can be by crystallizations, and then the equivalent resistance of current path equals the conduction resistance value R of metal oxide semiconductor transistor
0If apply an electric current I in this first bit line BL1, and Ireset1＜I＜Ireset2, can flow through this first phase-change material layer GST1 and this second phase-change material layer GST2 of electric current I then, but do not reach decrystallized degree with this second phase-change material layer GST2 owing to apply electric current I, therefore have only this first phase-change material layer GST1 by decrystallized, then the equivalent resistance of current path equals the decrystallized resistance value R of this first phase-change material layer GST1
Reset1If apply an electric current I in this first bit line BL1, and Ireset2＜I, wherein Ireset2 is the decrystallized attitude electric current of GST2, can flow through this first phase-change material layer GST1 and this second phase-change material layer GST2 of electric current I then, because applying electric current I has reached the decrystallized degree with this second phase-change material layer GST2, therefore this first phase-change material layer GST1 and this second phase-change material layer GST2 can be by decrystallized, and then the equivalent resistance of current path equals the decrystallized resistance value R of this first phase-change material layer GST1
Reset1Add the decrystallized resistance value R of the second phase-change material layer GST2
Reset2If apply an electric current I in this second bit line BL1 ', and Ireset2＜I, electric current I this second phase-change material layer GST2 that only can flow through then, because applying electric current I has reached the decrystallized degree with this second phase-change material layer GST2, therefore have only this second phase-change material layer GST2 can be by decrystallized, then the equivalent resistance of current path equals the decrystallized resistance value R of this second phase-change material layer GST2
Reset2, by different programming (program) mode, the equivalent resistance of current path can be distinguished four grades, therefore can make single Ovonics unified memory just can obtain 2 storage capacity.
Except making the layout area of this first phase-change material layer GST1 and this second phase-change material layer GST2, utilization produces differentiation, so that this first phase-change material layer GST1 has different decrystallized attitude resistance values with this second phase-change material layer GST2, and different decrystallized attitude electric current, also can utilize the thickness that makes this first phase-change material layer GST1 and this second phase-change material layer GST2 to produce differentiation, to reach identical effect, shown in Fig. 2 C, the thickness H2 of this second phase-change material layer GST2 for thin, therefore still makes the decrystallized attitude electric current I reset1 of this first phase-change material layer GST1 less than the decrystallized attitude electric current I reset2 of this second phase-change material layer GST2 than the thickness H1 of this first phase-change material layer GST1.
In addition, also can utilize the interface layer (interracial layer) that makes this first phase-change material layer GST1 and this second phase-change material layer GST2 to produce differentiation, to reach identical effect, shown in Fig. 2 D, this second phase-change material layer GST2 does not have interface layer, and this first phase-change material layer GST1 has interface layer 20, therefore still make the decrystallized attitude electric current I reset1 of this first phase-change material layer GST1 less than the decrystallized attitude electric current I reset2 of this second phase-change material layer GST2, moreover, also can utilize the heated contact surface area that makes this first phase-change material layer GST1 and this second phase-change material layer GST2 to produce differentiation, to reach identical effect, shown in Fig. 2 E, perforation (via) area under this second phase-change material layer GST2 wants big than perforation (via) area under this first phase-change material layer GST1, therefore still make the decrystallized attitude electric current I reset1 of this first phase-change material layer GST1 less than the decrystallized attitude electric current I reset2 of this second phase-change material layer GST2, except above-mentioned variety of way, also can utilize the doping content that makes this first phase-change material layer GST1 and this second phase-change material layer GST2 to produce differentiation or other modes, to reach identical effect.Be noted that the foregoing description is that example is done explanation with two phase-change material layer GST1, GST2, yet the present invention is not as limit.The number of the phase-change material layer that multidigit Ovonics unified memory of the present invention is comprised can design according to actual demand, and this should be general ripe this skill person can understand, and does not repeat them here.
The invention provides a kind of structural design of multidigit Ovonics unified memory.On drain electrode, source electrode serial connection, for example be the phase-transition material of different area respectively, to reach the current path of different change in resistance; Utilize the phase change of drain electrode, the different resistance phase-transition materials in source electrode two ends to cooperate, can clearly obtain multistage different change in resistance, multistage thus change in resistance can be reached the single memory memory of multidigit memory.The multidigit single memory Ovonics unified memory manufacturing process that the application carried is identical with traditional Ovonics unified memory, in other words, needn't increase under photomask, manufacturing step, the cost, can obtain the purpose of memory capacity multiplication.
Though the present invention discloses as above with embodiment; right its is not in order to limiting the present invention, anyly has the knack of this skill person, without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention is as the criterion when looking appended the claim person of defining.
Claims (16)
1. multidigit phase-change memory array comprises:
A plurality of multidigit Ovonics unified memories, each multidigit Ovonics unified memory comprises:
First bit line and second bit line;
First phase-change material layer is coupled between this first bit line and this second bit line;
Second phase-change material layer is coupled to source electrode line; And
Switch element is coupled between this first phase-change material layer and this second phase-change material layer by its source/drain electrode, and its grid is coupled to word line, and wherein this second bit line is coupled between this first phase-change material layer and this switch element;
Wherein, this first phase-change material layer has different decrystallized attitude resistance values with this second phase-change material layer, and different decrystallized attitude electric currents,
Wherein, the decrystallized of this first phase-change material layer controlled by this first bit line, and this second phase-change material layer is decrystallized by this first bit line or the control of this second bit line.
2. multidigit phase-change memory array as claimed in claim 1, wherein, the decrystallized attitude electric current of this first phase-change material layer is less than the decrystallized attitude electric current of this second phase-change material layer.
3. multidigit phase-change memory array as claimed in claim 1, wherein, this first phase-change material layer is different with the layout area of this second phase-change material layer.
4. multidigit phase-change memory array as claimed in claim 1, wherein, this first phase-change material layer is different with the thickness of this second phase-change material layer.
5. multidigit phase-change memory array as claimed in claim 1, wherein, this first phase-change material layer is different with the doping content of this second phase-change material layer.
6. multidigit phase-change memory array as claimed in claim 1, wherein, one of this first phase-change material layer and this second phase-change material layer comprise interface layer.
7. multidigit phase-change memory array as claimed in claim 1, wherein, this first phase-change material layer is different with the heated contact surface area of this second phase-change material layer.
8. multidigit phase-change memory array as claimed in claim 1, wherein, this switch element is a metal oxide semiconductor transistor.
9. multidigit Ovonics unified memory comprises:
First bit line and second bit line;
First phase-change material layer is coupled between this first bit line and this second bit line;
Second phase-change material layer is coupled to source electrode line; And
Switch element is coupled between this first phase-change material layer and this second phase-change material layer by its source/drain electrode, and its grid is coupled to word line, and wherein this second bit line is coupled between this first phase-change material layer and this switch element;
Wherein, this first phase-change material layer has different decrystallized attitude resistance values with this second phase-change material layer, and different decrystallized attitude electric currents,
Wherein, the decrystallized of this first phase-change material layer controlled by this first bit line, and this second phase-change material layer is decrystallized by this first bit line or the control of this second bit line.
10. multidigit Ovonics unified memory as claimed in claim 9, wherein, the decrystallized attitude electric current of this first phase-change material layer is less than the decrystallized attitude electric current of this second phase-change material layer.
11. multidigit Ovonics unified memory as claimed in claim 9, wherein, this first phase-change material layer is different with the layout area of this second phase-change material layer.
12. multidigit Ovonics unified memory as claimed in claim 9, wherein, this first phase-change material layer is different with the thickness of this second phase-change material layer.
13. multidigit Ovonics unified memory as claimed in claim 9, wherein, this first phase-change material layer is different with the doping content of this second phase-change material layer.
14. multidigit Ovonics unified memory as claimed in claim 9, wherein, one of this first phase-change material layer and this second phase-change material layer comprise interface layer.
15. multidigit Ovonics unified memory as claimed in claim 9, wherein, this first phase-change material layer is different with the heated contact surface area of this second phase-change material layer.
16. multidigit Ovonics unified memory as claimed in claim 9, wherein, this switch element is a metal oxide semiconductor transistor.
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| CN1805167A (en) * | 2005-01-10 | 2006-07-19 | 旺宏电子股份有限公司 | Phase change type multi-digit quasi-memory cell and its operating method |
| CN1996492A (en) * | 2006-01-05 | 2007-07-11 | 三星电子株式会社 | Phase change memory devices multi-bit operating methods |
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| CN1805167A (en) * | 2005-01-10 | 2006-07-19 | 旺宏电子股份有限公司 | Phase change type multi-digit quasi-memory cell and its operating method |
| CN1996492A (en) * | 2006-01-05 | 2007-07-11 | 三星电子株式会社 | Phase change memory devices multi-bit operating methods |
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