CN101359505B - Read isolation programmable memory unit and programming and reading method thereof - Google Patents
Read isolation programmable memory unit and programming and reading method thereof Download PDFInfo
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- CN101359505B CN101359505B CN2008101193082A CN200810119308A CN101359505B CN 101359505 B CN101359505 B CN 101359505B CN 2008101193082 A CN2008101193082 A CN 2008101193082A CN 200810119308 A CN200810119308 A CN 200810119308A CN 101359505 B CN101359505 B CN 101359505B
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Abstract
The invention discloses a read-isolated programmable memory unit and a programming and read method. The read-isolated programmable memory unit comprises a first transistor which consists of a first source electrode, a first drain electrode, a first grid and a first well voltage terminal, a second transistor which consists of a second ion injection area, a second grid and a second well voltage terminal, and a third transistor which consists of a third source electrode, a third drain electrode and a third grid. The first grid of the first transistor is connected with a word line; the drain electrode of the first transistor is connected with the second ion injection area of the second transistor; and the first source electrode of the first transistor is connected with a programming bit line. The second grid of the second transistor is connected with a source line; the third grid of the third transistor is connected with a read bit line; and the first well voltage terminal of the first transistor is connected with the second well voltage terminal of the second transistor. The invention can prevent the high voltage on the programming line from puncturing the transistors connected with the read bit line during the data programming process, thus improving the programming reliability of the programmable memory.
Description
Technical field
The present invention relates generally to semiconductor technology, relates in particular to a kind of isolation programmable memory unit and programming and read method read.
Background technology
In design process, usually need integrated a large amount of non-volatile memory cells based on the SOC (system on a chip) (SOC, System On Chip) of logic process.The SOC of different purposes may need the non-volatile memory cells of difference in functionality, comprises read-only memory unit, read-only memory unit able to programme, programmable and erasable read-only memory unit etc.Compare with read-only memory unit, programmable non-volatile memory cell has greatly increased SOC deviser's degree of freedom.The deviser can be according to different application needs, information is cured in the chip by programming goes, and need not redesign chip, and in this case, but the storage unit that designing institute adopts does not need erase feature.
Because therefore the data programing and the shared bi-directional data IO channel of read operation of existing programmable storage, cause the influence of the data read process of programmable storage easily in the operating process of programmable storage being carried out data programing.
Summary of the invention
In view of this, the object of the present invention is to provide a kind of isolation programmable memory unit and programming and read method read, reach the transistor that high voltage will be connected with reading bit line on the programming bit line when preventing data programing and puncture, improve the purpose of programmable storage data programing and reliability of reading.
According to the one side of the embodiment of the invention, a kind of isolation programmable memory unit of reading is provided, comprising:
The first transistor comprises first source electrode, first drain electrode, first grid and the first trap voltage end;
Transistor seconds comprises second ion implanted region, second grid and the second trap voltage end;
The 3rd transistor comprises the 3rd source electrode, the 3rd drain electrode and the 3rd grid;
The first grid of the first transistor is connected with word line;
First drain electrode of the first transistor is connected with second ion implanted region of transistor seconds;
First source electrode of the first transistor is connected with the programming bit line;
The second grid of transistor seconds is connected with the source line;
The 3rd transistorized the 3rd drain electrode is connected with reading bit line; The first trap voltage end of the first transistor is connected with the second trap voltage end of transistor seconds; The 3rd transistorized the 3rd source electrode is connected with the programming bit line.
According to a feature of the embodiment of the invention, described the first transistor is for selecting transistor.
According to another feature of the embodiment of the invention, described the first transistor comprises thick grid oxide layer.
According to another feature of the embodiment of the invention, described transistor seconds is the data storage transistor.
According to another feature of the embodiment of the invention, described transistor seconds comprises thin grid oxide layer.
According to another feature of the embodiment of the invention, described transistor seconds is half transistor.
According to another feature of the embodiment of the invention, described first, second transistor is a P type MOS transistor.
According to the embodiment of the invention on the other hand, provide a kind of programmed method of reading the isolation programmable storage unit, wherein, first, second, third transistor is a P type MOS transistor, and this programmed method comprises:
On first source electrode of the first transistor, apply first voltage;
On the first trap voltage end of the first transistor, apply first voltage;
On the first grid of the first transistor, apply second voltage;
On the second grid of transistor seconds, apply tertiary voltage;
On the second trap voltage end of transistor seconds, apply first voltage;
The first transistor conducting, make voltage on second ion implanted region of transistor seconds equal to be applied to first voltage on the first transistor source electrode, voltage forms voltage breakdown between the second grid, second ion implanted region of transistor seconds thereby make, this voltage breakdown punctures the grid oxide layer of transistor seconds in the given time, finishes programming operation;
Wherein, the voltage on the described the 3rd transistorized the 3rd source electrode is first voltage, applies first voltage on the described the 3rd transistorized the 3rd grid, makes the 3rd transistor be in closed condition.
According to a feature of the embodiment of the invention, described puncture comprises hard breakdown and soft breakdown, wherein,
Described hard breakdown is with the complete disposable puncture of grid oxide layer;
Described soft breakdown is the process puncture, and the puncture speed of soft breakdown and the thickness of grid oxide layer are inversely proportional to, and is directly proportional with the size of voltage breakdown.
According to another feature of the embodiment of the invention, described first voltage is to be the voltage of twice second voltage at least greater than size; Described second voltage is 1 voltage for the sign level value; Described tertiary voltage is 0 voltage for the sign level value.
According to another feature of the embodiment of the invention, described voltage breakdown is to be the voltage of twice second voltage at least greater than size.
According to the embodiment of the invention on the other hand, provide a kind of read method of reading the isolation programmable storage unit, wherein, first, second, third transistor is a P type MOS transistor, and this read method comprises:
On first source electrode of the first transistor, apply second voltage;
On the first trap voltage end of the first transistor, apply second voltage;
On the first grid of the first transistor, apply tertiary voltage;
On the second grid of transistor seconds, apply tertiary voltage;
On the second trap voltage end of transistor seconds, apply second voltage;
The first transistor conducting, make voltage on second ion implanted region of transistor seconds equal second voltage on the first transistor first source electrode, voltage is the difference voltage of the tertiary voltage and second voltage between the second grid, second ion implanted region of transistor seconds thereby make;
If the grid oxide layer of transistor seconds is not breakdown, then the transistor seconds equivalence is an electric capacity, and the voltage on the reading bit line is retained as second voltage, and making the data that read is that logical value is 1;
If transistor seconds grid oxide layer breakdown, then the transistor seconds equivalence is a resistance, the voltage on the reading bit line is pulled down to the threshold voltage of the first transistor, making the data that read is logical value 0.
According to a feature of the embodiment of the invention, described second voltage is 1 voltage for the sign level value; Described tertiary voltage is 0 voltage for the sign level value.
According to the embodiment of the invention on the other hand, provide a kind of programmed method of reading the isolation programmable storage unit, wherein, first, second, third transistor is a N type MOS transistor, and this programmed method comprises:
In first drain electrode of the first transistor, apply first voltage;
On the first grid of the first transistor, apply first voltage;
On the first trap voltage end of the first transistor, apply tertiary voltage;
Voltage on first source electrode of the first transistor is the voltage that is less than or equal to second voltage;
On the second grid of transistor seconds, apply tertiary voltage;
On the second trap voltage end of transistor seconds, apply tertiary voltage;
The first transistor conducting, make voltage on second ion implanted region of transistor seconds equal to be applied to first voltage on the first transistor source electrode, voltage forms voltage breakdown between the second grid, second ion implanted region of transistor seconds thereby make, this voltage breakdown punctures the grid oxide layer of transistor seconds in the given time, finishes programming operation;
Wherein, the voltage on the described the 3rd transistorized the 3rd source electrode is first voltage, applies second voltage on the described the 3rd transistorized the 3rd grid, makes the 3rd transistor be in closed condition.
According to a feature of the embodiment of the invention, described puncture comprises hard breakdown and soft breakdown, wherein,
Described hard breakdown is with the complete disposable puncture of grid oxide layer;
Described soft breakdown is the process puncture, and the puncture speed of soft breakdown and the thickness of grid oxide layer are inversely proportional to, and is directly proportional with the size of voltage breakdown.
According to another feature of the embodiment of the invention, described first voltage is to be the voltage of twice second voltage at least greater than size; Described second voltage is 1 voltage for the sign level value; Described tertiary voltage is 0 voltage for the sign level value.
According to another feature of the embodiment of the invention, described voltage breakdown is to be the voltage of twice second voltage at least greater than size.
According to the embodiment of the invention on the other hand, provide a kind of read method of reading the isolation programmable storage unit, wherein, first, second, third transistor is a N type MOS transistor, and this read method comprises:
On first source electrode of the first transistor, apply first voltage;
On the first grid of the first transistor, apply second voltage;
On the first trap voltage end of the first transistor, apply tertiary voltage;
Voltage on first source electrode of the first transistor is the voltage that is less than or equal to second voltage;
On the second grid of transistor seconds, apply tertiary voltage;
On the second trap voltage end of transistor seconds, apply tertiary voltage;
The first transistor conducting, make voltage on second ion implanted region of transistor seconds equal first voltage on the first transistor first source electrode, make that voltage is the difference voltage of the tertiary voltage and first voltage between the second grid, second ion implanted region of transistor seconds;
If the grid oxide layer of transistor seconds is not breakdown, then the transistor seconds equivalence is an electric capacity, and the voltage on the reading bit line is retained as second voltage, and making the data that read is that logical value is 1;
If transistor seconds grid oxide layer breakdown, then the transistor seconds equivalence is a resistance, the voltage on the reading bit line is pulled down to the threshold voltage of the first transistor, making the data that read is logical value 0.
According to a feature of the embodiment of the invention, described first voltage is to be the voltage of twice second voltage at least greater than size; Described second voltage is 1 voltage for the sign level value; Described tertiary voltage is 0 voltage for the sign level value.
A kind of isolation programmable memory unit and programming and read method read of the present invention, by between programming bit line and reading bit line, designing the transistor arrangement with isolation features that the two can be separated, the transistor that high voltage will be connected with reading bit line on the programming bit line when avoiding data programing punctures, thereby the influence that the high voltage that produces when preventing the data programing operation effectively causes the data read operation, improved the reliability of programming of disposable programmable memory, because forming greater than size is the voltage breakdown of twice operating voltage at least and the characteristics design data storage transistor that the thin grid oxide layer of utilization punctures easily, thereby improve the program speed of disposable programmable memory greatly.In addition, a kind of isolation programmable memory unit and programming and read method read of the present invention under the precondition that does not influence storer external circuit structure, is the high voltage of twice operating voltage at least by charge pump output size.In addition, one-time programmable memory cell of the present invention adopts standard logic process to make down, and the programming operation by logic control realization memory cell array does not need extra fuse programming equipment, has simplified design, has reduced cost.
Description of drawings
Fig. 1 is the structured flowchart of disposable programmable memory circuit in the specific embodiment of the invention;
Fig. 2 selects the synoptic diagram of an example of module for programming in the disposable programmable memory circuit in the description specific embodiment of the invention;
Fig. 3 is for describing the synoptic diagram that reads an example selecting module in the specific embodiment of the invention in the disposable programmable memory circuit;
Fig. 4 a for one-time programmable memory cell in the present invention's first specific embodiment with have the structural representation that the transistor of reading isolation features is connected;
Fig. 4 b for one-time programmable memory cell in the present invention's second specific embodiment with have the structural representation that the transistor of reading isolation features is connected;
Fig. 5 is the synoptic diagram of one-time programmable memory cell in the present invention's first specific embodiment;
Fig. 6 is the first local structural representation of disposable programmable non-volatile memory array in the first embodiment of the invention;
Fig. 7 is the first local canonical schema of disposable programmable non-volatile memory array in the first embodiment of the invention;
Fig. 8 is the vertical view of first part of disposable programmable non-volatile memory array in the first embodiment of the invention;
Fig. 9 is the synoptic diagram of one-time programmable memory cell in the present invention's second specific embodiment;
Figure 10 is the first local structural representation of disposable programmable non-volatile memory array in the second embodiment of the invention;
Figure 11 is the first local canonical schema of disposable programmable non-volatile memory array in the second embodiment of the invention;
Figure 12 is the vertical view of first part of disposable programmable non-volatile memory array in the second embodiment of the invention.
Embodiment
Describe specific embodiments of the invention in detail below in conjunction with accompanying drawing.
Fig. 1 is the structured flowchart of disposable programmable memory circuit in the specific embodiment of the invention, comprises memory cell array 101, charge pump 102, programming bit line decoding module 103, programming selection module 104, word line decoding module 105 among the figure, reads isolation module 106, reading bit line decoding module 107 and read selection module 108.Wherein,
Programming bit line decoding module 103 is used for determining that memory cell array 101 needs to carry out the programming bit line address of the storage unit of data programing.
Word line decoding module 105 is used for the word line that select storage unit array 101 needs to carry out the storage unit of data programing or data read.Each storage unit in the memory cell array 101 all has a word line corresponding with it.In the process of data programing operation, storage unit for P type MOS transistor, the predetermined voltage that word line decoding module 105 provides charge pump is sent to not to be needed on the word line of the selecteed storage unit WL, word line to the selecteed storage unit of needs then applies operating voltage in addition, is the operating voltage of 3V as size; Storage unit for N type MOS transistor, the predetermined voltage that word line decoding module 105 provides charge pump is sent on the word line that needs selecteed storage unit, the word line WL that does not need selecteed storage unit is then applied operating voltage in addition, is the operating voltage of 3V as size.
Read isolation module 106, be arranged at memory cell array 101 and read and select between the module 108, be used for data programing and data read are isolated, thus the influence that the high voltage that produces when preventing the data programing operation causes the data read operation.
Sense bit line decoding module 107 is used for determining that memory cell array 101 needs to carry out the reading bit line address of the storage unit of data read.
Read and select module 108, be used for the reading bit line address selection storage unit corresponding of the storage unit determined according to sense bit line decoding module 107, read the data that are stored in the storage unit with this storage unit bit line.
Fig. 2 selects the synoptic diagram of an example of module for programming in the disposable programmable memory circuit in the description specific embodiment of the invention;
Programming selects module 104 to comprise N type MOS transistor N1, N2, N3, wherein, the grid G 1 of N type MOS transistor N1, N2, N3, G2, G3 receive the programming bit line address that programming bit line decoding module 103 is determined among Fig. 1, the drain D 1 of N type MOS transistor N1, N2, N3, D2, D3 receive high voltage Vpp, and the source S 1 of N type MOS transistor N1, N2, N3, S2, S3 are connected with programming bit line W_BL1, W_BL2, W_BL3 respectively.By the conducting of programming bit line address control N type MOS transistor N1, N2, N3, thus selected corresponding programming bit line.
For convenience of the reader understanding, above-mentioned example has only been described the programming that comprises three N type MOS transistor and has been selected module 104, but do not mean that or not can only be the structure that comprises three N type MOS transistor that module 104 is selected in programming, programming selects module 104 can comprise the combination of a plurality of N type MOS transistor or P type MOS transistor and a plurality of N type MOS transistor and P type MOS transistor, as the many o controllers of single input, its purpose all is in order to realize the programming bit line of the storage unit in the select storage unit array 101, for data programing is prepared.
Fig. 3 is for describing the synoptic diagram that reads an example selecting module in the specific embodiment of the invention in the disposable programmable memory circuit;
Read and select module 108 to comprise N type MOS transistor N4, N5, N6, wherein, the grid G 4 of N type MOS transistor N4, N5, N6, G5, G6 receive the reading bit line address that reading bit line decoding module 107 is determined among Fig. 1, N type MOS transistor N4, the source S 1 of N5, N6, S2, S3 are connected with reading bit line R_BL1, R_BL2, R_BL3 respectively, and the drain D 4 of N type MOS transistor N4, N5, N6, D5, D6 will export from the data that reading bit line R_BL1, R_BL2, R_BL3 read as data output end.By the conducting of reading bit line address control N type MOS transistor N4, N5, N6, thus selected corresponding reading bit line.
For convenience of the reader understanding, above-mentioned example has only been described and has been comprised that reading of three N type MOS transistor select module 107, but do not mean that reading selection module 107 can only be the structure that comprises three N type MOS transistor, read and select module 107 can comprise the combination of a plurality of N type MOS transistor or P type MOS transistor and a plurality of N type MOS transistor and P type MOS transistor, as multiselect one logic controller, its purpose all is in order to realize the reading bit line of the storage unit in the select storage unit array 101, for data read is prepared.
Fig. 4 a for one-time programmable memory cell in the present invention's first specific embodiment with have the structural representation that the transistor of reading isolation features is connected, comprise P type MOS transistor P41 among Fig. 4, P42 and P type MOS transistor P43, wherein, the grid of P type MOS transistor P41 is connected with word line WL, the drain electrode of P type MOS transistor P41 is connected with the ion implanted region of P type MOS transistor P42, the source electrode of P type MOS transistor P41 is connected with bit line BL, the trap voltage end of P type MOS transistor P41 is connected with the trap voltage end of P type MOS transistor P42, the grid of P type MOS transistor P42 is connected with source line SL, the drain electrode of P type MOS transistor P43 is connected with bit line BL, as first kind of embodiment reading isolation module 106, P type MOS transistor P43 is used for preventing that the transistor of selecting module 108 that reads that the high voltage of data programing process will be connected with reading bit line R_BL from puncturing, thereby can not influence the data read process to one-time programmable memory cell.The specific embodiment of the invention directly is connected the bit line BL of storage unit with programming bit line W_BL, and be connected indirectly with reading bit line R_BL by P type MOS transistor P43, use programming bit line W_BL to carry out the data programing operation, use reading bit line R_BL to carry out data read operation.Data programing and read operation process to one-time programmable memory cell is described respectively below:
The data programing operating process
Select transistorized P type MOS transistor P41 for conduct, with source electrode that programming bit line W_BL is connected on and to apply size on the trap voltage end Vwell be the high voltage Vpp of twice operating voltage at least, as size is the high voltage of 6V, high voltage Vpp is provided by charge pump 102, select module 104 to send programming bit line W_BL to by programming, with grid that word line WL is connected on apply size for 3V sign level value is 1 operating voltage Vcc, make P type MOS transistor P41 conducting.
And for half P type MOS transistor P42 as data storage cell, with grid that source line SL is connected on apply that to characterize level value be 0 voltage Vss, as size be-voltage of 2V; On trap voltage end Vwell, apply high voltage Vpp; Because P type MOS transistor P41 conducting, therefore, the voltage of the ion implanted region of half P type MOS transistor P42 equals the high voltage Vpp on the P type MOS transistor P41, thereby makes voltage Vgs between the grid, ion implanted region of half P type MOS transistor P42
2Formation is more than or equal to the voltage breakdown of Vpp, and this voltage breakdown punctures the thin grid oxide layer of half P type MOS transistor P42 in the given time fully, finishes the one-off programming operation.
The programming operation of memory cell array 105 comprises hard breakdown and soft breakdown.Hard breakdown is that grid oxide layer is punctured fully, soft breakdown is to add the incomplete breakdown that predetermined voltage is realized on grid, wherein, soft breakdown is the process puncture, puncture speed in the soft breakdown is by the thickness of grid oxide layer and the voltage swing decision that is applied, be inversely proportional to the thickness of grid oxide layer, be directly proportional with the size of voltage breakdown.
Under the 0.13um logic process, thickness is about the about 3V-6V of voltage breakdown of the thin grid oxide layer of 2nm, therefore this specific embodiment has accelerated the speed of programming operation owing to form high voltage greater than 6V at the source electrode of the transistor P42 that is used to store data and grid.In addition, add negative voltage turn-on transistor P41, thereby make source voltage reach the high voltage of 6V by grid at data storage cell, and then the hard breakdown better effects if when making programming operation.
The data read operation process
Select transistorized P type MOS transistor P41 for conduct, on the source electrode of P type MOS transistor P41 and trap voltage end Vwell, apply operating voltage Vcc, as size is the operating voltage of 3V, with grid that word line WL is connected on apply that to characterize level value be 0 voltage, make P type MOS transistor P41 conducting.
And for half P type MOS transistor P42 as data storage cell, with grid that source line SL is connected on apply that to characterize level value be 0 voltage Vss, as size be-voltage of 2V; Applying operating voltage Vcc on trap voltage end Vwell, is the operating voltage of 3V as size; Because P type MOS transistor P41 conducting, therefore, voltage on the ion implanted region of P type MOS transistor P42 equals the operating voltage Vcc on the P type MOS transistor P41 source electrode, and voltage is the difference voltage of voltage Vss and operating voltage Vcc between the grid, ion implanted region of half P type MOS transistor P42 thereby make.Therefore, if the grid oxide layer of half P type MOS transistor P42 is not breakdown, then half P type MOS transistor P42 equivalence is an electric capacity, and the voltage on the reading bit line R_BL remains operating voltage Vcc, and making the data that read is that logical value is " 1 "; Otherwise if the grid oxide layer of half P type MOS transistor P42 is breakdown, then P type MOS transistor P42 equivalence is a resistance, and the voltage on the bit line BL is pulled down to the threshold voltage vt h of P41, and making the data that read is logical value " 0 ".
Among Fig. 4 a, high voltage when making programming operation on the bit line BL can not be transferred to reading bit line R_BL and cause the transistor that will be connected with reading bit line R_BL to puncture, be provided for realizing reading the P type MOS transistor P43 of isolation features at the data read outgoing position, to improve the reliability of disposable programmable memory.
The job step of P type MOS transistor P43 is as described below:
When storage unit being carried out the data programing operation, because with the voltage on the programming bit line W_BL that the source electrode of P type MOS transistor P43 is connected is high voltage Vpp, as size is the high voltage of 6V, grid at P type MOS transistor P43 also applies high voltage Vpp, makes P type MOS transistor P43 be in closed condition.
When storage unit is carried out data read operation, on the grid of P type MOS transistor P43, apply size and be the operating voltage of 0V, reading bit line R_BL is precharged to operating voltage Vcc.When storage unit is carried out read operation, if the grid oxide layer of half P type MOS transistor P42 is not breakdown, then half P type MOS transistor P42 equivalence is an electric capacity, and the voltage on the reading bit line R_BL is retained as operating voltage Vcc, and making the data that read is that logical value is " 1 "; Otherwise if the grid oxide layer of half P type MOS transistor P42 is breakdown, then half P type MOS transistor P42 equivalence is a resistance, and the voltage on the reading bit line R_BL is pulled down to the threshold voltage vt h of P type MOS transistor P41, and making the data that read is logical value " 0 ".
Fig. 4 b for one-time programmable memory cell in the present invention's second specific embodiment with have the structural representation that the transistor of reading isolation features is connected, comprise N type MOS transistor N41 among Fig. 4 b, N42 and N type MOS transistor N43, wherein, the grid of N type MOS transistor N41 is connected with word line WL, the source electrode of N type MOS transistor N41 is connected with the ion implanted region of N type MOS transistor N42, the drain electrode of N type MOS transistor N41 is connected with bit line BL, the trap voltage end of N type MOS transistor N41 is connected with the trap voltage end of N type MOS transistor N42, the grid of N type MOS transistor N42 is connected with source line SL, the drain electrode of N type MOS transistor N43 is connected with bit line BL, as first kind of embodiment reading isolation module 106, make the high voltage of data programing process the transistor that is connected with reading bit line R_BL can not punctured, thereby can not influence data read process one-time programmable memory cell.The specific embodiment of the invention directly is connected the bit line BL of storage unit with programming bit line W_BL, and be connected indirectly with reading bit line R_BL by N type MOS transistor N43, use programming bit line W_BL to carry out the data programing operation, use reading bit line R_BL to carry out data read operation.Data programing and read operation process to one-time programmable memory cell is described respectively below:
The data programing operating process
Select transistorized N type MOS transistor N41 for conduct, the grid that is connected with word line WL with drain electrode that programming bit line W_BL is connected on to apply size be the high voltage Vpp of twice operating voltage at least, as size is the high voltage of 6V, high voltage Vpp is provided by charge pump 102, select module 104 to send programming bit line W_BL to by programming, on trap voltage end Vwell, apply size and be the voltage of 0V, the source voltage of N type MOS transistor N41 is the voltage that is less than or equal to 3V, makes N type MOS transistor N41 conducting.
And for half N type MOS transistor N42 as data storage cell, with grid that source line SL is connected on apply that to characterize level value be 0 voltage Vss, as size be-voltage of 2V; On trap voltage end Vwell, apply size and be the voltage of 0V; Because N type MOS transistor N41 conducting, therefore, the voltage of the ion implanted region of half N type MOS transistor N42 equals the high voltage Vpp on the N type MOS transistor N41, thereby makes voltage Vgs between the grid, ion implanted region of half N type MOS transistor N42
2Formation is more than or equal to the voltage breakdown of Vpp, and this voltage breakdown punctures the thin grid oxide layer of half N type MOS transistor N42 in the given time fully, finishes the disposable operation of weaving into.
The programming operation of memory cell array 105 comprises hard breakdown and soft breakdown.Hard breakdown is that grid oxide layer is punctured fully, soft breakdown is to add the incomplete breakdown that predetermined voltage is realized on grid, wherein, soft breakdown is the process puncture, puncture speed in the soft breakdown is by the thickness of grid oxide layer and the voltage swing decision that is applied, be inversely proportional to the thickness of grid oxide layer, be directly proportional with the size of voltage breakdown.
Under the 0.13um logic process, the about 3V-6V of voltage breakdown that thickness is about the thin grid oxide layer of 2nm, therefore this specific embodiment has accelerated the speed of programming operation owing to form high voltage greater than 6V at the ion implanted region of the transistor N42 that is used to store data and grid.In addition, add negative voltage by grid and open N41, thereby make source voltage reach the high voltage of 6V at data storage cell, and then the hard breakdown better effects if when making programming operation.
The data read operation process
For as selecting transistorized N type MOS transistor N41, apply operating voltage Vcc in the drain electrode of the N type MOS transistor N41 that is connected with bit line BL, as size the operating voltage of 3V; With grid that word line WL is connected on apply operating voltage Vcc, be the operating voltage of 3V as size; On trap voltage end Vwell, apply size and be the voltage of 0V, make N type MOS transistor N41 conducting.
And for half N type MOS transistor N42 as data storage cell, with grid that source line SL is connected on apply that to characterize level value be 0 voltage Vss, as size be-voltage of 2V; On trap voltage end Vwell, apply size and be the voltage of 0V; Because N type MOS transistor N41 conducting, therefore, the voltage of the ion implanted region of N type MOS transistor N42 equals the operating voltage Vcc in the N type MOS transistor N41 drain electrode, and voltage is the difference voltage of voltage Vss and operating voltage Vcc between the grid, ion implanted region of half N type MOS transistor N42 thereby make.Therefore, if the grid oxide layer of half N type MOS transistor N42 is not breakdown, then half N type MOS transistor N42 equivalence is an electric capacity, and the voltage on the reading bit line R_BL remains operating voltage Vcc, and making the data that read is that logical value is " 1 "; Otherwise if the grid oxide layer of half N type MOS transistor N42 is breakdown, then N type MOS transistor N42 equivalence is a resistance, and the voltage on the bit line BL is pulled down to the threshold voltage vt h of N41, and making the data that read is logical value " 0 ".
Among Fig. 4 b, high voltage when making programming operation on the bit line BL can not be transferred to reading bit line R_BL and cause the transistor that will be connected with reading bit line R_BL to puncture, be provided for realizing reading the N type MOS transistor N43 of isolation features at the data read outgoing position, to improve the reliability of disposable programmable memory.
The job step of N type MOS transistor N43 is as described below:
When storage unit being carried out data programing when operation,, as size the high voltage of 6V owing to be high voltage Vpp with voltage on the programming bit line W_BL that the drain electrode of N type MOS transistor N43 is connected; And apply operating voltage Vcc at the grid of N type MOS transistor N43, as size is the operating voltage of 3V, with the voltage on the reading bit line R_BL that the source electrode of N type MOS transistor N43 is connected is the voltage that is less than or equal to 3V, makes N type MOS transistor N43 be in closed condition.
When storage unit is carried out data read operation, on the grid of N type MOS transistor N43, apply size and be the operating voltage of 3V, reading bit line R_BL is precharged to operating voltage Vcc, is the operating voltage of 3V as size.When storage unit is carried out read operation, if the grid oxide layer of half N type MOS transistor N42 is not breakdown, then half N type MOS transistor N42 equivalence is an electric capacity, and the voltage on the reading bit line R_BL is retained as operating voltage Vcc, makes that the data that read are that logical value is " 1 "; Otherwise if the grid oxide layer of half N type MOS transistor N42 is breakdown, then half N type MOS transistor N42 equivalence is a resistance, and the voltage on the reading bit line R_BL is pulled down to the threshold voltage vt h of N type MOS transistor N41, and making the data that read is logical value " 0 ".
By above-mentioned analysis as can be known, has the transistor of reading isolation features by on reading bit line R_BL, being provided with, the transistor that high voltage when preventing data programing effectively will be connected with reading bit line R_BL punctures, thereby improves the reliability of disposable programmable memory.
In the foregoing description, one-time programmable memory cell for the composition of the P type MOS transistor among first embodiment, also can be provided for realizing reading the N type MOS transistor of isolation features at the data read outgoing position, and, also can be provided for realizing reading the P type MOS transistor of isolation features at the data read outgoing position for the one-time programmable memory cell that the N type MOS transistor among second embodiment is formed.
Fig. 5 is the synoptic diagram of one-time programmable memory cell in the present invention's first specific embodiment, and the one-time programmable memory cell among Fig. 5 comprises P type MOS transistor P51 and half P type MOS transistor P52.Wherein, the grid of P type MOS transistor P51 is connected with word line WL, the drain electrode of P type MOS transistor P51 is connected with the ion implanted region of half P type MOS transistor P52, and the source electrode of P type MOS transistor P51 is connected with bit line BL, and the grid of half P type MOS transistor P52 is connected with source line SL.
Fig. 6 is the first local structural representation of disposable programmable non-volatile memory array in the first embodiment of the invention, the first 6011, second portion 6012, third part 6013, the 4th part 6014 and the 5th part 6015 that comprise polysilicon layer among the figure, thick grid oxide layer 6021,6022,6024 and 6025, thin grid oxide layer 6023, P type doped region 6031,6032,6033 and 6034, isolation channel 604 and substrate 605.
Wherein,
Polysilicon layer second portion 6012, thick grid oxide layer 6022, P type doped region 6031 and 6032, substrate 605 form P type MOS transistor P61;
Polysilicon layer third part 6013, thin grid oxide layer 6023, P type doped region 6032, substrate 605 form half P type MOS transistor P621;
Polysilicon layer the 4th part 6014, thick grid oxide layer 6024, P type doped region 6033 and 6034, substrate 605 form P type MOS transistor P63;
Polysilicon layer third part 6013, thin grid oxide layer 6023, P type doped region 6033, substrate 605 form half P type MOS transistor P622;
In the present embodiment, with P type MOS transistor P61, P63 as the selection transistor in the storage unit.In the raceway groove of P type MOS transistor P622, increase isolation channel 604, form half P type MOS transistor P621 and half P type MOS transistor P622, with half P type MOS transistor P621, P622 as the data storage transistor in the storage unit.
Fig. 7 is the first local canonical schema of disposable programmable non-volatile memory array in the first embodiment of the invention, comprises four storage unit 701,702,703,704 among Fig. 7, word line WL1, WL2 and source line SL.Wherein, storage unit 701 comprises P type MOS transistor 7011 and half P type MOS transistor 7012, storage unit 702 comprises P type MOS transistor 7021 and half P type MOS transistor 7022, storage unit 703 comprises P type MOS transistor 7031 and half P type MOS transistor 7032, and storage unit 704 comprises P type MOS transistor 7041 and half P type MOS transistor 7042.
The grid of P type MOS transistor 7011,7021 is connected with WL1, and the grid of P type MOS transistor 7031,7041 is connected with WL2.The grid of P type MOS transistor 7012,7022,7032,7042 is connected with SL.
Fig. 8 is the vertical view of first part of disposable programmable non-volatile memory array in the first embodiment of the invention, among Fig. 8, polysilicon 6012 among Fig. 6 forms word line WL1, polysilicon 6013 among Fig. 6 forms source line SL, polysilicon 6014 among Fig. 6 forms word line WL2, P type doped region 6031 among Fig. 6 forms bit line BL1, and the P type doped region 6034 among Fig. 6 forms bit line BL2.
Fig. 9 is the synoptic diagram of one-time programmable memory cell in the present invention's second specific embodiment, and the one-time programmable memory cell among Fig. 9 comprises P type MOS transistor P91, P92.Wherein, the grid of P type MOS transistor P91 is connected with word line WL, and the drain electrode of P type MOS transistor P91 is connected with the source electrode of P type MOS transistor P92, and the source electrode of P type MOS transistor P91 is connected with bit line BL, and the grid of P type MOS transistor P92 is connected with source line SL.
Figure 10 is the first local structural representation of disposable programmable non-volatile memory array in the second embodiment of the invention;
The first 10011, second portion 10012, third part 10013 and the 4th part 10014 that comprise polysilicon layer among the figure, thick grid oxide layer 10021 and 10024, thin grid oxide layer 10022 and 10023, P type doped region 10031,10032,10033,10034,10035 and 10036, isolation channel 1004 and substrate 1005.
Wherein,
Polysilicon layer first 10011, thick grid oxide layer 10021, P type doped region 10031 and 10032 and substrate 1005 form P type MOS transistor P1001;
Polysilicon layer second portion 10012, thin grid oxide layer 10022, P type doped region 10032 and 10033 and substrate 1005 form P type MOS transistor P1002;
Polysilicon layer third part 10013, thin grid oxide layer 10023, P type doped region 10034 and 10035 and substrate 1005 form P type MOS transistor P1003;
Polysilicon layer the 4th part 10014, thick grid oxide layer 10024, P type doped region 10035 and 10036 and substrate 1005 form half P type MOS transistor P1004;
In the present embodiment, with P type MOS transistor P1001, P1004 selection transistor as storage unit, with P type MOS transistor P1002, P1003 data storage transistor as storage unit, there is not shared doped region between transistor P1002, the P1003, and unsettled separately separation.
Figure 11 is the first local canonical schema of disposable programmable non-volatile memory array in the second embodiment of the invention, comprises four storage unit 1101,1102,1103,1104 among Figure 11, word line WL1, WL2 and source line SL1, SL2.Wherein, storage unit 1101 comprises P type MOS transistor 11011 and P type MOS transistor 11012, storage unit 1102 comprises P type MOS transistor 11021 and P type MOS transistor 11022, storage unit 1103 comprises P type MOS transistor 11031 and P type MOS transistor 11032, and storage unit 1104 comprises P type MOS transistor 11041 and P type MOS transistor 11042.
The grid of P type MOS transistor 11011,11021 is connected with WL1, and the grid of P type MOS transistor 11031,11041 is connected with WL2.The grid of P type MOS transistor 11012,11022 is connected with SL1, and the grid of P type MOS transistor 11032,11042 is connected with SL2.
Figure 12 is the vertical view of first part of disposable programmable non-volatile memory array in the second embodiment of the invention, among Figure 12, polysilicon 10011 among Figure 10 forms word line WL1, polysilicon 10012 among Figure 10 forms source line SL1, polysilicon 10013 among Figure 10 forms source line SL2, polysilicon 10014 among Figure 10 forms word line WL2, and the P type doped region 10031 among Figure 10 forms bit line BL1, and the P type doped region 10036 among Figure 10 forms bit line BL2.
The above only is preferred embodiment of the present invention; not in order to restriction the present invention; within the spirit and principles in the present invention all, any modification, the change that the embodiment of the invention is done, make up, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (19)
1. read isolation programmable memory unit for one kind, it is characterized in that, comprising:
The first transistor comprises first source electrode, first drain electrode, first grid and the first trap voltage end;
Transistor seconds comprises second ion implanted region, second grid and the second trap voltage end;
The 3rd transistor comprises the 3rd source electrode, the 3rd drain electrode and the 3rd grid;
The first grid of the first transistor is connected with word line;
First drain electrode of the first transistor is connected with second ion implanted region of transistor seconds;
First source electrode of the first transistor is connected with the programming bit line;
The second grid of transistor seconds is connected with the source line;
The 3rd transistorized the 3rd drain electrode is connected with reading bit line;
The first trap voltage end of the first transistor is connected with the second trap voltage end of transistor seconds;
The 3rd transistorized the 3rd source electrode is connected with the programming bit line.
2. a kind of programmable memory cell according to claim 1 is characterized in that, described the first transistor is for selecting transistor.
3. a kind of programmable memory cell according to claim 1 is characterized in that described the first transistor comprises thick grid oxide layer.
4. a kind of programmable memory cell according to claim 1 is characterized in that, described transistor seconds is the data storage transistor.
5. a kind of programmable memory cell according to claim 1 is characterized in that described transistor seconds comprises thin grid oxide layer.
6. a kind of programmable memory cell according to claim 1 is characterized in that, described transistor seconds is half transistor.
7. a kind of programmable memory cell according to claim 1 is characterized in that, described first, second transistor is a P type MOS transistor.
8. one kind to the described programmed method of reading the isolation programmable storage unit of claim 1, it is characterized in that described first, second, third transistor is a P type MOS transistor, and this programmed method comprises:
On first source electrode of the first transistor, apply first voltage;
On the first trap voltage end of the first transistor, apply first voltage;
On the first grid of the first transistor, apply second voltage;
On the second grid of transistor seconds, apply tertiary voltage;
On the second trap voltage end of transistor seconds, apply first voltage;
The first transistor conducting, make voltage on second ion implanted region of transistor seconds equal to be applied to first voltage on the first transistor source electrode, voltage forms voltage breakdown between the second grid, second ion implanted region of transistor seconds thereby make, this voltage breakdown punctures the grid oxide layer of transistor seconds in the given time, finishes programming operation;
Wherein, the voltage on the described the 3rd transistorized the 3rd source electrode is first voltage, applies first voltage on the described the 3rd transistorized the 3rd grid, makes the 3rd transistor be in closed condition.
9. programmed method according to claim 8 is characterized in that described puncture comprises hard breakdown and soft breakdown, wherein,
Described hard breakdown is with the complete disposable puncture of grid oxide layer;
Described soft breakdown is the process puncture, and the puncture speed of soft breakdown and the thickness of grid oxide layer are inversely proportional to, and is directly proportional with the size of voltage breakdown.
10. programmed method according to claim 8 is characterized in that,
Described first voltage is to be the voltage of twice second voltage at least greater than size;
Described second voltage is 1 voltage for the sign level value;
Described tertiary voltage is 0 voltage for the sign level value.
11. programmed method according to claim 8 is characterized in that, described voltage breakdown is to be the voltage of twice second voltage at least greater than size.
12. one kind to the described read method of reading the isolation programmable storage unit of claim 1, it is characterized in that described first, second, third transistor is a P type MOS transistor, this read method comprises:
On first source electrode of the first transistor, apply second voltage;
On the first trap voltage end of the first transistor, apply second voltage;
On the first grid of the first transistor, apply tertiary voltage;
On the second grid of transistor seconds, apply tertiary voltage;
On the second trap voltage end of transistor seconds, apply second voltage;
The first transistor conducting, make voltage on second ion implanted region of transistor seconds equal second voltage on the first transistor first source electrode, voltage is the difference voltage of the tertiary voltage and second voltage between the second grid, second ion implanted region of transistor seconds thereby make;
If the grid oxide layer of transistor seconds is not breakdown, then the transistor seconds equivalence is an electric capacity, and the voltage on the reading bit line is retained as second voltage, and making the data that read is that logical value is 1;
If transistor seconds grid oxide layer breakdown, then the transistor seconds equivalence is a resistance, the voltage on the reading bit line is pulled down to the threshold voltage of the first transistor, making the data that read is logical value 0.
13. read method according to claim 12 is characterized in that,
Described second voltage is 1 voltage for the sign level value;
Described tertiary voltage is 0 voltage for the sign level value.
14. one kind to the described programmed method of reading the isolation programmable storage unit of claim 1, it is characterized in that described first, second, third transistor is a N type MOS transistor, this programmed method comprises:
In first drain electrode of the first transistor, apply first voltage;
On the first grid of the first transistor, apply first voltage;
On the first trap voltage end of the first transistor, apply tertiary voltage;
Voltage on first source electrode of the first transistor is the voltage that is less than or equal to second voltage;
On the second grid of transistor seconds, apply tertiary voltage;
On the second trap voltage end of transistor seconds, apply tertiary voltage;
The first transistor conducting, make voltage on second ion implanted region of transistor seconds equal to be applied to first voltage on the first transistor source electrode, voltage forms voltage breakdown between the second grid, second ion implanted region of transistor seconds thereby make, this voltage breakdown punctures the grid oxide layer of transistor seconds in the given time, finishes programming operation;
Wherein, the voltage on the described the 3rd transistorized the 3rd source electrode is first voltage, applies second voltage on the described the 3rd transistorized the 3rd grid, makes the 3rd transistor be in closed condition.
15. programmed method according to claim 14 is characterized in that, described puncture comprises hard breakdown and soft breakdown, wherein,
Described hard breakdown is with the complete disposable puncture of grid oxide layer;
Described soft breakdown is the process puncture, and the puncture speed of soft breakdown and the thickness of grid oxide layer are inversely proportional to, and is directly proportional with the size of voltage breakdown.
16. programmed method according to claim 14 is characterized in that, described first voltage is to be the voltage of twice second voltage at least greater than size; Described second voltage is 1 voltage for the sign level value;
Described tertiary voltage is 0 voltage for the sign level value.
17. programmed method according to claim 14 is characterized in that, described voltage breakdown is to be the voltage of twice second voltage at least greater than size.
18. one kind to the described read method of reading the isolation programmable storage unit of claim 1, it is characterized in that described first, second, third transistor is a N type MOS transistor, this read method comprises:
In first drain electrode of the first transistor, apply second voltage;
On the first grid of the first transistor, apply second voltage;
On the first trap voltage end of the first transistor, apply tertiary voltage;
Voltage on first source electrode of the first transistor is the voltage that is less than or equal to second voltage;
On the second grid of transistor seconds, apply tertiary voltage;
On the second trap voltage end of transistor seconds, apply tertiary voltage;
The first transistor conducting, make voltage on second ion implanted region of transistor seconds equal first voltage on the first transistor first source electrode, make that voltage is the difference voltage of the tertiary voltage and first voltage between the second grid, second ion implanted region of transistor seconds;
If the grid oxide layer of transistor seconds is not breakdown, then the transistor seconds equivalence is an electric capacity, and the voltage on the reading bit line is retained as second voltage, and making the data that read is that logical value is 1;
If transistor seconds grid oxide layer breakdown, then the transistor seconds equivalence is a resistance, the voltage on the reading bit line is pulled down to the threshold voltage of the first transistor, making the data that read is logical value 0.
19. programmed method according to claim 18 is characterized in that,
Described first voltage is to be the voltage of twice second voltage at least greater than size;
Described second voltage is 1 voltage for the sign level value;
Described tertiary voltage is 0 voltage for the sign level value.
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