CN101350221B - Method for preventing non-volatility memory array from generating bit line interference - Google Patents
Method for preventing non-volatility memory array from generating bit line interference Download PDFInfo
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- CN101350221B CN101350221B CN2007100440919A CN200710044091A CN101350221B CN 101350221 B CN101350221 B CN 101350221B CN 2007100440919 A CN2007100440919 A CN 2007100440919A CN 200710044091 A CN200710044091 A CN 200710044091A CN 101350221 B CN101350221 B CN 101350221B
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Abstract
The invention discloses a method for preventing a non-volatile memory array from producing a bit line interference, the non-volatile memory array comprises a plurality of storage units which comprises gates, source cathodes and drains and are arranged in an array form, the gates of the storage units on each row are all connected with a word line, the source cathodes and the drains of the storage units on each column are respectively connected with a bit line, and the storage units on two adjacent columns share a bit line. When a certain storage unit receives programming, if one bit line of the two bit lines which are connected with other storage units is located on a high electric potential and the other one is located on an impending state, the other storage units are loaded with source cathode bias voltage and substrate bias voltage. Using the method of the invention, the non-volatile memory array can be prevented from producing the bit line interference, thereby increasing the performance of memory devices.
Description
Technical field
The present invention relates to the erasable technology of data of semiconductor devices, relate in particular to and prevent that non-volatile memory array from producing the method that bit line disturbs.
Background technology
Non-volatility memorizer (nonvolatile memory) is a kind of semiconductor devices commonly used, and according to the difference of material, structure, non-volatility memorizer can be divided into many types.With nitrogen ROM (read-only memory) (NROM) is example, it has device architecture as shown in Figure 1, it comprises: substrate 1, be formed at the source electrode 2 in the substrate 1 and drain 3, and the grid 4 that is formed at substrate 1 top, wherein, also have three superimposed insulation courses 51,52,53 between grid 4 and the substrate 1, middle one deck 52 is for catching sunken charge layer (charge-trappinglayer), be used to store data, the insulation course 51,53 of both sides is used to pin the electric charge in middle layer 52 up and down.The two ends that mend to fall into charge layer 52 have chargeable regional 61,62, are respectively applied for the data of storage one bit.
Fig. 2 is the structural representation of non-volatility memorizer array, and this array is formed with array format by several storage unit as shown in Figure 1, and for the purpose of simplifying the description, 16 unit that only drawn among the figure can carry out the expansion of structure as required in practical application.The grid of the storage unit of each row all is connected to a word line (Word Line, WL), the source electrode of the storage unit of each row and drain electrode are connected to a bit lines (BitLine respectively, BL), and a shared bit lines between adjacent two array storage units, for example shared bit line BL2 between storage unit C11～C41 and the storage unit C12～C42.
In the time need programming to a storage unit on a certain bit lines, the interference to adjoining memory cell appears easily.With storage unit C11 is example, when being programmed, it need on bit line BL2, add noble potential, because storage unit C22 and C11 shared bit line BL2, so also present noble potential on the source electrode of C22, because bit line BL3 is unsettled, therefore can have electric potential difference between the source electrode of C22 and the drain electrode, this electric potential difference can cause the threshold voltage variation amount DVt of storage unit C22 to increase, thereby has influence on the performance of storage unit.Except C22, the storage unit (no matter whether programming) of other and C11 shared bit line BL2 also can be subjected to similar interference, and is big more near the suffered interference of the storage unit of C11.
Summary of the invention
Technical matters solved by the invention is to provide a kind of method, with the generation that prevents that the non-volatile memory array neutrality line from disturbing, thus the performance of raising memory device.
For solving the problems of the technologies described above, the invention provides a kind of non-volatile memory array that prevents and produce the method that bit line disturbs, described non-volatile memory array comprises grid by several, source electrode, the storage unit of drain electrode forms with array format, the grid of the storage unit of each row all is connected to a word line, the source electrode of the storage unit of each row and drain electrode are connected to a bit line respectively, an and shared bit lines between adjacent two array storage units, described method when a certain storage unit when accepting programming, if the bit line that drain electrode connected of other storage unit is in noble potential, when the bit line that source electrode connected is in vacant state, then this other storage unit is loaded an one source pole bias voltage and a substrate bias voltage, wherein, the scope of described source bias voltage is 0～1.5V.
Further, the scope of described substrate bias voltage is 0～0.3V.
Further, described storage unit comprises substrate, be formed at source electrode and drain electrode in the substrate, and the grid that is formed at the substrate top, wherein, also have three superimposed insulation courses between grid and the substrate, the middle layer is used to catch sunken electric charge, the insulation course on both sides is used to pin the electric charge in middle layer, and described middle layer has two chargeable zones, is respectively applied for the data of storage one bit.
Compared with prior art, the present invention is when carrying out the programming of single storage unit to non-volatile memory array, the storage unit that is adjacent is loaded source bias voltage and substrate bias voltage, by regulating the size of these two bias voltages, can effectively reduce the electric potential difference of storage unit inside, thereby eliminate or improved the bit line interference, simultaneously, can not influence the programming efficiency of accepting the storage unit of programming.
Description of drawings
The method that prevents that non-volatile memory array generation bit line from disturbing of the present invention is provided by following embodiment and accompanying drawing.
Fig. 1 is a kind of structural representation of non-volatility memorizer.
Fig. 2 is the structural representation of non-volatile memory array.
Vs, Vb that Fig. 3 obtains for the present invention tests for first group and the graph of a relation of DVt.
Vs, Vb that Fig. 4 obtains for the present invention tests for second group and the graph of a relation of DVt.
Embodiment
Below will be described in further detail the method that prevents that non-volatile memory array generation bit line from disturbing of the present invention.
Method of the present invention be when a certain storage unit when accepting programming, if its contiguous one of two bit lines that storage unit connected are in noble potential, one and are in vacant state, be when having electric potential difference between source electrode and the drain electrode, this storage unit to be loaded an one source pole bias voltage Vs and a substrate bias voltage Vb.
Referring to Fig. 2, for example when storage unit C11 was accepting to programme, bit line BL2 was in noble potential, and bit line BL3 then is in vacant state, and promptly there is situation about being disturbed in the storage unit C22 of this moment, and need load bias voltage Vs and Vb to it.
In order to determine best bias voltage value, respectively the storage unit C22 that carries out programming and carried out programming had not been carried out following experiment, C11 is accepting the storage unit of programming in the experimentation.
At first, add zero offset for unchecked word line WL2～WL4, the grid voltage Vg that makes storage unit C22 is zero; Then, add a noble potential on the bit line BL2 that is chosen, size is controlled between 4.5V～5.5V, makes the drain voltage Vd of C22 remain between 4.5V～5.5V, the duration of this current potential equals long pulse width PW, and for example setting PW is 10ms; Then, on storage unit C22, load source bias voltage Vs and substrate bias voltage Vb, and the size of regulating Vs and Vb, corresponding threshold voltage variation amount write down; At last, find out best bias voltage value according to the test result that is write down.
Table 1 is that the storage unit C22 that did not accept programming is carried out the parameter value that above-mentioned experiment is adopted, and wherein, the scope of Vb is 0～0.3V, and the scope of Vs is 0～2.5V.The situation of change of Fig. 3 threshold voltage vt that to be the parameter value that provides according to table 1 obtain from C22, the longitudinal axis among the figure is represented threshold voltage variation amount DVt, the value of DVt is more little, more near ideal situation.
Table 2 is that the storage unit C22 that accepted programming is carried out the parameter value that above-mentioned experiment is adopted, and wherein, the scope of Vb is 0～0.3V, and the scope of Vs is 0～2.0V.The situation of change of Fig. 4 threshold voltage vt that to be the parameter value that provides according to table 2 obtain from C22, different with Fig. 3 is, the threshold voltage variation amount here is a negative value, so the longitudinal axis is designated as-DVt, similarly, the value of-DVt is more little, more near ideal situation.
Usually, when | DVt| is controlled at and promptly belongs to acceptable scope below the 0.2V, as can be seen, works as Vs=1.5V from Fig. 3, Fig. 4, during Vb=0.3V, | DVt| is reduced to below the 0.2V, is preferable value.Certainly, continue increasing Vs can also further reduce | DVt|, but do not have this necessity in actual applications, and also the Vs value is excessive also can cause the problem that other is unnecessary.
In sum, adopt method of the present invention can prevent effectively that the bit line of non-volatile memory array from disturbing.
Table 1
Table 2
Claims (6)
1. one kind prevents that non-volatile memory array from producing the method that bit line disturbs, described non-volatile memory array comprises grid by several, source electrode, the storage unit of drain electrode forms with array format, the grid of the storage unit of each row all is connected to a word line, the source electrode of the storage unit of each row and drain electrode are connected to a bit line respectively, an and shared bit lines between adjacent two array storage units, it is characterized in that: described method when a certain storage unit when accepting programming, if the bit line that drain electrode connected of other storage unit is in noble potential, when the bit line that source electrode connected is in vacant state, then this other storage unit is loaded an one source pole bias voltage and a substrate bias voltage, wherein, the scope of described source bias voltage is 0～1.5V.
2. the nonvolatile memory array that prevents as claimed in claim 1 produces the method that bit line disturbs, and it is characterized in that: described source bias voltage is 1.5V.
3. the nonvolatile memory array that prevents as claimed in claim 1 produces the method that bit line disturbs, and it is characterized in that: the scope of described substrate bias voltage is 0～0.3V.
4. the nonvolatile memory array that prevents as claimed in claim 3 produces the method that bit line disturbs, and it is characterized in that: described substrate bias voltage is 0.3V.
5. the nonvolatile memory array that prevents as claimed in claim 1 produces the method that bit line disturbs, it is characterized in that: described storage unit comprises substrate, be formed at source electrode and drain electrode in the substrate, and the grid that is formed at the substrate top, wherein, also have three superimposed insulation courses between grid and the substrate, the middle layer is used to catch sunken electric charge, and the insulation course on both sides is used to pin the electric charge in middle layer.
6. the nonvolatile memory array that prevents as claimed in claim 5 produces the method that bit line disturbs, and it is characterized in that: described middle layer has two chargeable zones, is respectively applied for the data of storage one bit.
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| CN2007100440919A CN101350221B (en) | 2007-07-20 | 2007-07-20 | Method for preventing non-volatility memory array from generating bit line interference |
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| CN101350221B true CN101350221B (en) | 2010-12-15 |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040027894A1 (en) * | 2001-02-27 | 2004-02-12 | Aplus Flash Technology, Inc. | Novel set of three level concurrent word line bias conditions for a NOR type flash memory array |
| WO2005029502A1 (en) * | 2003-09-17 | 2005-03-31 | Sandisk Corporation | Non-volatile memory and method with bit line to bit line coupled compensation |
| CN1610123A (en) * | 2004-10-15 | 2005-04-27 | 清华大学 | SONDS fast flash memory array framework capable of realizing reverse reading |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040027894A1 (en) * | 2001-02-27 | 2004-02-12 | Aplus Flash Technology, Inc. | Novel set of three level concurrent word line bias conditions for a NOR type flash memory array |
| WO2005029502A1 (en) * | 2003-09-17 | 2005-03-31 | Sandisk Corporation | Non-volatile memory and method with bit line to bit line coupled compensation |
| CN1610123A (en) * | 2004-10-15 | 2005-04-27 | 清华大学 | SONDS fast flash memory array framework capable of realizing reverse reading |
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