CN101345207A - Non-volatile memory, source/drain line plug and manufacturing method thereof - Google Patents
Non-volatile memory, source/drain line plug and manufacturing method thereof Download PDFInfo
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- CN101345207A CN101345207A CNA2007101283807A CN200710128380A CN101345207A CN 101345207 A CN101345207 A CN 101345207A CN A2007101283807 A CNA2007101283807 A CN A2007101283807A CN 200710128380 A CN200710128380 A CN 200710128380A CN 101345207 A CN101345207 A CN 101345207A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 30
- 239000000463 material Substances 0.000 claims abstract description 80
- 239000000758 substrate Substances 0.000 claims abstract description 62
- 229910052751 metal Inorganic materials 0.000 claims abstract description 56
- 239000002184 metal Substances 0.000 claims abstract description 56
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 51
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 51
- 239000010703 silicon Substances 0.000 claims abstract description 48
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 34
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 34
- 238000000034 method Methods 0.000 claims abstract description 33
- 238000002955 isolation Methods 0.000 claims description 37
- 238000003973 irrigation Methods 0.000 claims description 35
- 230000002262 irrigation Effects 0.000 claims description 35
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 10
- 229910021341 titanium silicide Inorganic materials 0.000 claims description 10
- 238000005516 engineering process Methods 0.000 claims description 9
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 9
- 229910052721 tungsten Inorganic materials 0.000 claims description 9
- 239000010937 tungsten Substances 0.000 claims description 9
- 230000015572 biosynthetic process Effects 0.000 claims description 8
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 8
- 229920005591 polysilicon Polymers 0.000 claims description 8
- 238000000151 deposition Methods 0.000 claims description 6
- 229910000077 silane Inorganic materials 0.000 claims description 6
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 claims description 5
- 238000005229 chemical vapour deposition Methods 0.000 claims description 4
- SVXHDONHRAZOCP-UHFFFAOYSA-N ethane;silicon Chemical compound [Si].CC SVXHDONHRAZOCP-UHFFFAOYSA-N 0.000 claims description 3
- POXCVKMBBFNXLZ-UHFFFAOYSA-N propane;silicon Chemical compound [Si].CCC POXCVKMBBFNXLZ-UHFFFAOYSA-N 0.000 claims description 3
- 239000004575 stone Substances 0.000 claims description 3
- 238000000059 patterning Methods 0.000 claims 1
- 150000004756 silanes Chemical class 0.000 claims 1
- 238000000926 separation method Methods 0.000 abstract 4
- 230000002950 deficient Effects 0.000 description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 239000011521 glass Substances 0.000 description 4
- 230000012447 hatching Effects 0.000 description 4
- 238000003860 storage Methods 0.000 description 3
- 230000005641 tunneling Effects 0.000 description 3
- 239000004020 conductor Substances 0.000 description 2
- 238000010276 construction Methods 0.000 description 2
- 239000003989 dielectric material Substances 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 239000011800 void material Substances 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 230000002159 abnormal effect Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 125000006239 protecting group Chemical group 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
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Abstract
The invention provides a manufacture method used for a source/drain wire jack plug, comprising the steps as follows: firstly, a plurality of element separation structures are formed in a substrate; furthermore, an active area is defined between two adjacent element separation structures; subsequently, a source/drain area is formed in the substrate of each active area; subsequently, a part of the element separation structure at two sides of the source/drain is removed so as to lead the surface of the element separation structure to be lower than the substrate surface of the source/drain; subsequently, a dielectric layer is formed on the substrate; subsequently, the dielectric layer is patterned so as to form a plurality of ditches which lead the source/drain areas to be exposed out; subsequently, a selective silicon growth material layer is formed on the source/drain areas exposed out of the ditches so as to at least cover an apical angle of the substrate of the source/drain area; subsequently, a metal silicide layer and a metal layer are sequentially formed on the selective silicon growth material layer so as to fill the ditches, thus forming a plurality of source/drain wire jack plugs.
Description
Technical field
The present invention relates to a kind of nonvolatile memory and manufacture method thereof, more specifically, relate to a kind of NAND type nonvolatile memory, source/drain line plug and manufacture method thereof.
Background technology
At present the flash memory array that more often uses of industry comprise or non-(NOR) type array structure and with non-(NAND) type array structure.Because NAND type array structure is to make a plurality of memory cell connection bunchiness (string) that only are connected to the bit line of a correspondence via same contact, its integrated level is compared better with NOR type array structure, therefore be widely used in the multiple electronic product.
Generally speaking, in NAND type array structure, when carrying out the reading of memory cell (read) operation, reading electric current can be by with a string memory cell, and converge whole to source electrode line (source line, SL), with reading of data.Hold above-mentionedly, source electrode line is arranged to be selected grid (selective gate is SG) in the silicon base between the structure.In addition, above source electrode line, also can be provided with source electrode line connector (SL plug).
For the integrated level of tackling integrated circuit technology improves constantly, and the resistance value problem of higher of source electrode line connector, industry proposes to form earlier titanium silicide, inserts tungsten again, with the material as the source electrode line connector.Yet, in the technology that forms titanium silicide, can consume the silicon atom in the silicon base simultaneously, and cause producing hole (void) or crack faults of construction such as (seam) (dotted line as Fig. 1 encloses shown in the place 100) in the silicon base of source electrode line connector bottom.Above-mentioned defective can make nand type memory when carrying out read operation, has with a string memory cell and reads unusual (read fail), and have influence on the usefulness and the reliability of memory component widely.
Summary of the invention
In view of this, one of purpose of the present invention just provides a kind of NAND type nonvolatile memory, source/drain line plug and manufacture method thereof, can avoid known substrate produce defective such as hole or crack and caused read abnormal problem and the usefulness and the reliability that can improve memory component.
The present invention proposes a kind of source plug manufacture.At first, in substrate, form a plurality of component isolation structures be arranged in parallel, and define active area between the two adjacent component isolation structures.Then, in the substrate of each active area, form source.Then, remove the component isolation structure of part source/drain regions both sides, make the surface of component isolation structure be lower than the substrate surface of source/drain regions.Afterwards, in substrate, form dielectric layer.Then, pattern dielectric layer, with a plurality of irrigation canals and ditches of formation with the component isolation structure vertical arrangement, these irrigation canals and ditches expose source/drain regions respectively.Then, carry out a selective silicon growth technique, with formation one material layer on the source/drain regions that irrigation canals and ditches were exposed, and material layer covers the drift angle of the substrate of source/drain regions at least.Afterwards, on material layer, form metal silicide layer and metal level in regular turn filling up irrigation canals and ditches, thereby form a plurality of source/drain line plugs.
According to the described source plug manufacture of the embodiment of the invention, before forming irrigation canals and ditches, also be included in and form a plurality of openings that expose the drain region in the dielectric layer.And, in these openings, also can further be formed with the above-mentioned material layer.
According to the described source plug manufacture of the embodiment of the invention, above-mentioned selective silicon growth technique for example uses silane gas as reacting gas.Wherein, silane gas for example is silicomethane, silicon ethane or silicon propane.
According to the described source plug manufacture of the embodiment of the invention, above-mentioned selective silicon growth technique for example is a brilliant technology of heap of stone.
According to the described source plug manufacture of the embodiment of the invention, above-mentioned selective silicon growth technique for example is the selective silicon depositing operation, and the selective silicon depositing operation for example is a chemical vapour deposition technique.
According to the described source plug manufacture of the embodiment of the invention, the material of above-mentioned material layer for example is to mix or unadulterated monocrystalline silicon, doping or unadulterated polysilicon.
According to the described source plug manufacture of the embodiment of the invention, the material of above-mentioned metal level for example is a tungsten.
According to the described source plug manufacture of the embodiment of the invention, the material of above-mentioned metal silicide layer for example is a titanium silicide.
The present invention also proposes a kind of NAND type nonvolatile memory, and it comprises: substrate, a plurality of NAND type memory cell string, dielectric layer, selective silicon growth material layer, metal silicide layer and metal level.Be formed with a plurality of component isolation structures that are arranged in parallel in the substrate, and defined active area between the two adjacent component isolation structures.A plurality of NAND type memory cell strings are disposed in the active area, and each NAND type memory cell string comprises an one source pole district and a drain region that is formed in the substrate.Wherein, the surface of the component isolation structure of source area both sides and both sides, drain region is lower than substrate surface.In addition, dielectric layer is disposed in the substrate, and has a plurality of irrigation canals and ditches with the component isolation structure vertical arrangement in the dielectric layer, and irrigation canals and ditches expose source area.Selective silicon growth material layer is disposed on the source area that irrigation canals and ditches expose, and covers the drift angle of the substrate of source area at least.Metal silicide layer is disposed on the selective silicon growth material layer.Metal level is disposed on the metal silicide layer and fills up irrigation canals and ditches.
According to the described NAND type of embodiment of the invention nonvolatile memory, have a plurality of openings that expose the drain region above-mentioned also comprising in dielectric layer.And above-mentioned selective silicon growth material layer also is configured in these openings.
According to the described NAND type of embodiment of the invention nonvolatile memory, the material of above-mentioned selective silicon growth material layer for example is to mix or unadulterated monocrystalline silicon, doping or unadulterated polysilicon.
According to the described NAND type of embodiment of the invention nonvolatile memory, the material of above-mentioned metal level for example is a tungsten.
According to the described NAND type of embodiment of the invention nonvolatile memory, the material of above-mentioned metal silicide layer for example is a titanium silicide.
The present invention also proposes a kind of source/drain line plug, and it comprises substrate, dielectric layer, selective silicon growth material layer, metal silicide layer and metal level.Have a plurality of component isolation structures that are arranged in parallel in the substrate, define an active area between the two adjacent component isolation structures, and form source in the substrate of each active area.Wherein, the surface of component isolation structure is lower than the substrate surface of source/drain regions.Dielectric layer is disposed in the substrate, and has a plurality of irrigation canals and ditches with the component isolation structure vertical arrangement in the dielectric layer, to expose source/drain regions.Selective silicon growth material layer is disposed on the source/drain regions that irrigation canals and ditches expose, and covers the drift angle of the substrate of source/drain regions at least.Metal silicide layer is disposed on the selective silicon growth material layer.Metal level is disposed on the metal silicide layer, and fills up irrigation canals and ditches.
According to the described source/drain line plug of the embodiment of the invention, the material of above-mentioned selective silicon growth material layer for example is to mix or unadulterated monocrystalline silicon, doping or unadulterated polysilicon.
According to the described source/drain line plug of the embodiment of the invention, the material of above-mentioned metal level for example is a tungsten.
According to the described source/drain line plug of the embodiment of the invention, the material of above-mentioned metal silicide layer for example is a titanium silicide.
Because method of the present invention is before metal silicide layer is formed on the irrigation canals and ditches bottom; can form selective silicon growth material layer; drift angle with the substrate that covers source area at least; therefore; but at the bottom of the selective silicon growth material layer protecting group; avoiding the silicon atom in the substrate in the manufacture process of metal silicide layer, to be consumed, and produce defectives such as hole or crack.In addition, because do not have defectives such as hole or crack in the substrate of structure of the present invention,, and then can improve the usefulness and the reliability of memory component so reading of being produced can avoid carrying out read operation the time is unusual.On the other hand, the present invention is configurable selective silicon growth material layer in exposing the opening of drain region, therefore can reduce the depth-to-width ratio value of opening, and then improves the nargin of technology.
For above-mentioned and other purposes, feature and advantage of the present invention can be become apparent, embodiment cited below particularly, and cooperate appended graphicly, be described in detail below.
Description of drawings
Fig. 1 illustrates the transmission electron microscope photo of the section of known NAND type nonvolatile memory;
Fig. 2 to Fig. 5 is the schematic diagram according to the manufacturing process of the NAND type nonvolatile memory that the embodiment of the invention illustrated, wherein subgraph (a) illustrates and looks schematic diagram, subgraph (b) illustrates along the generalized section of hatching A-A ', and subgraph (c) illustrates along the generalized section of hatching B-B '.
[main description of reference numerals]
100: dotted line encloses the place
200: substrate
202: component isolation structure
204: active area
206: column of memory cells
208: memory cell
210: the drain region
212: source area
213,226: dielectric layer
214a, 214b: selected cell
215: conductor layer
216: doped region
218: tunneling dielectric layer
220: electric charge storage layer
222: dielectric layer between grid
224: the control grid
225: irrigation canals and ditches
227: opening
235: dotted line
236: material layer
238: metal silicide layer
240: metal level
Embodiment
Fig. 2 to Fig. 5 is the schematic diagram according to the manufacturing process of the NAND type nonvolatile memory that the embodiment of the invention illustrated, wherein subgraph (a) illustrates and looks schematic diagram, subgraph (b) illustrates along the generalized section of hatching A-A ', and subgraph (c) illustrates along the generalized section of hatching B-B '.
At first, please provide substrate 200 simultaneously with reference to Fig. 2 (a), Fig. 2 (b) and Fig. 2 (c), substrate 200 for example is a silicon base.Then, in substrate 200, form a plurality of component isolation structures 202.These component isolation structures 202 are arranged in parallel on directions X (column direction), and define active area 204 between two adjacent component isolation structures 202.Said elements isolation structure 202 for example is a channel isolating structure, and its formation method is well known to those of ordinary skill in the art, does not repeat them here.
Then, in substrate 200, form a plurality of NAND type memory cell strings 206.Each NAND type memory cell string 206 is made of a plurality of memory cell 208, drain region 210 and source area 212 and two selected cell 214a, 214b.Wherein, memory cell 208 is connected in series between drain region 210 and the source area 212.And component isolation structure 202 is understood some and is removed in manufacture process, makes the surface of component isolation structure 202 of source area 212 both sides and 210 both sides, drain region be lower than the surface of substrate 200.Two selected cell 214a, 214b are formed at respectively between outermost two memory cell 208 and drain region 210 in the NAND type memory cell string 206, the source area 212.And, between each memory cell 208 and for example be to link together between memory cell 208 and two selected cell 214a, the 214b with doped region 216.Memory cell 208 comprises dielectric layer 222 and control grid 224 between tunneling dielectric layer 218, electric charge storage layer 220, grid at least from substrate 200.Wherein, the material of dielectric layer 222 for example is a silicon oxide/silicon nitride/silicon oxide between grid, and the material of electric charge storage layer 220 for example is a doped polycrystalline silicon, and the material of tunneling dielectric layer 218 for example is a silica, and the material of control grid 224 for example is a doped polycrystalline silicon.Selected cell 214a, 214b are made of one dielectric layer 213 and one deck conductor layer 215.
Afterwards, please in substrate 200, form dielectric layer 226 simultaneously with reference to Fig. 3 (a), Fig. 3 (b) and Fig. 3 (c), to cover NAND type memory cell string 206.The material of dielectric layer 226 for example is phosphorosilicate glass, boron-phosphorosilicate glass or other dielectric materials that is fit to, and its formation method for example is a chemical vapour deposition technique.Then, pattern dielectric layer 226, to form a plurality of irrigation canals and ditches 225, irrigation canals and ditches 225 are as the source electrode line plug open.Irrigation canals and ditches 225 are arranged on the Y direction (line direction), and are vertical with component isolation structure 202, and expose source area 212 respectively.In one embodiment, in subsequent technique, can form a plurality of openings 227 in dielectric layer 226, and these openings 227 expose drain region 210, opening 227 is as bit line contact window.
Then, please after irrigation canals and ditches 225 form, then carry out the selective silicon growth technique simultaneously with reference to Fig. 4 (a), Fig. 4 (b) and Fig. 4 (c), to form layer of material layer 236 on the source area 212 that is exposed at irrigation canals and ditches 225.The material of material layer 236 for example is to mix or unadulterated monocrystalline silicon, doping or unadulterated polysilicon.Above-mentioned selective silicon growth technique for example is a selectivity brilliant method of heap of stone.The selective silicon growth technique comprises the use silane gas as reacting gas, and silane gas for example is silicomethane, silicon ethane or silicon propane.In another embodiment, can also utilize another kind of selective silicon growth technique, promptly the selective silicon depositing operation forms material layer 236.The selective silicon depositing operation for example is a chemical vapour deposition technique.
Be noted that the drift angle (shown in dotted line 235) that can cover the substrate 200 of source area 212 with the formed material layer 236 of selective silicon growth technique at least especially.Therefore, material layer 236 can be protected the substrate 200 of active area 204, produces hole (void) or crack faults of construction such as (seam) in the substrate to avoid causing when the follow-up formation metal silicide layer, and influences element efficiency and reliability.
Hold above-mentionedly, in another embodiment, material layer 236 also can be formed in the opening 227.Thus, can further reduce the depth-to-width ratio value of opening 227, to improve the nargin (margin) of technology.
Then, please on material layer 236, form metal silicide layer 238 simultaneously with reference to Fig. 5 (a), Fig. 5 (b) and Fig. 5 (c).The material of metal silicide layer 238 for example is a titanium silicide, and its formation method is well known to those of ordinary skill in the art, does not repeat them here.Particularly, owing to before metal silicide layer 238 forms, be formed with the substrate 200 of material layer 236 earlier, so metal silicide layer 238 can not cause defectives such as hole or crack to substrate 200 with protection active area 204.
Subsequently, on metal silicide layer 238, form metal level 240, to fill up irrigation canals and ditches 225.The material of metal level 240 for example is a tungsten, and its formation method is well known to those of ordinary skill in the art, does not repeat them here.Wherein, metal level 240, metal silicide layer 238 and material layer 236 can constitute source electrode line connector (source line plug).And the follow-up technology of finishing semiconductor element is well known to those of ordinary skill in the art, does not repeat them here.
Next, the structure that NAND type nonvolatile memory of the present invention is described with Fig. 5 (a), Fig. 5 (b) and Fig. 5 (c) of the foregoing description.
Please once more simultaneously with reference to Fig. 5 (a), Fig. 5 (b) and Fig. 5 (c), NAND type nonvolatile memory of the present invention mainly is made up of substrate 200, a plurality of NAND type memory cell string 206, dielectric layer 226, material layer 236, metal silicide layer 238 and metal level 240.Wherein, be formed with a plurality of component isolation structures 202 that are arranged in parallel in the substrate 200, and two adjacent component isolation structures 202 define active area 204.A plurality of NAND type memory cell strings 206 are disposed in the active area 204, and NAND type memory cell string 206 comprises drain region 210, source area 212, memory cell 208, selected cell 214a and 214b and doped region 216.The surface of the component isolation structure 202 of source area 212 both sides and 210 both sides, drain region is lower than substrate 200 surfaces.The material of each member of NAND type memory cell string 206 describes in detail in the foregoing description with composition, does not repeat them here.
In one embodiment, also has the opening 227 that exposes drain region 210 in the dielectric layer 226.This opening 227 is as character line contact window.And also configurable in opening 227 have a material layer 236, reducing the depth-to-width ratio value of opening, and then improves the nargin of technology.
Because the silicon base of the source electrode line connector of the NAND type nonvolatile memory of present embodiment bottom can not produce defectives such as hole or crack, therefore when carrying out the read operation of NAND type nonvolatile memory, do not have with a string memory cell and (read fail) unusually occur reading.
In sum, the present invention can avoid the silicon atom in the substrate to be consumed in the manufacture process of metal silicide layer, and causes producing in the silicon base of source electrode line connector bottom defectives such as space or crack.And reading that the present invention is produced in the time of also can avoiding carrying out read operation is unusual, and the usefulness and the reliability that can improve memory component.
Though the present invention discloses as above with embodiment; but it is not in order to limit the present invention; any those of ordinary skills without departing from the spirit and scope of the present invention; can carry out some and change and retouching, thus protection scope of the present invention should with appending claims the person of being defined be as the criterion.
Claims (21)
1. source plug manufacture comprises:
In substrate, form a plurality of component isolation structures be arranged in parallel, define active area between the two adjacent component isolation structures;
In the substrate of each active area, form source/drain regions;
Remove this component isolation structure of each source/drain regions both sides of part, make the surface of this component isolation structure be lower than this substrate surface of this source/drain regions;
In this substrate, form dielectric layer;
This dielectric layer of patterning, with a plurality of irrigation canals and ditches of formation with those component isolation structure vertical arrangements, those irrigation canals and ditches expose those source/drain regions respectively;
Carry out the selective silicon growth technique, forming material layer on those source/drain regions that those irrigation canals and ditches were exposed, and this material layer covers the drift angle of this substrate of those source/drain regions at least; And
On this material layer, form metal silicide layer and metal level in regular turn filling up those irrigation canals and ditches, thereby form a plurality of source/drain line plugs.
2. source plug manufacture as claimed in claim 1 wherein before forming those irrigation canals and ditches, also is included in and forms a plurality of openings that expose those drain regions in this dielectric layer.
3. source plug manufacture as claimed in claim 2, wherein this material layer also comprises and being formed in those openings.
4. source plug manufacture as claimed in claim 1, wherein this selective silicon growth technique comprises that the use silane gas is as reacting gas.
5. source plug manufacture as claimed in claim 4, wherein this silane gas comprises silicomethane, silicon ethane or silicon propane.
6. source plug manufacture as claimed in claim 1, wherein this selective silicon growth technique comprises brilliant technology of heap of stone.
7. source plug manufacture as claimed in claim 1, wherein this selective silicon growth technique comprises the selective silicon depositing operation.
8. source plug manufacture as claimed in claim 7, wherein this selective silicon depositing operation comprises chemical vapour deposition technique.
9. source plug manufacture as claimed in claim 1, wherein the material of this material layer comprises doping or unadulterated monocrystalline silicon, doping or unadulterated polysilicon.
10. source plug manufacture as claimed in claim 1, wherein the material of this metal level comprises tungsten.
11. source plug manufacture as claimed in claim 1, wherein the material of this metal silicide layer comprises titanium silicide.
12. a NAND type nonvolatile memory comprises:
Substrate has been formed with a plurality of component isolation structures that are arranged in parallel in this substrate, define active area between the two adjacent component isolation structures;
A plurality of NAND type memory cell strings are disposed in those active areas, and respectively this NAND type memory cell string comprises source area and the drain region that is formed in this substrate,
Wherein respectively these source area both sides and respectively the surface of this component isolation structure of these both sides, drain region be lower than this substrate surface;
Dielectric layer is disposed in this substrate, and has a plurality of irrigation canals and ditches with those component isolation structure vertical arrangements in this dielectric layer, to expose those source areas;
Selective silicon growth material layer is disposed on those source areas that those irrigation canals and ditches expose, and covers the drift angle of this substrate of this source area at least;
Metal silicide layer is disposed on this selective silicon growth material layer; And
Metal level is disposed on this metal silicide layer, and fills up those irrigation canals and ditches.
13. NAND type nonvolatile memory as claimed in claim 12 wherein also comprises having a plurality of openings that expose those drain regions in this dielectric layer.
14. NAND type nonvolatile memory as claimed in claim 13, wherein this selective silicon growth material layer also comprises and being disposed in those openings.
15. NAND type nonvolatile memory as claimed in claim 12, wherein the material of this selective silicon growth material layer comprises doping or unadulterated monocrystalline silicon, doping or unadulterated polysilicon.
16. NAND type nonvolatile memory as claimed in claim 12, wherein the material of this metal level comprises tungsten.
17. NAND type nonvolatile memory as claimed in claim 12, wherein the material of this metal silicide layer comprises titanium silicide.
18. a source/drain line plug comprises:
Substrate, have a plurality of component isolation structures that are arranged in parallel in this substrate, define active area between the two adjacent component isolation structures, and respectively form source/drain regions in this substrate of this active area, wherein the surface of this component isolation structure is lower than this substrate surface of this source/drain regions;
Dielectric layer is disposed in this substrate, and has a plurality of irrigation canals and ditches with those component isolation structure vertical arrangements in this dielectric layer, to expose those source/drain regions;
Selective silicon growth material layer is disposed on those source/drain regions that those irrigation canals and ditches expose, and covers the drift angle of this substrate of this source/drain regions at least;
Metal silicide layer is disposed on this selective silicon growth material layer; And
Metal level is disposed on this metal silicide layer, and fills up those irrigation canals and ditches.
19. source/drain line plug as claimed in claim 18, wherein the material of this selective silicon growth material layer comprises doping or unadulterated monocrystalline silicon, doping or unadulterated polysilicon.
20. source/drain line plug as claimed in claim 18, wherein the material of this metal level comprises tungsten.
21. source/drain line plug as claimed in claim 18, wherein the material of this metal silicide layer comprises titanium silicide.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA2007101283807A CN101345207A (en) | 2007-07-10 | 2007-07-10 | Non-volatile memory, source/drain line plug and manufacturing method thereof |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA2007101283807A CN101345207A (en) | 2007-07-10 | 2007-07-10 | Non-volatile memory, source/drain line plug and manufacturing method thereof |
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| Publication Number | Publication Date |
|---|---|
| CN101345207A true CN101345207A (en) | 2009-01-14 |
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| CNA2007101283807A Pending CN101345207A (en) | 2007-07-10 | 2007-07-10 | Non-volatile memory, source/drain line plug and manufacturing method thereof |
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| CN (1) | CN101345207A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109148371A (en) * | 2017-06-16 | 2019-01-04 | 台湾积体电路制造股份有限公司 | Semiconductor device and its manufacturing method |
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2007
- 2007-07-10 CN CNA2007101283807A patent/CN101345207A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109148371A (en) * | 2017-06-16 | 2019-01-04 | 台湾积体电路制造股份有限公司 | Semiconductor device and its manufacturing method |
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