CN101345090A - Memory element test method - Google Patents
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- CN101345090A CN101345090A CNA2007101283741A CN200710128374A CN101345090A CN 101345090 A CN101345090 A CN 101345090A CN A2007101283741 A CNA2007101283741 A CN A2007101283741A CN 200710128374 A CN200710128374 A CN 200710128374A CN 101345090 A CN101345090 A CN 101345090A
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Abstract
The invention provides a testing method of a memory element, which is applicable for a testing machine station; wherein, the testing machine station is provided with a first memory; the testing method of the memory element comprises the step of providing the memory element to be tested. Subsequently, according to the dimension of the memory element to be tested and the dimension of the first memory of the testing machine station, N testing samples are generated; wherein, the dimension of the memory element to be tested is N times of the dimension of the first memory of the testing machine station; and N is more than 1; subsequently, the N testing samples are used and the memory element to be tested is tested.
Description
Technical field
The present invention relates to a kind of method of testing of memory component, particularly relate to a kind of method of testing of dynamic RAM.
Background technology
At some memory components dynamic RAM (Dynamic Random AccessMemory for example, DRAM) in the test process, because the storage unit (cell) of memory component is aligned to the shape as array, therefore the test result of each storage unit is to represent whether to pass through test, that is whether this memory cell operation is normal with the data of a bit.The test result of all storage unit; to be stored a binary figure; be called mistake bit figure (fail bit map); can know the integrated testability result of memory component by wrong bit figure; memory cell operation is normal during for example as if test; signable is " 1 "; on the contrary; as if operating undesired or making a mistake; signable is " 0 "; so can check the quality of the memory component that produces according to wrong bit figure, determine follow-up processing to move or repair again at particular memory location.See also Fig. 1.Fig. 1 illustrates the synoptic diagram of a known test macro 100.As shown in the figure, memory component 110 to be measured is sent to a tester table 120 and tests, and the result of test is observed on computer installation 130 by on-line operation person or slip-stick artist again.The address error memory (address fail memory, AFM) 122, the address that makes a mistake in the memory component when testing that have comprised a fixed size in the tester table 120 in order to store.Because the address error memory of tester table is fixed, therefore can certain restriction must be arranged, with the test result of all storage unit of storing memory component to be measured in order to the size (size) of the memory component of test.For instance, if a tester table 120 has the address error memory that is of a size of the 512*512 bit, then these tester table 120 maximums can be in order to test a memory component that is of a size of the 512*512 bit.
Test simultaneously owing to have several memory components to be measured on the tester table, tester table will be according to the characteristic of different test patterns, and the address error memory space of distributing different sizes is to write down the test result of each memory component to be measured.When not having enough spaces can write down the test result of all memory components to be measured in the address error memory, will make test to carry out smoothly.
In addition, heal when big when the size of memory component more becomes, the address error memory of tester table is not come all address of the wrong bit figure of record storage element because of there being enough spaces originally, so can't become big memory component to size and test.For instance, when becoming 512 megabits unit, can't use the tester table of the address error memory that only has 256 megabit units to test as if memory component to be measured.At this moment, if buy more board,, do not calculate very much increasing huge testing cost with larger capacity.
Summary of the invention
In view of this, one of purpose of the present invention is to provide a kind of method of testing that is applicable to the memory component of tester table, can test the memory component of large-size with the tester table with less memory-size, required cost when reducing test.
Based on above-mentioned purpose, the invention provides a kind of method of testing of memory component, be applicable to a tester table, wherein tester table has first memory.The method of testing of memory component comprises the following steps.At first, provide memory component to be measured.Afterwards, the size according to the first memory of the size of memory component to be measured and tester table produces N test sample book (test pattern), and memory component wherein to be measured is of a size of N times of size of the first memory of tester table, and N＞1.Then, utilize N test sample book in regular turn, memory component to be measured is tested.
The present invention also provides a kind of method of testing of memory component, is applicable to a tester table, and wherein tester table has first memory.The method of testing of memory component comprises that changing the pin relevant with the address of memory component to be measured disposes, memory component wherein to be measured has the blank block of a plurality of no datat and a plurality of block, blank block and block are distributed in the memory component to be measured discontinuously and skip over the blank block that is distributed in the memory component to be measured, so that discontinuously arranged block is read continuously and is tested, and with the test result continuity of block be stored in this first memory.Wherein, the size of first memory is less than the size of storage unit to be measured.
The present invention also provides a kind of method of testing of memory component, is applicable to a tester table, and wherein tester table has first memory.The method of testing of this memory component comprises the following steps.At first, judge whether memory component to be measured has unnecessary pin under a test pattern.If change the pin configuration relevant with the address of memory component to be measured.Then, according to the pin configuration after changing, address taking-up data corresponding in memory component to be measured are tested.Wherein, the size of first memory is less than the size of storage unit to be measured.
The present invention also provides a kind of method of testing of memory component, is applicable to a tester table, and wherein tester table has first memory.The method of testing of this memory component comprises the following steps: to judge whether memory component to be measured has unnecessary pin under a test pattern; If change the pin relevant and dispose, and according to the pin configuration after changing, address taking-up data corresponding in memory component to be measured are tested with the address of memory component to be measured; Otherwise the size of the size of foundation memory component to be measured and the first memory of tester table produces N test sample book, and utilizes N test sample book in regular turn, and memory component to be measured is tested.Wherein, memory component to be measured be of a size of tester table first memory size N doubly, and N＞1.
For above-mentioned and other purposes of the present invention, feature and advantage can be become apparent, cited below particularlyly go out preferred embodiment, and cooperate appended graphicly, be described in detail below.
Description of drawings
Fig. 1 is the synoptic diagram that known test system is shown.
Fig. 2 is the process flow diagram that illustrates according to the method for testing of the memory component of the embodiment of the invention.
Fig. 3 illustrates another process flow diagram according to the method for testing of the memory component of the embodiment of the invention.
Fig. 4 illustrates another process flow diagram according to the method for testing of the memory component of the embodiment of the invention.
Fig. 5 A is the synoptic diagram that illustrates according to the address error memory of the embodiment of the invention.
Fig. 5 B illustrates another synoptic diagram according to the address error memory of the embodiment of the invention.
Fig. 5 C is that the pin that illustrates according to the embodiment of the invention changes synoptic diagram.
[main description of reference numerals]
100～test macro
110～memory component to be measured
120～tester table
130～computer installation
S210-S260～step
S310-S340～step
S410-S460～step
500,510～address error memory
BANK0-BANK3～memory block
520,530～address pin
Embodiment
Embodiments of the invention are the method for testings about memory component (for example DRAM), be applicable to a tester table, has storer (for example address error memory) in this tester table, wherein, can be in the tester table in order to the size of the storer of record less than the size of the required record of memory component.Herein, the size of the required record of memory component can comprise the size of the required record of whole memory component or the memory component size corresponding to the required record of block to be measured of board, and wherein each memory component can be divided into a plurality of blocks to be measured.In an embodiment, the test pattern of memory component comprises at least once needs to provide simultaneously 8 outputs to go into 8 bit test patterns of signal (64*8), and once needs to provide simultaneously 16 outputs to go into 16 bit test patterns of signal (32*16).At memory component is to test with 8 bits or 16 bit test patterns, and different method of testings is arranged.According to the embodiment of the invention, if memory component is in a certain test pattern following time, can produce unnecessary pin is not used, then can utilize the method that changes pin configuration (pin assignment), skip and do not have the blank memory of store data block, only the memory block (memory bank) that includes data content in the memory component is configured in the storer of tester table, so, but just the use test board has the memory component more bigger than the memory-size of tester table with test.In another embodiment, no matter memory component can or can not produce unnecessary pin in test pattern following time, can be according to the corresponding relation of the memory-size and the memory component size of tester table, memory component is divided into N memory block (bank), produces the test sample book (test pattern) of corresponding each memory block more respectively.Then, carry out these test sample books in regular turn, so that memory component to be measured is tested.At last, reexamine the test result of each test sample book, learn the integrated testability result of memory component to be measured.By the method for above-mentioned change pin configuration and the method that memory fragmentation is tested, can effectively solve the situation of the storer deficiency of tester table, therefore can test the memory component of large-size (for example 512 megabit units) with tester table, can significantly reduce cost required when testing with less memory-size (for example 256 megabit units).
Fig. 2 is the process flow diagram that illustrates according to the method for testing 200 of the memory component of the embodiment of the invention, be applicable to a tester table, wherein tester table has the address error memory, when testing in order to storage, and the wrong address that on memory component to be measured, is found.The method of testing that note that memory component herein is applicable to various test patterns.As shown in the figure, at step S210, provide earlier a memory component to be measured for example DRAM to tester table.Then, at step S220, tester table is divided into N memory block according to the size of the address error memory of memory component to be measured and tester table with memory component to be measured.For instance, when if the address error memory that memory component to be measured is of a size of 512 megabit units and tester table is of a size of 256 megabits unit, then memory component to be measured can be divided into two independently memory block (N=512M/256M=2) M1 and M2, and the size of each block equals the size of the address error memory of tester table just, that is, 256 megabit units.Afterwards, at step S230, respectively above-mentioned two memory block M1 and M2 are produced two test sample book T1 and T2, wherein test sample book T1 and T2 correspond to the test of memory block M1 and M2 respectively.At step S240, utilize two test sample books in regular turn, memory component to be measured is tested.In other words, utilize test sample book T1 to test the memory block M1 after, utilize test sample book T2 to test memory block M2 again.At step S250, store a test result of each test sample book.For instance, the test result R1 of test sample book T1 and T2 and R2 are stored to a temporary storage location respectively for example in the archives.Secondly, at step S260, the test result R1 of checkout sample T1 and T2 and R2 are to obtain the integrated testability result of memory component to be measured.Wherein, test result R1 and R2 can form a wrong bit figure, judge for follow-up processing.
In this embodiment, be divided into several quantum memory sections owing to have the memory component of large-size, and the size of each block is less than or equal to the size of the address error memory of tester table, for each section, the address error memory of tester table can be in order to store complete test result.Then, the test result of each section is stored respectively, just can observe the complete test result that these test results are learnt whole memory component.Thus, when the size of memory component to be measured becomes big again,, just can on existing tester table, test as long as change the number of segmentation.For instance, if the size of memory component to be measured becomes 1024 megabit units, and the address error memory of tester table as long as change the number N of segmentation into 4, utilizes above-mentioned method of testing to test when being of a size of 256 megabits unit again.Therefore, can solve the problem of the address error memory deficiency of tester table, make tester table can be used for the test of the memory component of more sizes.
It should be noted that, in part embodiment, board to be measured may be in order to test several memory components to be measured simultaneously, and memory component to be measured will be divided into a plurality of blocks to be measured according to the characteristic of board, at this moment, can the address error memory be carried out segmentation, to test according to the size of the required record of each block to be measured.
As previously mentioned, because memory component has various test pattern, for example 8 bits or 16 bit test patterns according to its element characteristic.In order to meet specific specification standards, under some test pattern, partly pin can be retained and not have a storage data.For instance, the general JEDEC standard of organizing JEDEC to formulate by the storer industrial standard of all observing when memory component is made, defined in the JEDEC standard when memory component when 16 bits are exported into pattern, address pin A13 needs to keep (A13 is made as " 0 ") usefulness to following expansion, so in fact the pairing storage space of address pin A13 can't be used.These unnecessary pins make memory component have the blank block of discontinuous no datat and the block that data are arranged.With existing test mode, these blank blocks also can be stored in the address error memory of tester table in the lump.A kind of method of testing of improvement is just proposed at this characteristic therefore.
Fig. 3 illustrates another process flow diagram according to the method for testing 300 of the memory component of the embodiment of the invention.In the present embodiment, suppose that memory component to be measured meets the JEDEC standard, therefore when 16 bits were exported into pattern, address pin A13 was the pin of unnecessary (reservation).At step S310, change the pin setting relevant with the address of memory component to be measured, replace unnecessary pin position with other corresponding pins.Then, at step S320, skip over the blank block that is distributed in the memory component to be measured.Because the pin that address is relevant is provided with change, make the blank block of memory block of memory component can when test, not be addressed to or read, so these blank blocks will be skipped over.Then, at step S330, discontinuously arranged block is read continuously and tested.Afterwards, at step S340, with the test result continuity of block be stored in the address error memory of tester table.
For instance, please refer to Fig. 5 A and Fig. 5 B.Fig. 5 A illustrates the synoptic diagram of known address error memory content 500, and Fig. 5 B illustrates the synoptic diagram according to the address error memory content 510 of the embodiment of the invention.In this example, as previously mentioned, memory component to be measured meets the JEDEC standard, that is address pin A13 is unnecessary pin.Therefore the pairing memory block of address pin A13 will form the blank block of no datat.Shown in Fig. 5 A, the address space of address error memory is from 0000H to FFFFH, address 0000H～1FFFH, 4000H～5FFFH, 8000H～9FFFH and C000H～DFFFH have stored the test result of block BANK0, BANK1, BANK2 and the BANK3 of memory component to be measured respectively, and the pairing address space 2000H～3FFFH of address pin A13,6000H～7FFFH, A000H～BFFFH and E000H～FFFFH have then stored the blank block N of memory component to be measured.Therefore, can change the pin configuration according to the method for testing 300 of the embodiment of the invention, A13 replaces with A14 with address, and other pins are then adjusted in regular turn, shown in Fig. 5 C.The pin that Fig. 5 C illustrates according to the embodiment of the invention changes synoptic diagram.As shown in the figure, new address pin configuration 530 is changed in original address pin configuration 520, and A14 changes to A13 with the address pin, and the position of the address pin A14 that sky falls is then filled vacancies in the proper order by next address pin A15, and therefore becoming A15 is unnecessary pin.So, when tester table tests the memory block BANK0 of memory component to be measured and stores test results after the address error memory, owing to change the influence of address pin configuration, N will be skipped between the clear area of original pairing 2000H-3FFFH of address pin A13, directly then memory block BANK1 is afterwards tested, and stores test results is in the address error memory.Therefore, shown in Fig. 5 B, in the address error memory of tester table continuously the test result of storing memory block BANK0-BANK3 among memory block 0000H-7FFFH continuously, the address 8000H-FFFFH of address error memory then forms a remaining memory block, be next to after the connected storage block, can be used to store other test result and information.When the size of memory component to be measured becomes big, for example become original twice, i.e. 8 memory block BANK0-BANK7, can utilize the method for testing of the embodiment of the invention, the test result of memory block BANK4-BANK7 is stored within the remaining memory block 8000H-FFFFH of address error memory of tester table, therefore can be under the condition of the address error memory undergage of tester table, still can test the memory component of some large-size, can obtain more complete test result, and reduce the cost of test.
In addition, also can effectively according to the test characteristic of memory component to be measured, select for use suitable method of testing in conjunction with above-mentioned method of testing 200 and 300 to promote the effect of test.Please be simultaneously with reference to Fig. 2 and Fig. 4.Fig. 4 illustrates another process flow diagram according to the method for testing 400 of the memory component of the embodiment of the invention.In the present embodiment, suppose to be divided into 8 bits and the test of 16 bits, and meet the JEDEC standard in memory component.At step S410, judge earlier memory component to be measured is at which kind of test pattern.If memory component to be measured is under 8 bit test patterns, then follow execution in step S450, the size of the size of the required record of foundation memory component to be measured and the address error memory of tester table is divided into N memory block with memory component to be measured.Then, at step S460, carry out the step of S230 to S260 again, that is respectively above-mentioned N memory block produced N test sample book, utilizes N test sample book in regular turn, a test result of each test sample book and the test result of checking each test sample book are tested, stored to memory component to be measured, to obtain the integrated testability result of memory component to be measured.Because step S450-S460 is similar to step S220-S260 shown in Figure 2, can be with reference to the related description of figure 2, its details is omitted at this.
If judging memory component to be measured at step S410 is under 16 bit test patterns, then follow execution in step S420, judge whether that memory component to be measured has a unnecessary pin.(step S420 denys) if not, expression does not have unnecessary pin, just use the method for memory component segmentation to be measured is tested, as step S450-S460.(if step S420 is), at step S430, the pin according to unnecessary changes the pin setting relevant with the address of memory component to be measured.In this example, address pin A13 is unnecessary pin, therefore the position that address A15 is changed to A14 and address pin A14 is changed to A13.At step S440, according to the pin configuration after changing, address taking-up data corresponding in memory component to be measured are tested.Step S440 is similar to step S320-S340, therefore tester table will skip over the blank block that is distributed in the memory component to be measured, discontinuously arranged block is read continuously and is tested, again with the test result continuity of block be stored in the address error memory of tester table.Therefore, can under the condition of the address error memory undergage of tester table, test the memory component of some large-size, can obtain more complete test result, and reduce the cost of test.
Above-mentioned explanation provides several different embodiment or uses distinct methods of the present invention.Specific device in the example and method the invention is not restricted to this certainly in order to help explaination main spirit of the present invention and purpose.
Therefore; though the present invention discloses as above with preferred embodiment; right its is not in order to limit the present invention; any those of ordinary skills; without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention is as the criterion when looking appended the claim number person of defining.
Claims (21)
1. the method for testing of a memory component is applicable to a tester table, and wherein this tester table has first memory, and the method for testing of this memory component comprises the following steps:
Memory component to be measured is provided;
Size according to this first memory of the size of this memory component to be measured and this tester table produces N test sample book, and wherein this memory component to be measured is of a size of N times of size of this first memory of this tester table, and N＞1; And
Utilize this N test sample book in regular turn, this memory component to be measured is tested.
2. the method for testing of memory component as claimed in claim 1, wherein said this N test sample book of utilizing in regular turn, the step that this memory component to be measured is tested also comprises:
According to the size of this first memory, should be divided into N memory block by memory component to be measured, and each this N memory block corresponds to one in this N test sample book.
3. the method for testing of memory component as claimed in claim 2, wherein each this N memory block corresponds to a Stand Alone Memory space of this memory component to be measured, and the size in this Stand Alone Memory space equals the size of this first memory.
4. the method for testing of memory component as claimed in claim 1, wherein said this N test sample book of utilizing in regular turn, the step that this memory component to be measured is tested also comprises:
Store a test result of each this N test sample book; And
Utilize described test result, obtain the test result of this memory component to be measured.
5. the method for testing of memory component as claimed in claim 4, wherein this test result forms wrong bit figure.
6. the method for testing of memory component as claimed in claim 1, wherein this first memory is the address error memory, in order to store the wrong address of this memory component to be measured.
7. the method for testing of memory component as claimed in claim 1, wherein this memory component to be measured comprises dynamic RAM.
8. the method for testing of memory component as claimed in claim 1, wherein this memory component to be measured meets storer industrial standard organizational standard.
9. the method for testing of a memory component is applicable to a tester table, and wherein this tester table has first memory, and the method for testing of this memory component comprises the following steps:
Change the pin configuration relevant with the address of memory component to be measured, wherein this memory component to be measured has blank block and a plurality of block of a plurality of no datat, and described blank block and block are distributed in this memory component to be measured discontinuously; And
Skip over the described blank block that is distributed in this memory component to be measured, so that discontinuously arranged described block is read continuously and is tested, and with the test result continuity of described block be stored in this first memory,
Wherein the size of this first memory is less than the size of this storage unit to be measured.
10. the method for testing of memory component as claimed in claim 9, wherein this memory component to be measured comprises unnecessary pin, and the described change pin configuration relevant with the address of this memory component to be measured is relevant with this unnecessary pin.
11. the method for testing of memory component as claimed in claim 9 also comprises:
Utilize a remaining memory block of this first memory to test, wherein this remaining memory block is next to after the connected storage block of this first memory.
12. the method for testing of memory component as claimed in claim 9 also comprises:
Utilize the test result of this memory component to be measured, form wrong bit figure.
13. the method for testing of memory component as claimed in claim 9, wherein this first memory is the address error memory, when carrying out this test in order to storage, and the wrong address that on this memory component to be measured, is found.
14. the method for testing of memory component as claimed in claim 9, wherein this memory component to be measured comprises dynamic RAM.
15. the method for testing of memory component as claimed in claim 9, wherein this memory component to be measured meets storer industrial standard organizational standard.
16. the method for testing of a memory component is applicable to a tester table, wherein this tester table has first memory, and the method for testing of this memory component comprises the following steps:
Judge whether memory component to be measured has unnecessary pin under a test pattern;
If change the pin configuration relevant with the address of this memory component to be measured; And
According to the pin configuration after changing, corresponding address taking-up data are tested in this memory component to be measured certainly,
Wherein the size of this first memory is less than the size of this storage unit to be measured.
17. the method for testing of memory component as claimed in claim 16, wherein this test pattern comprises the test of 8 bits and 16 bits.
18. the method for testing of memory component as claimed in claim 16, wherein this test pattern also comprises first test pattern and second test pattern, and this memory component to be measured has unnecessary pin under this first test pattern, the method for testing of this memory component also comprises the following steps:
Under this first test pattern, change the pin relevant and dispose, and according to the pin configuration after changing, corresponding address taking-up data are tested in this memory component to be measured certainly with the address of this memory component to be measured; And
Under this second test pattern, the size of the size of this memory component to be measured of foundation and this first memory of this tester table, produce N test sample book, and utilize this N test sample book in regular turn, this memory component to be measured is tested, wherein this memory component to be measured be of a size of this tester table this first memory size N doubly, and N＞1.
19. the method for testing of memory component as claimed in claim 16, wherein this memory component to be measured comprises the dynamic RAM that meets storer industrial standard organizational standard.
20. the method for testing of a memory component is applicable to a tester table, wherein this tester table has first memory, and the method for testing of this memory component comprises the following steps:
Judge whether memory component to be measured has unnecessary pin under a test pattern;
If change the pin relevant and dispose, and according to the pin configuration after changing, corresponding address taking-up data are tested in this memory component to be measured certainly with the address of this memory component to be measured; And
If this memory component to be measured does not have unnecessary pin under this test pattern, the size of the size of this memory component to be measured of foundation and this first memory of this tester table produces N test sample book, and utilizes this N test sample book in regular turn, this memory component to be measured is tested
Wherein this memory component to be measured be of a size of this tester table this first memory size N doubly, and N＞1.
21. the method for testing of memory component as claimed in claim 20, wherein this test pattern also comprises the test pattern of 8 bits and 16 bits, and the method for testing of this memory component also comprises the following steps:
Under the test pattern of this 16 bit, change the pin relevant and dispose, and according to the pin configuration after changing, corresponding address taking-up data are tested in this memory component to be measured certainly with the address of this memory component to be measured; And
Under the test pattern of this 8 bit, the size of the size of this memory component to be measured of foundation and this first memory of this tester table produces N test sample book, and utilizes this N test sample book in regular turn, and this memory component to be measured is tested.
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| CNA2007101283741A CN101345090A (en) | 2007-07-10 | 2007-07-10 | Memory element test method |
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Open date: 20090114 |