CN101335239A - Image sensor and method for fabricating the same - Google Patents
Image sensor and method for fabricating the same Download PDFInfo
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- CN101335239A CN101335239A CNA2008101278201A CN200810127820A CN101335239A CN 101335239 A CN101335239 A CN 101335239A CN A2008101278201 A CNA2008101278201 A CN A2008101278201A CN 200810127820 A CN200810127820 A CN 200810127820A CN 101335239 A CN101335239 A CN 101335239A
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- 238000009792 diffusion process Methods 0.000 claims abstract description 39
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- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 5
- 230000008021 deposition Effects 0.000 claims description 5
- 229910052759 nickel Inorganic materials 0.000 claims description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 4
- 229920005591 polysilicon Polymers 0.000 claims description 4
- 239000005368 silicate glass Substances 0.000 claims description 4
- 238000001259 photo etching Methods 0.000 claims description 3
- 239000010936 titanium Substances 0.000 claims description 3
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14609—Pixel-elements with integrated switching, control, storage or amplification elements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
- H01L27/14689—MOS based technologies
Abstract
The invention discloses an image sensor and a method for fabricating the same. The method may include forming a gate, a photo diode, and a floating diffusion region on a pixel region of a semiconductor substrate; forming an oxide film on the pixel region and on an edge region of the semiconductor substrate; forming a sacrificial oxide layer by etching the oxide film using a photoresist pattern as a mask; forming a metal layer on the photoresist pattern, the gate, and the floating diffusion region; forming a salicide layer on the gate and the floating diffusion region; etching a remaining non-salicided portion of the metal layer, the photoresist pattern, and at least a portion of the sacrificial oxide layer; and forming an interlayer insulating film on the semiconductor substrate and planarizing the interlayer insulating film.
Description
The application requires the priority of the korean patent application submitted on June 25th, 2007 10-2007-0062163 number, and its full content is hereby expressly incorporated by reference.
Technical field
The present invention relates to a kind of semiconductor element, more particularly, relate to a kind of cmos image sensor and manufacture method thereof.
Background technology
A kind of as imageing sensor, cmos image sensor is a kind of element of the CMOS of use technology, it uses control circuit and signal processing circuit as peripheral circuit.
The method of making cmos image sensor has used self aligned polycide technology (salicide process) to reduce the active area on the pixel region and the impedance of grid.The metal film that is applied to self aligned polycide technology has the highly reflective to light, and it is formed on the active area except that photodiode.Especially, except that pixel region, self aligned polycide film (salicide film) also can be formed on the marginal zone of Semiconductor substrate.
The self aligned polycide film that is formed on the marginal zone of Semiconductor substrate has very low bonding strength to insulating barrier, thereby can produce the dielectric film particulate in the follow-up flatening process of dielectric film.
Summary of the invention
Therefore, the present invention proposes a kind of imageing sensor and manufacture method thereof.
An object of the present invention is to provide a kind of imageing sensor and manufacture method thereof, this imageing sensor has improved the bonding strength between Semiconductor substrate and the insulating barrier.
In order to realize these purposes with other advantages and according to purpose of the present invention, as giving an example in this article and institute's general description, a kind of imageing sensor comprises the Semiconductor substrate with pixel region and marginal zone; Be formed at the grid on the Semiconductor substrate in the pixel region; Be formed at the photodiode on the Semiconductor substrate of grid one side; Be formed at the floating diffusion region on the semiconductor of grid opposite side; Be formed at the self aligned polycide layer on grid and the floating diffusion region; Be formed in the pixel region and the interlayer dielectric on the Semiconductor substrate in the marginal zone, this pixel region has photodiode and has the grid and the floating diffusion region of the self aligned polycide layer that forms thereon, and wherein the surface of the Semiconductor substrate in the pixel region is not by autoregistration multi-crystal silicification (non-salicided).This imageing sensor can further comprise rim openings part (edge open part), thereby comes the part in exposed edge district to make this rim openings partly expose the Semiconductor substrate that is equivalent to the marginal zone part by forming interlayer dielectric.This imageing sensor can further comprise sacrificial oxidation film (sacrificial oxide film), and it is formed on the Semiconductor substrate and the interlayer dielectric in the marginal zone in the marginal zone.
Another aspect of the present invention, the method for shop drawings image-position sensor are included on the pixel region of Semiconductor substrate and form grid; Side at grid forms photodiode, and forms floating diffusion region at the opposite side of grid; Form oxide-film on the pixel region of Semiconductor substrate and marginal zone, wherein pixel region has grid, photodiode, floating diffusion region; Formation has the photoresist pattern of opening, and it is corresponding to the floating diffusion region on grid and the oxide-film, and making with photoresist then, pattern comes the etching oxidation film to form sacrificial oxide layer as mask; At the photoresist pattern, form metal level on grid and the floating diffusion region; On grid and floating diffusion region, form the self aligned polycide layer by implementing rapid thermal treatment (rapid thermal processing); Metal remained layer, photoresist pattern and sacrificial oxide layer after the etching rapid thermal treatment form interlayer dielectric then and this interlayer dielectric are carried out planarization.
Be understandable that above-mentioned describe, in general terms of the present invention and following specific descriptions all are exemplary with illustrative, and are in order to provide desired further explanation of the present invention.
Description of drawings
Accompanying drawing (it is involved to be used to provide a further understanding of the present invention and the part that is integrated into and is configured to the application), exemplary embodiment of the present invention and specification have been set forth principle of the present invention.In the accompanying drawings:
Fig. 1 to 8 shows the cross-sectional view that is used for the technology of shop drawings image-position sensor according to the specific embodiment of the present invention.
Embodiment
To describe in detail preferred embodiment of the present invention and embodiment illustrated in the accompanying drawings now.
Be understandable that when such as layer, the element of district or substrate refers to when another element " on/top ", can directly maybe may also there be intermediary element in this element on another element.
In the accompanying drawings,, will amplify, omit or schematically illustrate the thickness or the size of each layer for illustrated convenience or clear.Each size of component is not represented its real size.
Fig. 8 shows the cross-sectional view according to the imageing sensor of the specific embodiment of the invention.
With reference to figure 8, each comprises that all the unit pixel of photodiode 30 is deposited on the Semiconductor substrate 10.The part of Semiconductor substrate 10 is called pixel region (A), formed the element such as unit pixel in part, and other parts of Semiconductor substrate 10 is called marginal zone (B), is formed for the laser labelling to the semiconductor element classification in these other parts.By element-isolating film 20 pixel region (A) and marginal zone (B) are kept apart mutually.
Go up the transistorized grid 40 of photodiode placed 30 and formation unit pixel at pixel region (A).Although do not illustrate in Fig. 8, transistor can be transfering transistor, reset transistor, driving transistors or select transistor.
The interlayer dielectric 80 that is used for lead and element mutually insulated is deposited on pixel region (A) and marginal zone (B) that comprises unit pixel.Contact plug 95 and 97 is deposited in the interlayer dielectric on the pixel region (A), and is electrically connected with grid 40 and floating diffusion region 35.
Optionally remove the interlayer dielectric 80 on the marginal zone (B), thereby form rim openings part 15.Edge by rim openings part 15 exposed edge districts (B).For example, rim openings part 15 has the width of 1.0mm to 2.0mm, has exposed the laser labelling that is formed on the marginal zone (B).
Below with reference to Fig. 1 to 8, the method for shop drawings image-position sensor will be described according to the specific embodiment of the present invention.
As shown in fig. 1, the part of Semiconductor substrate 10 is called pixel region (A), formed the element such as unit pixel in this part, and the marginal portion of Semiconductor substrate 10 is called marginal zone (B), does not form element in this part.
Go up to form element-isolating film 20 at pixel region (A), it is used to be limited with source region and field region and unit pixel is isolated mutually.
(B) goes up and forms laser labelling in the marginal zone, and it is classified to semiconductor element according to chip (chips).Go up the grid that forms photodiode 30 and form the transistor circuit of unit pixel at pixel region (A).
Grid comprises gate insulating film 37, gate electrode 40 and gate spacer (gate spacer) 50.For example, by going up formation oxide-film and polysilicon film at pixel region (A) and coming this oxide-film of one patterned and polysilicon film, form gate insulating film 37 and gate electrode 40 by photoetching process and etch process.By going up the deposition dielectric film and finish recess process, on the sidewall of gate insulating film 37 and gate electrode 40, form gate spacer 50 at pixel region (A) with gate insulating film 37 and grid 40.At this moment, grid can be the grid of the transfering transistor of adjacent photodiode 30.
Photodiode 30 is deposited on a side of grid, and floating diffusion region 35 is deposited on the opposite side of this grid.
The p-type district that photodiode 30 is included in the n-type district of grid one side and has the little degree of depth in n-type district.
Form with spacer 50 that two sidewalls of grid all contact after, by use gate electrode 40 and as the spacer 50 of ion injecting mask at spacer 50 places of grid opposite side arrangement floating diffusion region 35.
On the Semiconductor substrate 10 that comprises pixel region (A) and marginal zone (B), form sacrificial oxidation film 60.For example, form this sacrificial oxidation film 60 by thermal oxidation process.
As shown in Figure 2, photodiode 30 and marginal zone (B) at pixel region (A) goes up the formation sacrificial oxide layer 65 and the first photoresist pattern 100.
Formation sacrificial oxide layer 65 as described below.
At first, form the first photoresist pattern 100 on sacrificial oxidation film 60, this first photoresist pattern exposes and floating diffusion region 35 corresponding a part of sacrificial oxidation film 60.For example, the first photoresist pattern 100 has exposed the top of grid, the spacer 50 of this grid opposite side and floating diffusion region 35, and do not expose other parts.
Then, use the first photoresist pattern 100 to come etch sacrificial oxide-film 60, thereby expose floating diffusion region 35 as etching mask.
Like this, go up formation sacrificial oxide layer 65 at photodiode 30 and marginal zone (B) of pixel region (A), this sacrificial oxide layer exposes the grid and the floating diffusion region 35 of pixel region (A).Therefore, make photodiode 30 and marginal zone (B) not by the autoregistration multi-crystal silicification by the sacrificial oxide layer in the self aligned polycide technology 65.
As shown in Figure 3, metal level 70 is formed on the Semiconductor substrate 10, has formed the sacrificial oxide layer 65 and the first photoresist pattern 100 on this Semiconductor substrate.Can have the metal of conductivity by deposition, form this metal level 70 such as cobalt, nickel or titanium.For example, use the physical vapor deposition (PVD) method to come deposit cobalt to form metal level 70.
Go up formation metal level 70 at the pixel region that comprises first photoresist 100 (A) and marginal zone (B).That is to say that metal level 70 is formed on first photoresist 100 and grid and the floating diffusion region 35, wherein first photoresist is formed on pixel region (A) and marginal zone (B), and floating diffusion region is exposed by sacrificial oxide layer 65.
Form the self aligned polycide layer by the rapid thermal treatment (hereinafter referred to as ' RTP ') of finishing metal level 70.For example, under 300 ℃ to 1000 ℃ temperature, carry out RTP.
By RTP, gate electrode 40 and floating diffusion region 35 interacts with metal level 70, thus by the autoregistration multi-crystal silicification, marginal zone (B) by sacrificial oxide layer 65 and the first photoresist pattern 100 not by the autoregistration multi-crystal silicification.
Next, as shown in Figure 4, when removing the first photoresist pattern 100 and sacrificial oxide layer 65, self aligned polycide layer 75 and 77 is formed at respectively on gate electrode 40 and the floating diffusion region 35.
The metal level 70 that forms on photodiode 30 and marginal zone (B) is removed together with the removal of first photoresist 100 or sacrificial oxide layer 65.
Therefore, the surface of photodiode 30 and marginal zone (B) is exposed on the outside.At this moment, sacrificial oxide layer 65 is not done and removes, and possible part is residual.
Because the sacrificial oxide layer 65 and the first photoresist pattern 100 make photodiode 30 not by the autoregistration multi-crystal silicification, this makes the photosensitivity that improves imageing sensor become possibility.
In addition, because sacrificial oxide layer 65 and the first photoresist pattern 100 make marginal zone (B) not by the autoregistration multi-crystal silicification, this makes the bonding strength that improves marginal zone (B) and be formed on the interlayer dielectric 80 on the marginal zone (B) become possibility.In addition, by keeping the method for sacrificial oxide layer 65, make the bonding strength that improves marginal zone (B) and interlayer dielectric 80 better become possibility.
As shown in Figure 5, interlayer dielectric 80 is formed on pixel region (A) and marginal zone (B), and forms the second photoresist pattern 200 by photoetching process on interlayer dielectric 80.
Interlayer dielectric 80 is formed on the Semiconductor substrate 10 that comprises pixel region (A) and marginal zone (B).For example, this interlayer dielectric 80 is a kind of dielectric films, and it comprises at least a in boron phosphorus silicate glass (BPSG) and the plain silicate glass (USG).Interlayer dielectric is after 80s forming, and carries out planarization.For example, carry out the planarization of interlayer dielectric 80 by chemico-mechanical polishing (CMP).
Because the interlayer dielectric 80 on the marginal zone (B) is formed on the non-autoregistration multi-crystal silicification part of Semiconductor substrate 10, has improved the bonding strength of interlayer dielectric 80 with Semiconductor substrate 10.Especially, by remaining in the sacrificial oxide layer 65 on the Semiconductor substrate 10, improved the bonding strength between Semiconductor substrate 10 and the interlayer dielectric 80.
In follow-up CMP technology, the raising of the bonding strength between interlayer dielectric 80 and marginal zone (B) has reduced the stress of interlayer dielectric 80.Thereby, can MINly reduce the generation of dielectric film particulate, this dielectric film particulate such as circular flaw (circledefect) are caused by the degeneration of the bonding strength between interlayer dielectric 80 and marginal zone (B).
Under the particulate of dielectric film such as circular flaw drop on situation on the contact hole, when follow-up formation contact plug, can produce defective such as pore.In the specific embodiment of the present invention, the bonding strength between interlayer dielectric 80 and marginal zone (B) is improved, thereby has prevented the generation of dielectric film particulate.Therefore, improved the reliability of semiconductor element.
The one patterned second photoresist pattern 200 is to have first opening, 210, the second openings 220 and the 3rd opening 215.For example, the second photoresist pattern 200 is carried out first time one patterned to have first opening 210 and second opening 220, and wherein first opening 210 has exposed corresponding to the surface of the part interlayer dielectric 80 of gate electrode 40 and second opening 220 has exposed the surface corresponding to other part interlayer dielectrics 80 of floating diffusion region 35.
Then, as shown in Figure 6, form the 3rd opening 215 by optionally removing the second photoresist pattern 200.The 3rd opening 215 of this second photoresist pattern 200 has exposed the surface corresponding to other parts of the interlayer dielectric 80 of part edge district (B).For example, the 3rd opening 215 has the diameter of 1.0mm to 2.0mm.Form the 3rd opening 215 by exposing corresponding to the part second photoresist pattern 200 at the edge of marginal zone (B) and using solvent to remove this part second photoresist pattern 200.
As shown in Figure 7, the second photoresist pattern 200 that use has first to the 3rd opening 210,220 and 215 comes etching interlayer dielectric 80 to form the contact hole 85 that exposes gate electrode 40 and floating diffusion region 35 respectively and 87 and the rim openings part 15 at edge, exposed edge district (B) as etching mask.
Be exposed to the self aligned polycide layer 75 and 77 that forms on gate electrode 40 and the floating diffusion region 35 by contact hole 85 and 87.In addition, remove corresponding to this part interlayer dielectric 80 of marginal zone (B) so that the edge of (B) forms rim openings part 15 in the marginal zone by the second photoresist pattern 200.
For example, the rim openings part 15 on marginal zone (B) has the width of 1.0mm to 2.0mm.The edge of marginal zone (B) is exposed so that can confirm that (B) goes up the laser labelling that forms in the marginal zone.
As shown in Figure 8, contact plug 95 and 97 is formed in the contact hole 85 and 87 of interlayer dielectric 80. Contact hole 85 and 87 with metal filled interlayer dielectric 80 carries out planarization formation contact plug 95 and 97 then.For example, filling contact hole 85 and 87 metal are tungsten.
When being used to form the metal deposition of contact plug 95 and 97, the rim openings part 15 of marginal zone (B) is filled metal.Can remove the metal of filling rim openings part 15 by the CMP technology of metal.Therefore, the rim openings part by marginal zone (B) 15 exposes and is used for laser labelling that semiconductor element is classified.
Know by foregoing description, the invention provides a kind of imageing sensor and manufacture method thereof, wherein the marginal zone of Semiconductor substrate and the bonding strength between the interlayer dielectric are improved.
In addition, when carrying out the CMP technology of interlayer dielectric, the stress that is added on the interlayer dielectric is minimized, thereby has prevented the generation of dielectric film particulate.
In addition, the photoresist film that is used to form the contact hole that passes interlayer dielectric is carried out one patterned removing the part interlayer dielectric that forms on the marginal zone, thereby the laser labelling that forms on the marginal zone can be identified.
Can do various modifications and distortion without departing from the spirit and scope of the present invention, this is conspicuous for a person skilled in the art.Therefore, the present invention covered claim and be equal to provide in the replacement to modification of the present invention and change.
Claims (20)
1. the method for a shop drawings image-position sensor comprises:
On the pixel region of Semiconductor substrate, form grid;
Side at described grid forms photodiode, and forms floating diffusion region at the opposite side of described grid;
Form oxide-film on the described pixel region of described Semiconductor substrate and marginal zone, described pixel region is provided with described grid, described photodiode and described floating diffusion region;
Form the photoresist pattern, described photoresist pattern has corresponding to the described grid on the described oxide-film and the opening of described floating diffusion region, uses described photoresist pattern to come the described oxide-film of etching to form sacrificial oxide layer as mask then;
On described photoresist pattern, described grid and described floating diffusion region, form metal level;
On described grid and described floating diffusion region, form the self aligned polycide layer by carrying out rapid thermal treatment;
Residual described metal level, described photoresist pattern and described sacrificial oxide layer after the described rapid thermal treatment of etching, and form interlayer dielectric and to described interlayer dielectric planarization.
2. method according to claim 1 further comprises by the described interlayer dielectric on the described marginal zone of etching forming the rim openings part that has exposed part Semiconductor substrate in the described marginal zone.
3. method according to claim 1, the described rim openings of wherein said marginal zone partly has the width of 1.0mm to 2.0mm.
4. method according to claim 1, the formation of wherein said grid comprises:
Thereby on described pixel region, form oxide-film and polysilicon film and come described oxide-film of one patterned and described polysilicon film to form gate insulating film and gate electrode by photoetching process and etch process; And
By being provided with on the described pixel region of described gate insulating film and described gate electrode the deposition dielectric film and implementing recess process, thereby on the sidewall of described gate insulating film and described gate electrode, form gate spacer.
5. method according to claim 1, wherein in the formation of described sacrificial oxide layer, described sacrificial oxide layer is formed on described photodiode and the described marginal zone and exposes described grid and described floating diffusion region.
6. method according to claim 1 wherein in the formation of described sacrificial oxide layer, uses thermal oxidation process to form described sacrificial oxide layer.
7. method according to claim 1 wherein in the formation of described metal level, is selected from the group of being made up of cobalt, nickel and titanium any one and forms described metal level by deposition.
8. method according to claim 7 wherein in the formation of described metal level, is selected from the group that cobalt, nickel and titanium form any one by PVD method deposition and forms described metal level.
9. method according to claim 1 wherein in the formation of described self aligned polycide layer, forms described self aligned polycide layer by carry out described rapid thermal treatment under 300 ℃ to 1000 ℃ temperature.
10. method according to claim 4, wherein in the formation of described self aligned polycide layer, by described rapid thermal treatment, described gate electrode and described floating diffusion region and described metal level effect and by the autoregistration multi-crystal silicification, and make described photodiode and described marginal zone not by the autoregistration multi-crystal silicification by described sacrificial oxide layer and described photoresist pattern.
11. method according to claim 1, wherein in the formation and planarization of described interlayer dielectric, described sacrificial oxide layer has not been removed part by etching fully and has been kept.
12. method according to claim 11, wherein in the formation and planarization of described interlayer dielectric, described interlayer dielectric comprises at least a in boron phosphorus silicate glass (BPSG) and the unadulterated silicate glass (USG).
13. method according to claim 10, wherein in the formation and planarization of described interlayer dielectric, described interlayer dielectric is formed on the marginal zone of described non-autoregistration multi-crystal silicification and is flattened.
14. method according to claim 2, the formation of wherein said rim openings part comprises:
On described interlayer dielectric, form another photoresist pattern with first, second and the 3rd opening; And
Use described photoresist pattern to come the described interlayer dielectric of etching to correspond respectively to the contact hole of described grid and described floating diffusion region and form the described rim openings part that exposes described marginal zone with formation as etching mask.
15. method according to claim 2, wherein in the formation of described rim openings part, the described edge of described marginal zone is exposed so that be exposed to the described laser labelling that forms on the described marginal zone.
16. an imageing sensor comprises:
Semiconductor substrate comprises pixel region and marginal zone;
Grid is formed on the described Semiconductor substrate in the described pixel region;
Photodiode is formed on the described Semiconductor substrate of described grid one side;
Floating diffusion region is formed on the described Semiconductor substrate of described grid opposite side;
The self aligned polycide layer is formed on described grid and the described floating diffusion region; And
Interlayer dielectric, be formed in the described pixel region and described marginal zone in described Semiconductor substrate on, described pixel region is provided with described photodiode and described grid and described floating diffusion region, described grid and described floating diffusion region have the self aligned polycide layer that forms thereon
The surface of the described Semiconductor substrate in the wherein said pixel region is non-autoregistration multi-crystal silicification.
17. imageing sensor according to claim 16 further comprises by the interlayer dielectric that form to expose described part edge district exposing rim openings part corresponding to the described Semiconductor substrate in described part edge district.
18. imageing sensor according to claim 17, wherein said rim openings partly have the width of 1.0mm to 2.0mm.
19. imageing sensor according to claim 16 wherein forms described self aligned polycide layer by being selected from least a in the group that cobalt, nickel and titanium form.
20. imageing sensor according to claim 16 further comprises the described Semiconductor substrate that is formed at described marginal zone and the sacrificial oxidation film on the described interlayer dielectric in the described marginal zone.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR10-2007-0062163 | 2007-06-25 | ||
| KR1020070062163 | 2007-06-25 | ||
| KR1020070062163A KR100881016B1 (en) | 2007-06-25 | 2007-06-25 | Method for Manufacturing of Image Sensor |
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| Publication Number | Publication Date |
|---|---|
| CN101335239A true CN101335239A (en) | 2008-12-31 |
| CN101335239B CN101335239B (en) | 2010-09-22 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2008101278201A Expired - Fee Related CN101335239B (en) | 2007-06-25 | 2008-06-25 | Image sensor and method for fabricating the same |
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| Country | Link |
|---|---|
| US (1) | US7897425B2 (en) |
| KR (1) | KR100881016B1 (en) |
| CN (1) | CN101335239B (en) |
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| CN104393010A (en) * | 2014-12-01 | 2015-03-04 | 豪威科技(上海)有限公司 | CMOS (complementary metal oxide semiconductor) image sensor capable of lowering image delay and preparation method of CMOS image sensor capable of lowering image delay |
| CN109585476A (en) * | 2017-09-29 | 2019-04-05 | 台湾积体电路制造股份有限公司 | Cmos image sensor and forming method thereof |
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| US8247262B2 (en) * | 2009-05-04 | 2012-08-21 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for reducing contact resistance of CMOS image sensor |
| US8138531B2 (en) * | 2009-09-17 | 2012-03-20 | International Business Machines Corporation | Structures, design structures and methods of fabricating global shutter pixel sensor cells |
| US8691690B2 (en) * | 2010-09-13 | 2014-04-08 | International Business Machines Corporation | Contact formation method incorporating preventative etch step reducing interlayer dielectric material flake defects |
| CN102569073B (en) * | 2010-12-07 | 2014-11-05 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method of semiconductor apparatus |
| US9093379B2 (en) * | 2013-05-29 | 2015-07-28 | International Business Machines Corporation | Silicidation blocking process using optically sensitive HSQ resist and organic planarizing layer |
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| KR20030002018A (en) * | 2001-06-30 | 2003-01-08 | 주식회사 하이닉스반도체 | Image sensor |
| CN1276306C (en) * | 2002-05-14 | 2006-09-20 | 株式会社东芝 | Processing method, mfg. method and processing device for semiconductor |
| JP4541666B2 (en) * | 2002-06-20 | 2010-09-08 | 三星電子株式会社 | Image sensor and manufacturing method thereof |
| KR100508086B1 (en) * | 2002-09-11 | 2005-08-17 | 삼성전자주식회사 | Cmos image sensor and method of fabricating the same |
| US7071505B2 (en) * | 2003-06-16 | 2006-07-04 | Micron Technology, Inc. | Method and apparatus for reducing imager floating diffusion leakage |
| KR100595899B1 (en) * | 2003-12-31 | 2006-06-30 | 동부일렉트로닉스 주식회사 | Image sensor and method for fabricating the same |
| KR20060020395A (en) * | 2004-08-31 | 2006-03-06 | 매그나칩 반도체 유한회사 | Fabricating method of cmos image sensor |
| CN100389498C (en) * | 2005-06-07 | 2008-05-21 | 中芯国际集成电路制造(上海)有限公司 | Method for preparing complementary metal oxide image sensor-mixed silicide |
| KR100720474B1 (en) * | 2005-06-17 | 2007-05-22 | 동부일렉트로닉스 주식회사 | CMOS Image sensor and Method for fabricating of the same |
| KR100672729B1 (en) * | 2005-07-14 | 2007-01-24 | 동부일렉트로닉스 주식회사 | Method for manufacturing of CMMS image sensor |
| JP2007027311A (en) | 2005-07-14 | 2007-02-01 | Matsushita Electric Ind Co Ltd | Solid-sate imaging apparatus, its manufacturing method and camera using same |
| JP2008177306A (en) * | 2007-01-17 | 2008-07-31 | Matsushita Electric Ind Co Ltd | Solid-state imaging device |
| KR100904589B1 (en) * | 2007-06-25 | 2009-06-25 | 주식회사 동부하이텍 | Method for Manufacturing of Image Sensor |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104393010A (en) * | 2014-12-01 | 2015-03-04 | 豪威科技(上海)有限公司 | CMOS (complementary metal oxide semiconductor) image sensor capable of lowering image delay and preparation method of CMOS image sensor capable of lowering image delay |
| CN104393010B (en) * | 2014-12-01 | 2017-09-05 | 豪威科技(上海)有限公司 | Reduce cmos image sensor of picture delay and preparation method thereof |
| CN109585476A (en) * | 2017-09-29 | 2019-04-05 | 台湾积体电路制造股份有限公司 | Cmos image sensor and forming method thereof |
| CN109585476B (en) * | 2017-09-29 | 2021-03-30 | 台湾积体电路制造股份有限公司 | CMOS image sensor and method for forming the same |
Also Published As
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| US7897425B2 (en) | 2011-03-01 |
| KR100881016B1 (en) | 2009-01-30 |
| CN101335239B (en) | 2010-09-22 |
| KR20080113555A (en) | 2008-12-31 |
| US20080315271A1 (en) | 2008-12-25 |
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