CN101330324B - Method, apparatus and system for extracting synchronous indicating signal - Google Patents

Abstract

The invention is applied to the communication field, and provides a method, a device and a system for extracting synchronizing indication signals. The method for extracting the synchronizing indication signals comprises the following steps: receiving base band data signals; analyzing the base band data signals, obtaining frame synchronizing signals from carrier signals in the base band data signals, and contrasting with local clock signals to obtain first frequency deviation estimation information; and adjusting a local clock according to the first frequency deviation estimation information to output the stable frame synchronizing signals. In the invention, the first frequency deviation estimation information is obtained through obtaining the frame synchronizing signals in the base band data signals and contrasting with the local clock signals; and the clock is further adjusted according to the frequency deviation estimation information, to finally output the stable frame synchronizing signals; the extraction device of the frame synchronizing indication signals can be taken as an FPGA unit, and has the advantages of simple hardware structure, low cost, stability, fastness and high resolution.

Description

A kind of method for distilling of synchronous indicating signal, Apparatus and system

Technical field

The invention belongs to the communications field, relate in particular to a kind of method for distilling, Apparatus and system of synchronous indicating signal.

Background technology

TD SDMA (Time Division-Synchronous Code Division MultipleAccess; TD-SCDMA) technology is as the 3G (Third Generation) Moblie standard of China's proposition; Collection code division multiple access (Code Division Multiple Access; CDMA), time division multiple access (Time Division MultipleAccess; TDMA), (Frequence Division Multiple Access, FDMA) technology has the characteristics that power system capacity is big, the availability of frequency spectrum is high, antijamming capability is strong concurrently in one to frequency division multiple access.

The TD-SCDMA system is a time-sharing system, and for the TD repeater, up-downgoing is the prerequisite that guarantees equipment work synchronously, the method that realizes the TD system synchronization generally have global positioning system (GlobalPositioning System, GPS), method such as power detection.For indoor distributed system, the GPS method is powerless, and under the too little situation of signal strength signal intensity, the power detection method also shows very unreliablely, can't carry out the extraction of down channel synchronizing signal well.

Summary of the invention

The purpose of the embodiment of the invention is to provide a kind of method for distilling of synchronous indicating signal, be intended to solve prior art can't well to the problem of the extraction of the down channel synchronizing signal of TD-SCDMA system.

The embodiment of the invention is achieved in that a kind of method for distilling of synchronous indicating signal, said method comprising the steps of:

Receive base-band data signal;

Analyze said base-band data signal, obtain frame synchronizing signal in the carrier signal in said base-band data signal, and obtain the first frequency offset estimating information with the local clock signal contrast, the said step of obtaining frame synchronizing signal is:

Calculate the fast fourier transform FFT of said carrier signal sequence, obtain the frequency-region signal sequence, and its fast fourier inverse transformation IFFT is calculated in the frequency domain transform sequence of said frequency-region signal sequence and each the SYNC-DL sequence back of multiplying each other;

According to said first frequency offset estimating information adjustment local clock, to export stable frame synchronizing signal.

Another purpose of the embodiment of the invention is to provide a kind of synchronous indicating signal extraction element, and said device comprises:

The frame synchronizing signal extraction module is used to analyze base-band data signal, obtains frame synchronizing signal in the carrier signal in base-band data signal, and the said step of obtaining frame synchronizing signal is:

Calculate the fast fourier transform FFT of said carrier signal sequence, obtain the frequency-region signal sequence, and its fast fourier inverse transformation IFFT is calculated in the frequency domain transform sequence of said frequency-region signal sequence and each the SYNC-DL sequence back of multiplying each other;

Phase discriminator, the frame synchronizing signal and the local clock signal contrast that are used for said frame synchronizing signal extraction module is obtained obtain the first frequency offset estimating information; And

The frequency offset estimating message output module is used for the first frequency offset estimating information output with said phase discriminator output, with adjustment local clock, stabilizer frame synchronizing signal.

Another purpose of the embodiment of the invention is to provide a kind of synchronous indicating signal extraction system, and said system comprises above-mentioned synchronous indicating signal extraction element, and said system also comprises:

Down-converter unit is used for the radiofrequency signal down-conversion is obtained single carrier analog baseband signal and output;

AD conversion unit is used for the single carrier analog baseband signal process analog-to-digital conversion with said down-converter unit output, obtains digital baseband signal;

AD conversion unit is used for the frequency offset estimating information translation of said synchronous indicating signal extraction element output is handled; And

Clock signal generating unit is used for according to the signal after the said AD conversion unit conversion process, adjusts local clock, and exports adjusted local clock signal to said synchronous indicating signal extraction element.

In the embodiment of the invention; Through obtaining the frame synchronizing signal in the base band data information and obtaining frequency offset estimating information with the local clock signal contrast, further adjust clock according to this frequency offset estimating information, finally export stable frame synchronization index signal; The frame synchronization index signal extraction element that the embodiment of the invention provides can be a FPGA unit; Hardware configuration is simple, and cost is low, and stable, fast, resolution is high.

Description of drawings

Fig. 1 is the structure principle chart of the extraction system of the synchronizing signal that provides of the embodiment of the invention;

Fig. 2 is the realization flow figure that frame synchronization index signal extraction element extracts the synchronizing signal method among Fig. 1;

Fig. 3 is the structural representation of the QML-BCPD algorithm that provides of the embodiment of the invention;

Fig. 4 is the flow chart of the frame synchronization algorithm that provides of the embodiment of the invention;

Fig. 5 is the structural representation of the open loop algorithm for estimating that provides of the embodiment of the invention;

Fig. 6 is the structural representation of the closed loop algorithm for estimating that provides of the embodiment of the invention;

Fig. 7 is the flow chart of the closed loop algorithm for estimating that provides of the embodiment of the invention;

Fig. 8 is the structure principle chart of the frame synchronization index signal extraction element that provides of the embodiment of the invention.

Embodiment

In order to make the object of the invention, technical scheme and advantage clearer,, the present invention is further elaborated below in conjunction with accompanying drawing and embodiment.Should be appreciated that specific embodiment described herein only in order to explanation the present invention, and be not used in qualification the present invention.

The embodiment of the invention adopts the mode of baseband decoding to realize the extraction of downlink synchronous signal; At first the carrier signal zero intermediate frequency down-conversion that receives is obtained base-band data signal; Analyzing this base-band data signal confirms the carrier frequency of transmission and locks onto on the carrier wave of transmission; Obtain the frame synchronizing signal in the base-band data signal then and obtain frequency offset estimating information, further adjust clock, finally export stable frame synchronization index signal according to this frequency offset estimating information with the local clock signal contrast.

Fig. 1 shows the structural principle of the extraction system of the synchronizing signal that the embodiment of the invention provides, and for the ease of describing, only shows the part relevant with the embodiment of the invention.This extraction system can be used for the synchronizing signal of the down channel of TD-SCDMA system is extracted.

With reference to Fig. 1; At first carry out Filtering Processing from the radiofrequency signal that antenna receives through bandpass filtering unit 11; Send into down-converter unit 12 then and carry out down-conversion and obtain the single carrier analog baseband signal, 13 conversion obtain digital baseband signal to this single carrier analog baseband signal through AD conversion unit.In the embodiment of the invention, down-converter unit 12 can adopt chip MAX2392 to realize, further comprises low noise amplification module 121, down conversion module 122, amplification filtering module 123; AD conversion unit 13 can adopt chip AD9201 to realize, this chip contains two AD passages, and quantified precision can reach 10 bits, and it is one tunnel output that the I/Q circuit-switched data interweaves, so each chip adopts 4 appearance, and sampling rate is 10.24MHz.

Frame synchronization index signal extraction element 14 receives the digital baseband signal of D/A conversion unit 13 outputs, and carries out carrier wave detection, frequency offset estimating and synchronizing signal and extract.The synchronizing signal of extracting is by Serial Peripheral Interface (SPI) (Serial Peripheral Interface; SPI) bus is sent into D/A conversion unit 15; After the D/A conversion unit 15 novel digital-to-analogue conversions clock signal generating unit 16 is sent in signal output; The adjustment local clock, clock signal generating unit 16 is exported adjusted local clock signal to frame synchronization index signal extraction element 14 again, with the synchronizing signal of stabilizer frame synchronous indicating signal extraction element 14 extractions.Wherein, Frame synchronization index signal extraction element 14 can for a field programmable gate array (Field Programmable Gate Array, FPGA) unit, D/A conversion unit 15 can adopt chip AD5312 to realize; This chip contains two DA passages; The serial input, quantified precision can reach 10 bits, and clock signal generating unit 16 provides work clock for each unit module of internal system.

Fig. 2 shows the realization flow of frame synchronization index signal extraction element 14 extraction synchronizing signal methods among Fig. 1, and details are as follows:

In step S201, receive base-band data signal.

In the embodiment of the invention, this base-band data signal is the digital baseband data signal.

In step S202, detect and judge whether the base-band data signal that receives includes carrier signal.

In the embodiment of the invention, the power of the base-band data signal that receives through detection judges wherein whether include carrier signal, when signal power satisfies predetermined threshold value, representes wherein to contain carrier signal, and it is specific as follows said to detect principle.

Adopting chip MAX2392 with the automatic detection of 200KHz stepping frequency and selection, converter unit 12 is example; The down-conversion local frequency formula of chip MAX2392 is RF_Lo_Freq=12.8MHz * RFM/RFR; RFM initial value among 14 couples of MAX2392 of frame synchronization index signal extraction element is made as 10050, and the RFR initial value is made as 64; Make RF_Lo_Freq=2010MHz, step value is 200KHz, and the RFM value among the MAX2392 since 10050, from increasing 1, up to 10125, is being added in 1 at every turn, and frame synchronization index signal extraction element 14 carries out power detection, and writes down this performance number.After accomplishing the detection of 15MHz (75 frequencies) scan power, therefrom choosing the pairing frequency of power the maximum is current working frequency, and resets corresponding RFM value.

Specific algorithm: owing to what receive is chip signal, chip signal to noise ratio E _c/ I ₀Very low, and each chip all modulates, and therefore directly adopts the method for chip energy accumulation, can't obtain the signal to noise ratio raising.We propose the blind carrier power detection algorithm (QML-BCPD algorithm) of a kind of accurate ML.

Supposing to receive the chip complex signal is:

r _i＝h _i·c _i+n _i，i＝0，1，...，6399 (0.1)

H wherein _iExpression decline information, n _i～N (0, σ ²), c _i=± 1 ± j.

Make k=0,1 ..., 799, A _k={ r _8k+n| n=0,1 ..., 7}, $S^{\left(1\right)}=\left\{s_n^{\left(1\right)}\right|n=\mathrm{0,1},...,7\},$ $S^{\left(2\right)}=\left\{s_n^{\left(2\right)}\right|n=\mathrm{0,1},...,15\},$ $S^{\left(3\right)}=\left\{s_n^{\left(3\right)}\right|n=\mathrm{0,1},...,127\}$ The data acquisition system of representing three iteration respectively.Order ${\stackrel{\‾}{S}}^{\left(3\right)}=\left\{{-s}_n^{\left(3\right)}\right|n=\mathrm{0,1},...,127\},$ $S=\left\{s_n\right|n=\mathrm{0,1},...,255\}=S^{\left(3\right)}\∪{\stackrel{\‾}{S}}^{\left(3\right)},$ R _k=R _Ik+ jR _QkRepresent 8 chip correlations, P representes the carrier wave gross power, and then the iterative process of QML-BCPD algorithm can be described below:

(1) by set A _kProcess and difference are calculated, and obtain S set ⁽¹⁾

(2) by S set ⁽¹⁾Process and difference are calculated, and obtain S set ⁽²⁾

(3) by S set ⁽²⁾Process and difference are calculated, and obtain S set ⁽³⁾

(4) by S set ⁽³⁾Through getting negative computing, obtain S set ⁽³⁾Thereby, obtain S set;

(5) process maximum operation in S set obtains $R_{\mathrm{Ik}}=\mathrm{Arg}\underset{s_n\∈S}{\mathrm{Max}}\mathrm{Re}\left(s_n\right),$ $R_{\mathrm{Qk}}=\mathrm{Arg}\underset{s_n\∈S}{\mathrm{Max}}\mathrm{Im}\left(s_n\right);$

(6) through accumulating operation, obtain the carrier wave gross power $P=\underset{k=0}{\overset{799}{\mathrm{\&Sigma;}}}{\mathrm{<figure-callout\; id="2"\; label="R\; Ik"\; filenames="S2008101425022E00021.png"\; state="\{\{state\}\}">R</figure-callout>}}_{\mathrm{Ik}}^{}+{\mathrm{<figure-callout\; id="2"\; label="R\; Qk"\; filenames="S2008101425022E00021.png"\; state="\{\{state\}\}">R</figure-callout>}}_{\mathrm{Qk}}^{}.$

The detailed structure of above-mentioned algorithm is illustrated in fig. 3 shown below; It is actually carries out the exhaustive of related operation to 8 chip signal; If directly carry out computing, then complexity is 256 * 7=1792 time complex addition, if carry out according to above-mentioned algorithm; Then only need 8+16+128=152 time complex addition, efficient can be saved to the method for exhaustion like this $\mathrm{\&eta;}=\frac{152}{1792}=8.48\%.$

Because it is exhaustive that above-mentioned algorithm has just carried out in the scope of 8 chips, be accurate maximum likelihood QML algorithm therefore.Because the spreading gain of 8 chips is 10lg8=9dB; Basically satisfy the requirement of TD-SCDMA signal to noise ratio, in addition, if further increase the length of relevant chip; Though also can promote algorithm structure; The more complicated but algorithm becomes, the consideration of combination property and complexity two aspects, the suggestion correlation length is SF=8.

If the base-band data signal that receives does not comprise carrier signal; Then indication generates frequency stepping information; By the new base-band data signal of this frequency stepping information triggering for generating; Return step S201 and receive this new base-band data signal again, and the detection judgement comprises carrier signal in the base-band data signal that receives again.

If include carrier signal in the base-band data signal that receives, then get into next step.

In step S203, analyze this base-band data signal, and in carrier signal, obtain frame synchronizing signal, and obtain the first frequency offset estimating information with the local clock signal contrast.

After obtaining frame synchronizing signal in the carrier signal in base-band data signal, carry out phase discrimination processing, obtain the first frequency offset estimating information through after the filtering again with the local clock signal.Wherein, the principle of in the carrier signal in base-band data signal, obtaining frame synchronizing signal is for accomplishing the catching of SYNC-DL sequence, and is specific as follows said.

For reducing computation complexity, the embodiment of the invention adopts frequency-domain transform method, and it is { r}=(r that order receives burst ₀, r ₁... .), l SYNC-DL sequence table is shown $\left\{s^{\left(l\right)}\right\}=(s_0^{\left(l\right)},s_1^{\left(l\right)},...,s_{63}^{\left(l\right)}),$ s _i ^(l)Be the QPSK symbol, 0≤l＜32.The correlated results that then receives between signal and l the SYNC-DL sequence is:

$c_i^{\left(l\right)}=\underset{j=0}{\overset{63}{\mathrm{\&Sigma;}}}{r}_{i+j}^{*}\&CenterDot;s_j^{\left(l\right)}---\left(5.1\right)$

Then the ML decision rule of SYNC-DL sequence and sync bit

is:

$c_{\hat{i}}^{\left(\hat{l}\right)}=\underset{0\&le;i<6400}{\max }\left\{\underset{0\&le;l<32}{\max }\right\{c_i^{\left(l\right)}\left\}\right\}---\left(5.2\right)$

Wherein, The estimation of

expression SYNC-DL sequence numbering, the estimation of

expression DwPTS original position.For to anti-fading, improve the detection performance under the low signal-to-noise ratio condition, can carry out the multiframe noncoherent accumulation, then ML decision rule is modified to:

$c_{i,H}^{\left(l\right)}=\frac{1}{H}\underset{h=0}{\overset{H-1}{\mathrm{\&Sigma;}}}\left|c_{i+6400h}^{\left(l\right)}\right|---\left(5.3\right)$

Wherein, H is the frame number that adds up.

Formula (5.2) is if directly calculate in time domain; Then in a sub-frame period 5ms, 6400 32 length of needs calculating are 64 related operation, and the corresponding algorithm complexity is 6400 * 32 * 64 * 200=2621.44MCMPS (Millions of Complex Multiplication PerSecond); Complexity is too high; Be difficult to realize, so we need adopt frequency domain method, the complexity of reduction computing with hardware.

The computing of formula (5.1) is actually convolution algorithm, if adopt the FFT conversion, is product with convolution transform, then can reduce computational complexity significantly.For the convenience of arthmetic statement, we define length is N, and original position is that the conjugation of Δ receives burst

${\left\{r^{*}\right\}}_{\mathrm{\&Delta;},N}=(r_{\mathrm{\&Delta;}}^{*},r_{\mathrm{\&Delta;}+1}^{*},...,r_{\mathrm{\&Delta;}+N-1}^{*})---\left(5.4\right)$

We are with SYNC-DL sequence backward and add N-64 0, obtain a new family sequence:

${\left\{s^{\left(l\right)}\right\}}_N^a=(s_{63}^{\left(l\right)},s_{62}^{\left(l\right)},...,s_0^{\left(l\right)},0,...,0)---\left(5.5\right)$

The corresponding FFT frequency domain transform sequence of this sequence family is:

${\left\{S^{\left(l\right)}\right\}}_N=(S_0^{\left(l\right)},S_1^{\left(l\right)},...,S_{N-1}^{\left(l\right)})=\mathrm{FFT}\left[{{\{s}^{\left(l\right)}\}}_N^a\right]---\left(5.6\right)$

In the formula, a representes adapted.

Then the flow process of whole algorithm is as shown in Figure 4:

(1) calculates the FFT conversion that receives burst

{R} _N＝(R ₀，R ₁，...，R _N-1)＝FFT[{r ^*} _Δ，N] (5.7)

(2) the frequency domain transform sequence of frequency-region signal sequence and each SYNC-DL multiplies each other

${\left\{C^{\left(l\right)}\right\}}_N=(C_0^{\left(l\right)},C_1^{\left(l\right)},...,C_{N-1}^{\left(l\right)})={\left\{R\right\}}_N\&CenterDot;{\left\{S^{\left(l\right)}\right\}}_N---\left(5.8\right)$

(3) calculate the IFFT conversion

${\left\{{\tilde{c}}^{\left(l\right)}\right\}}_{\mathrm{\&Delta;},N}=({\tilde{c}}_{\mathrm{\&Delta;}}^{\left(l\right)},{\tilde{c}}_{\mathrm{\&Delta;}+1}^{\left(l\right)},...,{\tilde{c}}_{\mathrm{\&Delta;}+N-1}^{\left(l\right)})=\mathrm{IFFT}\left[{\left\{C^{\left(l\right)}\right\}}_N\right]---\left(5.9\right)$

Then correlation is:

$c_i^{\left(l\right)}={\tilde{c}}_{i+63}^{\left(l\right)},\mathrm{\&Delta;}\&le;i<\mathrm{\&Delta;}+N-64---\left(5.10\right)$

In fact aforementioned calculation has used overlapping reservation method to calculate long sequence convolution.To the TD-SCDMA system, best N=512, then each data window can obtain 512-63=449 correlation.For a sub-frame length, total

Individual data window, the algorithm complex that above-mentioned 3 steps handle is (15 (data window number) * 256 * log ₂256 (FFT complexity) * 33 (1 FFT, 32 IFFT)+512 * 15 * 32 (frequency domain multiplies each other)) * 200=251.904MCMPS.Compare with time domain approach, algorithm complex has reduced by 10 times.

In order further to reduce algorithm complex, can adopt the method for frequency domain filtering, calculate approximate correlation { y ^(l)} _{Δ, M}, the frequency domain sequence { Y that it is corresponding ^(l)} _MFor:

$Y_q^{\left(l\right)}=\left\{\begin{array}{cc}{R}_q{\&CenterDot;S}_q^{\left(l\right)}& 0\&le;q<M/2\\ R_{q+N-M}\&CenterDot;S_{q+N-M}^{\left(l\right)}& M/2\&le;q<M\end{array}\right.---\left(5.11\right)$

In the formula, M is 2 integer power, and M＜N, and the complexity gain that therefore can obtain is K=N/M.

In order to obtain approximate relevant frequency domain sequence, can adopt the perfect low pass filtering method, that is:

$G_q^{\left(l\right)}=\left\{\begin{array}{cc}{C}_q^{\left(l\right)}& 0\&le;q<M/2\\ 0& M/2\&le;q<N-M/2\\ C_q^{\left(l\right)}& N-M/2\&le;q<N\end{array}\right.---\left(5.12\right)$

Following formula is actually the frequency domain ideal LPF, and the mid portion that is about to frequency spectrum is forced to 0.Definition ${\left\{g^{\left(l\right)}\right\}}_{\mathrm{\&Delta;},N}=\mathrm{IFFT}\left[{\left\{G^{\left(l\right)}\right\}}_N\right],$ Then approximate relevant can the expression as follows:

$y_{i+\mathrm{\&Delta;}}^{\left(l\right)}=g_{\mathrm{Ki}+\mathrm{\&Delta;}}^{\left(l\right)},0\&le;i<M---\left(5.13\right)$

The approximate correlation that utilizes frequency domain filtering to obtain is actually frequency domain and owes the correlation of sampling, and the correlation peak that therefore obtains can drift about, and need carry out precise search again in the 6th step, improves and catches precision.

After adopting approximate data, for a sub-frame length, the algorithm complex that above-mentioned 3 steps handle is (15 (data window number) * (256 * log ₂256+256/K * log ₂(256/K) * 32+512/K * 32 (frequency domain multiplies each other)) * 200.If get K=8, then algorithm complex is 27.648MCMPS, compares with direct frequency domain method, and algorithm complex has reduced about 10 times again.

Accumulation frame length H=20or30 can obtain anti fading performance preferably.

In step S204,, in carrier signal, obtain the second frequency offset estimating information in conjunction with frame synchronizing signal.

In order to obtain better frequency offset estimating information calculations precision,, also need combine frame synchronizing signal to obtain the second frequency offset estimating information as a preferred embodiment of the present invention.

The frequency stability of local crystal oscillator is 1ppm, because the RF frequency is 2GHz, corresponding maximum frequency deviation is 4KHz.Because the tdma frame design feature of TD-SCDMA, traditional can't use based on CP continuous pilot ML algorithm for estimating, and therefore, we recommend to use the non-linear low complex degree FoE algorithm of SYNC-DL sequence and midamble sequence.

1, signal model

Supposing to receive signal is:

$r_k=d_k{e}^{-\mathrm{<figure-callout\; id="2"\; label="j"\; filenames="S2008101425022E00021.png"\; state="\{\{state\}\}">j</figure-callout>}2\mathrm{\&pi;\&Delta;fk}{T}_c}+v_k---\left(6.1\right)$

D wherein _kBe data symbol, Δ f is a frequency deviation.

The result who receives signal and local sequence conjugate multiplication is:

$y_i=r_{i-\mathrm{\&epsiv;}}{a}_i^{*},1\&le;i\&le;N---\left(6.2\right)$

Wherein, ε is the delay inequality of reception signal and local sequence, $a_i(i=\mathrm{1,2},...,N;a_i{a}_i^{*}=1)$ Being training sequence, perhaps is SYNC-DL sequence (N=64), perhaps is midamble sequence (N=144).

The frequency offset estimating of utilizing the ML criterion to obtain is:

$\mathrm{\&Delta;}\hat{f}\&cong;\frac{1}{\mathrm{\&pi;}{T}_c(M+1)}\arg \left\{\underset{k=1}{\overset{M}{\mathrm{\&Sigma;}}}R\left(k\right)\right\}---\left(6.3\right)$

Wherein,

$R\left(k\right)=\frac{1}{N-k}\underset{k-1}{\overset{N-1}{\mathrm{\&Sigma;}}}{y}_i{y}_{i-k}^{*},0\&le;k\&le;N-1---\left(6.4\right)$

2, algorithm flow

The FoE algorithm comprises open loop estimation and closed loop estimation two parts.In the open loop estimating part, adopt the SYNC-DL sequence to carry out frequency offset estimating, in the closed loop estimating part, adopt the midamble sequence to carry out frequency offset estimating.

(1) algorithm structure of open loop estimation is as shown in Figure 5, and the open loop frequency offset estimating utilizes formula (6.3) to calculate,

In order to resist channel fading, need carry out multi-frame mean, therefore obtain following estimation formulas:

$\mathrm{\&Delta;}\hat{f}\&cong;\frac{1}{\mathrm{\&pi;}{T}_{c}L(M+1)}\underset{l=0}{\overset{L-1}{\mathrm{\&Sigma;}}}\arg \left\{\underset{k=1}{\overset{M}{\mathrm{\&Sigma;}}}{R}_l\left(k\right)\right\}---(6.5)$

Wherein,

$R_l\left(k\right)=\frac{1}{N-k}\underset{k=1}{\overset{N-1}{\mathrm{\&Sigma;}}}{y}_{i+6400l}{y}_{i+6400l-k}^{*},0\&le;k\&le;N-1---\left(6.6\right)$

The employing open loop is estimated, can obtain the estimated accuracy below the 1ppm, in the process that correlation adds up, can reject the inconsistent correlation of symbol, can further improve estimated performance like this.General, can make that the frame number that adds up is L=10.In order to obtain higher estimated accuracy, need carry out closed loop and estimate.

(2) algorithm structure of closed loop estimation is as shown in Figure 6, and the design philosophy of closed loop algorithm for estimating is to find and delete the improper value of frequency offset estimating, thereby can reduce the root mean square of frequency offset estimating, improves the convergence rate of estimating.Closed loop algorithm has three kinds of criterions, and its algorithm flow is as shown in Figure 7.

Three criterions that closed loop is estimated are: symbol criterion, standard deviation criterion and statistics independent criteria.Preceding two kinds of criterion main purposes are to improve the accuracy of estimating, and introduce the statistics independent criteria, then are important component and the correction terms for the balance frequency offset estimating, and keep the statistical independence between the two.Introduce this three criterions below in detail.

(1) symbol criterion

If which value of the main opposite in sign of the symbol of deletion estimated value and estimation set, then the reliability of frequency offset estimating can improve.When α ≠ 0, then need the using symbol criterion.If the estimation item number that contains same-sign then need carry out frequency offset correction greater than α.

(2) standard deviation criterion

Standard deviation sigma with nearest received frequency offset correction set _OldBe reference value, if the standard deviation of new frequency offset correction set satisfies σ＜β σ _Old, then accepted.Less β → 1 is corresponding to bigger K, otherwise bigger β is corresponding to less K.

(3) statistics independent criteria

In the closed loop algorithm for estimating, want γ sub-frame at interval between the two adjacent groups frequency offset correction item at least, thus the independence between guaranteeing to estimate.

Relate to parameter: L in the closed loop algorithm for estimating, α, beta, gamma, K, its concrete value need confirm that the embodiment of the invention provides the some of the recommendations value, and is as shown in the table through emulation:

α	β	γ	L	K	Er 50(Hz)	Er 100(Hz)	P 50	P 100
									1	10	3	5	0.1	173	145	0.8	0.87
1	10	1	5	0.1	188	186	0.75	0.74
									1	10	5	5	0.1	213	148	0.71	0.86
1	10	3	10	0.1	174	164	0.75	0.8
									1	10	10	10	0.1	318	189	0.6	0.76
0	10	3	5	0.1	187	174	0.76	0.8
									5	10	3	5	0.1	241	153	0.62	0.82
1	1	3	5	0.4	233	222	0.64	0.65
									1	50	3	5	0.4	351	340	0.55	0.56
1	1	3	5	0.1	366	335	0.53	0.56
									1	50	3	5	0.1	187	174	0.76	0.79

In the last table, Er ₅₀Or Er ₁₀₀Represent the frequency offset estimating standard deviation after the iteration 50 or 100 times, P ₅₀Or P ₁₀₀Expression is through after 50 or 100 iteration, and the frequency offset estimating error is less than the probability of 200Hz.Channel condition is the VehicularA channel, and the speed of a motor vehicle is 120km/h, and carrier/interface ratio is C/I=-3dB.Parameter configuration under other channel condition repeats no more.

In step S205, according to first and second frequency offset estimating information adjustment local clock, to export stable frame synchronizing signal.

In conjunction with first, second frequency offset estimating information adjustment local clock,, can certainly only realize through first frequency offset estimating information adjustment local clock to export stable frame synchronizing signal.

Fig. 8 shows the structural principle of the frame synchronization index signal extraction element that the embodiment of the invention provides, and this unit can be used for the synchronizing signal of the down channel of TD-SCDMA system is extracted.

Serial to parallel conversion module 141 is carried out serial to parallel conversion with the base-band data signal that receives; Obtain the I/Q two paths of data; Send into carrier power detection module 142 then, carrier power detection module 142 detects to judge whether comprise carrier signal in the two-way base-band data signal, if do not comprise carrier signal; Then indicate frequency adjusting module 143 to generate frequency stepping information, and export down-converter unit 12 to the new baseband signal of triggering for generating; If include carrier signal in the base-band data signal; Then output enable signal Enable is to the frame synchronizing signal extraction module 144 and the second frequency offset estimating information generating module 148, trigger frame synchronizing signal extraction module 144 and the second frequency offset estimating information generating module, 148 receiving and analyzing base-band data signals.Wherein carrier power detection module 142 detects and judges that whether base-band data signal comprises the as indicated above originally of carrier signal, repeats no more.

Frame synchronizing signal extraction module 144 is analyzed the base-band data signal after 141 conversion of serial to parallel conversion modules, and in carrier signal, obtains frame synchronizing signal, and principle is for to the catching of SYNC-DL sequence, and is specifically as indicated above, repeats no more.The local clock signal that this frame synchronizing signal and clock signal generating unit 16 obtain after handling through frequency division module 145 frequency divisions carries out phase demodulation in phase discriminator 146, then through obtaining the first frequency offset estimating information after loop filter 147 filtering.

The frame synchronizing signal that the second frequency offset estimating information generating module 148 combines frame synchronizing signal extraction module 144 to obtain; Base-band data signal after 141 conversion of analysis serial to parallel conversion module; And in carrier signal, obtaining the second frequency offset estimating information, its concrete principle is as indicated above, repeats no more here.Wherein the second frequency offset estimating information generating module 148 is optional as the case may be.

Frequency offset estimating message output module 149 merges first frequency offset estimating information of loop filter 147 outputs and the second frequency offset estimating information of the second frequency offset estimating information generating module, 148 outputs; And the process spi bus is sent into outside D/A conversion unit 15; By exporting clock signal generating unit 16 to after D/A conversion unit 15 processing; With adjustment local clock frequency, more stable local clock and the frame synchronizing signal of final acquisition.

In the embodiment of the invention, analyze base-band data signal and confirm that the carrier frequency of transmission also locks onto on the carrier wave of transmission, obtain the frame synchronizing signal in the base band data information then and obtain frequency offset estimating information with the local clock signal contrast; Further adjust clock according to this frequency offset estimating information; The stable frame synchronization index signal of final output wherein for improving the precision of frame synchronization index signal, adopts the combination adjustment local clock of the first frequency offset estimating information and the second frequency offset estimating information; The frame synchronization index signal extraction element that the embodiment of the invention provides can be a FPGA unit; Hardware configuration is simple, and cost is low, and stable, fast, resolution is high.

The above is merely preferred embodiment of the present invention, not in order to restriction the present invention, all any modifications of within spirit of the present invention and principle, being done, is equal to and replaces and improvement etc., all should be included within protection scope of the present invention.

Claims (10)

1. the method for distilling of a synchronous indicating signal is characterized in that, said method comprising the steps of:

Receive base-band data signal;

Analyze said base-band data signal, obtain frame synchronizing signal in the carrier signal in said base-band data signal, and obtain the first frequency offset estimating information with the local clock signal contrast, the said step of obtaining frame synchronizing signal is:

Calculate the fast fourier transform FFT of said carrier signal sequence, obtain the frequency-region signal sequence, and its fast fourier inverse transformation IFFT is calculated in the frequency domain transform sequence of said frequency-region signal sequence and each the SYNC-DL sequence back of multiplying each other;

According to said first frequency offset estimating information adjustment local clock, to export stable frame synchronizing signal.

2. the method for distilling of synchronizing signal as claimed in claim 1 is characterized in that, according to said first frequency offset estimating information adjustment local clock, before the step of exporting stable frame synchronizing signal, said method further may further comprise the steps said:

In conjunction with said frame synchronizing signal, obtain the second frequency offset estimating information in the carrier signal in said base-band data signal;

Said according to said first frequency offset estimating information adjustment local clock, be specially with the step of exporting stable frame synchronizing signal:

According to said first frequency offset estimating information and second frequency offset estimating information adjustment local clock, to export stable frame synchronizing signal.

3. the method for distilling of synchronizing signal as claimed in claim 1; It is characterized in that; At the said base-band data signal of said analysis; Obtain frame synchronizing signal in the carrier signal in said base-band data signal, and obtain before the step of the first frequency offset estimating information the further following steps of said method with the local clock signal contrast:

Detect and judge whether said base-band data signal includes carrier signal; Be then to get into to analyze said base-band data signal; Obtain frame synchronizing signal in the carrier signal in said base-band data signal, and obtain the step of the first frequency offset estimating information with the local clock signal contrast; Otherwise indication generates frequency stepping information, by this frequency stepping information triggering for generating new base-band data signal and reception again.

4. the method for distilling of synchronizing signal as claimed in claim 1 is characterized in that, the step that said and local clock signal contrast obtains the first frequency offset estimating information is specially:

Said frame synchronizing signal and local clock signal carry out phase discrimination processing, obtain the first frequency offset estimating information through after the filtering again.

5. a synchronous indicating signal extraction element is characterized in that, said device comprises:

The frame synchronizing signal extraction module is used to analyze base-band data signal, obtains frame synchronizing signal in the carrier signal in base-band data signal, and the said step of obtaining frame synchronizing signal is:

Calculate the fast fourier transform FFT of said carrier signal sequence, obtain the frequency-region signal sequence, and its fast fourier inverse transformation IFFT is calculated in the frequency domain transform sequence of said frequency-region signal sequence and each the SYNC-DL sequence back of multiplying each other;

Phase discriminator, the frame synchronizing signal and the local clock signal contrast that are used for said frame synchronizing signal extraction module is obtained obtain the first frequency offset estimating information; And

The frequency offset estimating message output module is used for the first frequency offset estimating information output with said phase discriminator output, with adjustment local clock, stabilizer frame synchronizing signal.

6. synchronous indicating signal extraction element as claimed in claim 5 is characterized in that, said device also comprises:

Frequency division module is used for that external timing signal is carried out frequency division and handles, and obtains the local clock signal, and exports said phase discriminator to; And

Loop filter is used for the first frequency offset estimating information of said phase discriminator output is carried out Filtering Processing, exports said frequency offset estimating message output module to.

7. synchronous indicating signal extraction element as claimed in claim 5 is characterized in that, said device also comprises:

The second frequency offset estimating information generating module is used to the frame synchronizing signal that combines said frame synchronizing signal extraction module to obtain, analyzes base-band data signal, and obtains the second frequency offset estimating information in the carrier signal in base-band data signal;

Said frequency offset estimating message output module is used to merge the first frequency offset estimating information of said phase discriminator output and the second frequency offset estimating information and the output of second frequency offset estimating information generating module output, with adjustment local clock, stabilizer frame synchronizing signal.

8. synchronous indicating signal extraction element as claimed in claim 5 is characterized in that, said device also comprises:

The carrier power detection module is used for detecting to judge whether base-band data signal comprises carrier signal, if comprise, then triggers said frame synchronizing signal extraction module receiving and analyzing base-band data signal; And

The frequency adjusting module is used for detecting when judging base-band data signal and not comprising carrier signal at said carrier power detection module, generates frequency stepping information and output by said carrier power detection module indication.

9. synchronous indicating signal extraction element as claimed in claim 5 is characterized in that, said device also comprises:

The serial to parallel conversion module, the base-band data signal that is used to receive carries out serial to parallel conversion, obtains the I/Q two paths of data, and data are exported.

10. a synchronous indicating signal extraction system is characterized in that, said system comprises that said system also comprises like each described synchronous indicating signal extraction element of claim 5 to 9:

Down-converter unit is used for the radiofrequency signal down-conversion is obtained single carrier analog baseband signal and output;

AD conversion unit is used for the single carrier analog baseband signal process analog-to-digital conversion with said down-converter unit output, obtains digital baseband signal;

AD conversion unit is used for the frequency offset estimating information translation of said synchronous indicating signal extraction element output is handled; And

Clock signal generating unit is used for according to the signal after the said AD conversion unit conversion process, adjusts local clock, and exports adjusted local clock signal to said synchronous indicating signal extraction element.

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