CN101330091A - Phase-changing storage device and manufacture method thereof - Google Patents
Phase-changing storage device and manufacture method thereof Download PDFInfo
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Abstract
The invention provides a phase-change memory device and a manufacturing method thereof. The phase-change memory device comprises a phase-change memory cell array. Each phase-change memory cell comprises a transistor element arranged on a base plate. A vertical type electrode structure is electrically connected with the transistor element, and a vertical type memory layer and the vertical type electrode structure are stacked in a vertical manner and come into contact with a contact point, wherein, the contact point is the phase-change position for the phase-change memory cell action.
Description
Technical field
The present invention is particularly to a kind of phase change memory cell, phase change memory array structure and preparation method thereof relevant for a kind of memory component and manufacture method thereof.
Background technology
Ovonics unified memory (Phase-Change Memory is called for short PCM) has speciality non-volatile, that height reads signal, high density, high erasable number of times and low-work voltage/electric current, is quite potential memory.In order to satisfy high density and the demand that reduces current density, the element design rule of tradition Ovonics unified memory is the contact area of dwindling memory cell and heating electrode, to reduce operating current, further dwindle transistorized size, reach the purpose of high density, mass storage device.Yet, so the contact area that need dwindle memory cell and heating electrode limited for fear of the current density that current controling element (generally being example with the MOS transistor) is provided.
Phase-transition material can present two kinds of solid-state phases at least, comprises crystalline state and noncrystalline attitude, and the change structure of general using temperature is carried out the conversion between binary states.The crystalline phase structure is because the atomic arrangement of tool systematicness makes its resistance lower.On the other hand, noncrystalline phase structure has irregular atomic arrangement makes its resistance higher, and the resistance difference between crystalline phase structure and the noncrystalline phase structure can be up to four more than the order of magnitude.Therefore, can distinguish the crystalline state of phase-transition material and the state of noncrystalline attitude easily by simple electrically measurement.In various phase-transition materials, the alloy of germanic (Ge), antimony (Sb) and single (Te) extensive use to various recording elements.
Since phase-transition material change a kind of reversible reaction mutually into, so phase-transition material is to store by the conversion between non-crystalline state and the crystalline state binary states when being used for being used as storage material.More particularly, can utilize the difference of resistance between crystalline state and the noncrystalline attitude to write or read bank bit rank 0 and 1.
In the memory cell array that is characterized as formation of tradition phase change storage array, each memory cell comprises the transistor phase change storage material layer member of arranging in pairs or groups, and claims the 1T-1R structure again.No. 6,605,821, No. 6,429,064, United States Patent (USP) US, US, US all disclose pcram structure 6,707, No. 087, and its common feature is for reducing the thickness of contact electrode, to reach the purpose of dwindling element.More particularly, the required current density of Ovonics unified memory is determined by the contact area of phase change layer and electrode.The contact area that reduces phase change layer and electrode promptly reduces the required current density of Ovonics unified memory.
Fig. 1 is the floor map that shows traditional phase change storage array.See also Fig. 1, semiconductor substrate 10 has transistor array (not shown) and is connected in series by the lead 20 along first direction.Electrode structure 32 is electrical connected with each transistor unit.Electrode structure 32 is a square metal wall construction, is centered around around the insulating barrier 34.One phase change accumulation layer 40 is arranged on electrode structure 32 and the insulating barrier 34, and is positioned at a corner of square metal wall construction, to reduce the contact area of phase change accumulation layer 40 and electrode structure 32.The contact area that reduces phase change layer and electrode promptly reduces the required current density of Ovonics unified memory.
Yet in Fig. 1, phase change accumulation layer 40 is the block on plane, and the contact area of itself and electrode structure 32 still must further be dwindled the contact area that reduces phase change layer and electrode along with the component density increase.
Fig. 2 A-2C is the schematic diagram that shows another kind of traditional phase change storage array, and wherein Fig. 2 A and 2B show that respectively along the generalized section of directions X and Y direction, Fig. 2 C is a floor map.See also Fig. 2 A and 2B, a metal plug 55 is arranged in the Lower Half of a dielectric layer 50, and the other end of metal plug 55 is connected with transistor unit (not shown).One electrode structure 60 is arranged in the first half of dielectric layer 50, and is electrical connected with metal plug 55.Electrode structure 60 is a square metal wall construction, around an insulating barrier 65.One dielectric layer 72 is arranged on the dielectric layer 50, has the electrode structure 60 of strip opening exposed portions serve.One phase change accumulation layer 74 is arranged on the dielectric layer 72 and inserts the strip opening, makes the contact area of itself and electrode structure 60 be confined to the width of strip opening thereby the contact area of further dwindling phase change layer and electrode.Plain conductor 76 is arranged on the phase change accumulation layer 74, as the bit line of Ovonics unified memory.Protective layer 80 is arranged on the plain conductor 76, with the protected storage structure.
In order further to increase the integrated level of novel phase change memory, thereby need further dwindle the contact area of phase change layer and electrode.Moreover traditional novel phase change memory is all the transistor phase change means of storage of arranging in pairs or groups, and claims the 1T-1R structure again.The 1T-1R pcram structure causes the memory cell arrays space to fail effectively to utilize, and the integrated level of restriction novel phase change memory.
Summary of the invention
In view of this, the present invention proposes a kind of phase change memory cell design and memory array structure, utilize vertical type electrode structure and vertical type phase change means of storage, dwindle contact area, and utilize a current controling element two phase change memory cell structures (1T-2R structure) of arranging in pairs or groups, reach and dwindle the effect that the memory element unit are promptly increases integrated level.
The invention provides a kind of phase-change memorizer device, comprising: a current controling element is arranged on the substrate; Vertical electrode structure and this current controling element are electrical connected always; And one first vertical type accumulation layer and this vertical type electrode structure up and down upright form stack and contact in a first make contact, wherein the first make contact of this vertical type electrode structure and this first vertical type accumulation layer intersection is as the phase change position of one first phase change memory cell effect.
The present invention provides a kind of manufacture method of phase-change memorizer device in addition, comprising: provide a substrate to have a current controling element thereon; Form always vertical electrode structure on this substrate, and be electrical connected with this current controling element; And form a vertical type accumulation layer on this vertical type electrode structure, and stack phase change position as a phase change memory cell effect with upright form.
For above-mentioned purpose, the feature and advantage that make the present invention can become apparent, embodiment cited below particularly, and cooperate appended graphicly, be described in detail below.
Description of drawings
Fig. 1 is the floor map that shows traditional phase change storage array;
Fig. 2 A-2C is the schematic diagram that shows another kind of traditional phase change storage array, and wherein Fig. 2 A and 2B show that respectively along the generalized section of directions X and Y direction, Fig. 2 C is a floor map;
Fig. 3 is the schematic diagram that shows according to an Ovonics unified memory of the embodiment of the invention;
Fig. 4 is the floor map that shows according to the phase-change memory array of the embodiment of the invention;
Fig. 5 A-14B is the schematic diagram of demonstration according to each step of manufacture method of the phase-change memory array of first embodiment of the invention;
7A-9C figure shows the schematic diagram of formation vertical type electrode structure step on substrate of first embodiment of the invention respectively;
Figure 10 A-12B shows the schematic diagram of formation vertical type accumulation layer step on the vertical type electrode structure of first embodiment of the invention respectively;
Figure 13 A-14B shows that respectively the formation bit line of first embodiment of the invention connects the schematic diagram of vertical type accumulation layer step;
Figure 15 A-17C shows the schematic diagram of formation vertical type accumulation layer step on the vertical type electrode structure of second embodiment of the invention respectively;
Figure 18 A-19C shows that respectively the formation bit line of second embodiment of the invention connects the schematic diagram of vertical type accumulation layer step;
Figure 20 is the schematic diagram of demonstration according to the same attitude of the phase-change memory array of the embodiment of the invention;
Figure 21 is the schematic diagram that shows according to another sample attitude of phase-change memory array of the embodiment of the invention; And
Figure 22 is the schematic diagram that shows according to another sample attitude of phase-change memory array of the embodiment of the invention.
The main element symbol description
Known part (Fig. 1～2)
10～semiconductor substrate;
20～lead;
32～electrode structure;
34～insulating barrier;
40～phase change accumulation layer;
50～dielectric layer;
55～metal plug;
60～electrode structure;
65～insulating barrier;
72～dielectric layer;
74～phase change accumulation layer;
76～plain conductor;
80～protective layer.
This case part (Fig. 3～22)
100～Ovonics unified memory unit;
110～substrate;
120～grid;
122～source electrode;
124～drain electrode;
130～conductive plug;
135～vertical type electrode structure;
140～vertical type accumulation layer;
145～contact point;
150～bit line;
150a～first bit line;
150b～second bit line;
222,224, three electrodes of 226～bipolar junction transistor (BJT);
115～the first dielectric layers;
132～the second dielectric layers;
133～opening;
136～the 3rd dielectric layers;
138～the 4th dielectric layers;
E～anisotropic etch-back step;
140a～first vertical type the accumulation layer;
140b～second vertical type the accumulation layer;
Second metal level of two subtend clearance walls of 140 '～parallel first direction;
140 "～second metal level of two subtend clearance walls of parallel second direction;
142～clearance wall;
I～ion implantation;
146～the 5th dielectric layers;
246～the 4th dielectric layers;
238～the 5th dielectric layers;
240～top metal level;
257～contact hole;
258～metal plug;
M11-M22～Ovonics unified memory;
N11～Ovonics unified memory.
Embodiment
The embodiment of the invention described " Ovonics unified memory " generally refers to the final pattern of product, as comprises the wafer (chip) of control Driver Circuit." memory array " refers to comprise the colony of the orderly arrangement of transistor (transistor) and novel phase change memory, do not contain the array portion of control Driver Circuit." novel phase change memory " or " memory cell " refers to the combination of heating electrode and phase change layer, is two memory cell of a transistor collocation as 1T2R structure of the present invention.
In order to increase the integrated level of novel phase change memory or memory cell, the present invention proposes a kind of phase change memory cell design and memory array structure, reaches the effect of dwindling contact area and dwindling unit are simultaneously.More particularly, the present invention therefore by the mode that reduces thickness, obtains minimum contact area by vertical type heating electrode and vertical type phase change layer, reaches the purpose that reduces operating current.On the other hand, adopt the pattern of transistor two memory cell of collocation (1T-2R), under the prerequisite that does not change the transistor design rule, can further dwindle the memory cell unit are, reach the effect that storage density doubles.
Fig. 3 shows the schematic diagram of a phase change memory cell according to an embodiment of the invention.See also Fig. 3, a phase change memory cell 100 comprises that a current controling element is arranged on the substrate 110.Current controling element can be a transistor unit, and for example MOS transistor has grid 120, source electrode 122 and drain electrode 124.(word line's grid 120 of MOS transistor WL) contacts with the grid of other MOS transistor by the word line along first direction.Vertical type electrode structure 135 is electrical connected by a conductive plug 130 with current controling element.One vertical type accumulation layer 140 and vertical type electrode structure about in the of 135 upright form stack and contact in a contact point 145, as a phase change memory cell.(bitline BL) 150 is connected in series each vertical type accumulation layer 140 along second direction to one bit line, wherein first direction and second direction quadrature in fact.
Fig. 4 is the floor map that shows according to the phase-change memory array of the embodiment of the invention.In Fig. 4, the memory array that is made of phase change memory cell shown in Figure 3 100 is electrical connected by a plurality of current controling elements corresponding on conductive plug 130 and the substrate 110.Many word line 120 is connected in series each current controling element along first direction.Many first bit line 150a are connected in series one group of vertical type accumulation layer 140 along second direction, and many second bit line 150b are parallel with the first bit line 150a, are connected in series another group vertical type accumulation layer 140, wherein first direction and second direction quadrature in fact.
See also Fig. 4 again, the phase-change memory array of one embodiment of the invention has an array of transistor elements, as current controling element, with its corresponding conductive plug 130 contrast expressions.Array of transistor elements comprises one first group transistor array and one second group transistor array.First group of time transistor array is positioned at that (m, n) on the position of grid point, second group transistor array is positioned at that (m+1/2, n+1/2) on the position of grid point, wherein m, n are integer.More particularly, first group transistor array becomes (1/2,1/2) translation symmetry with second group transistor array.
Fig. 5 A-14B is the schematic diagram of demonstration according to each step of manufacture method of the phase-change memory array of first embodiment of the invention.At first, provide a substrate 110, comprise the semiconductor substrate of any pattern, on substrate, have a current controling element array.The control end of each current controling element (for example grid) is with many parallel word lines series connection, with and output respectively connect a conductive plug 130.Current controling element comprises transistor unit, for example metal-oxide-semiconductcor field effect transistor (MOSFET), PN junction diode (PN junction diode) and bipolar junction transistor (BJT).Fig. 5 A, 5B have the plane and the generalized section of metal-oxide-semiconductcor field effect transistor (MOSFET) array respectively on the display base plate 110, and MOS transistor has grid 120, source electrode 122 and drain electrode 124.Fig. 6 A, 6B have the plane and the generalized section of bipolar junction transistor (BJT) array respectively on the display base plate 110.Bipolar junction transistor (BJT) comprises pnp-transistor npn npn or npn-transistor npn npn, and each represents its three electrodes with label 222,224,226.
Have one first dielectric layer 115 on substrate 110, conductive plug 130 is arranged in first dielectric layer 115.
Fig. 7 A-9C shows the schematic diagram of formation vertical type electrode structure step on substrate of first embodiment of the invention respectively.See also Fig. 7 A-7C, form one second dielectric layer 132 on first dielectric layer 115, its along the profile of hatching 7A-7A shown in Fig. 7 B, and carry out photoengraving and carve step patterning second dielectric layer 132, to form a plurality of openings 133, corresponding each conductive plug 130 that also exposes, its along the profile of hatching 7A-7A shown in Fig. 7 C.The pattern of opening 133 can be arbitrary shape, and is for example square.
Then, see also Fig. 8 A-8B, compliance deposition the first metal layer 135 on second dielectric layer 132 and opening 133, its along the profile of hatching 8A-8A shown in Fig. 8 B.The first metal layer 135 can utilize the deposit metal films technology to form, for example sputtering method, physical vaporous deposition or chemical vapour deposition technique.The material of the first metal layer 135 for example is that dystectic electric conducting material constitutes, and comprises alloy, nitride, carbide or the nitrogen carbide of transition metal, thulium or above-mentioned metallic element.
See also Fig. 9 A-9C, deposit one the 3rd dielectric layer 136 on the first metal layer 135 and fill up opening 133, shown in Fig. 9 A.Then, impose planarisation step, for example with chemical mechanical milling method (CMP) remove the 3rd dielectric layer 136 and the first metal layer 135 until the surface of exposing second dielectric layer 132 shown in Fig. 9 B, to form a square metal wall construction 135, as the vertical type electrode structure of Ovonics unified memory, shown in Fig. 9 C.
Figure 10 A-12B shows the schematic diagram of formation vertical type accumulation layer step on the vertical type electrode structure of first embodiment of the invention respectively.See also Figure 10 A-10C, form one the 4th dielectric layer 138 on the 3rd dielectric layer 132, its along the profile of hatching 10A-10A shown in Figure 10 B.Then, patterning the 4th dielectric layer 138 is to form an island structure, and its pattern can be arbitrary shape, and is for example square, its along the profile of hatching 10A-10A shown in Figure 10 C.Island structure is formed on the square metal wall construction 135, and is arranged at a corner of square metal wall construction 135.
See also Figure 11 A-11C, compliance forms one second metal level 140 on the 4th dielectric layer 138 and the 3rd dielectric layer 136, its along the profile of hatching 11A-11A shown in Figure 11 B.Then, impose anisotropic etch-back step e, remove part second metal level, forming a clearance wall metal structure on the sidewall of square island structure 138, its along the profile of hatching 11A-11A shown in Figure 11 C.Second metal level 140 is made of a phase change storage medium, reaches the effect of storage by the state of control generation phase.The phase change storage medium comprises the alloy of III, IV, V, VI family metallic element or above-mentioned metallic element.
See also Figure 12 A-12B, two subtend clearance walls, 142 insulatings with parallel second direction, the two subtend clearance wall structures 140 that keep parallel first direction are second metal level, respectively as the one first vertical type accumulation layer 140a and the one second vertical type accumulation layer 140b of Ovonics unified memory, shown in Figure 12 A.According to another embodiment of the present invention, the step of clearance wall 142 insulatings is comprised with tilted direction ion implantation I, with the both sides tilted direction two subtend clearance walls of parallel second direction are injected oxygen or nitrogen ion, make its insulating, its along the profile of hatching 12B-12B ' shown in Figure 12 B.
Two subtend metal gap wall construction 140a and 140b respectively are single face metal wall structure independently, as the vertical type accumulation layer.Vertical type accumulation layer 140a, 140b and vertical type electrode structure about in the of 135 upright form stack and contact respectively at contact point, as phase change memory cell.According to another embodiment of the present invention, vertical type electrode structure 135 uprightly intersects with the thickness face with vertical type accumulation layer 140a, 140b, and its cross angle comprises vertical or non-perpendicular.
Figure 13 A-14B shows that respectively the formation bit line of first embodiment of the invention connects the schematic diagram of vertical type accumulation layer step.See also Figure 13 A-13C, deposit one the 5th dielectric layer 146 in the 4th dielectric layer 132 and vertical type accumulation layer 140a, 140b is last and with its planarization, its along the profile of hatching 13A-13A shown in Figure 13 B.
Then, impose the photoetching etching step, patterning the 5th dielectric layer 146 to be forming many parallel grooves 147 along second direction, and exposes vertical type accumulation layer 140a, 140b, its along the profile of hatching 13A-13A shown in Figure 13 C.
See also Figure 14 A-14B, deposit one the 3rd metal level 150 on the 5th dielectric layer 146, and insert groove 147.Then, impose the photoetching etching step, patterning the 3rd metal level 150 becomes many leads along second direction, and (bit line, BL), it along the profile of hatching 14A-14A as shown in Figure 14B as the bit line of phase-change memorizer device.
Figure 15 A-19C is the schematic diagram of demonstration according to each step of manufacture method of the phase-change memory array of second embodiment of the invention.The manufacture method of the phase-change memory array of second embodiment of the invention is identical with Fig. 5 A-9C step of the phase-change memory array of first embodiment, for simple and clear event, omits identical narration at this.The different formation steps that are in the vertical type accumulation layer.
Figure 15 A-17C shows the schematic diagram of formation vertical type accumulation layer step on the vertical type electrode structure of second embodiment of the invention respectively.See also Figure 15 A-15C, form one the 4th dielectric layer 246 on the 3rd dielectric layer 132, its along the profile of hatching 15A-15A shown in Figure 15 B.Then, along second direction patterning the 4th dielectric layer 246 to form many parallel long bar shaped island structures 246.Each strip island structure along second direction across on each vertical type electrode structure 135, its along the profile of hatching 15A-15A shown in Figure 15 C.
See also Figure 16 A-16C, form one the 5th dielectric layer 238 on the 3rd dielectric layer 132 and the 4th dielectric layer 246 (strip island structure), the 5th dielectric layer 238 has higher rate of etch than the 4th dielectric layer 246, and with 238 planarizations of the 5th dielectric layer, its along the profile of hatching 16A-16A shown in Figure 16 B.Then, form a top metal level 240 on the 5th dielectric layer 238.Etching top metal level 240 and the 5th dielectric layer 238 in regular turn, to be patterned to an island structure, its pattern can be arbitrary shape, and is for example square.Island structure forms a corner with respect to square metal wall construction 135, its along the profile of hatching 16A-16A shown in Figure 16 C.
See also Figure 17 A-17C, compliance forms one second metal level 140 on top metal level 240 (island structure) and the 4th dielectric layer 246 (strip island structure), its along the profile of hatching 17A-17A shown in Figure 17 B.Then, impose anisotropic etch-back step e, remove part second metal level 140, forming a clearance wall metal structure around square island structure on the sidewall, its along the profile of hatching 17A-17A shown in Figure 17 C.Second metal level 140 is to be made of a phase change storage medium, reaches the effect of storage by the state of control generation phase.The phase change storage medium comprises the alloy of III, IV, V, VI family metallic element or above-mentioned metallic element.
Between second metal level 140 ' and vertical type electrode structure of two subtend clearance walls of parallel second direction, because of every being electrically insulated with the 4th dielectric layer 246 (strip island structure), and second metal level 140 of two subtend clearance walls of parallel first direction "; respectively as the first vertical type accumulation layer and the second vertical type accumulation layer of Ovonics unified memory, shown in Figure 17 A.
Figure 18 A-19C shows that respectively the formation bit line of second embodiment of the invention connects the schematic diagram of vertical type accumulation layer step.See also Figure 18 A-18C, deposit one the 6th dielectric layer 256 on top metal level 240 (island structure) and the 4th dielectric layer 246 (strip island structure), and with its planarization, its along the profile of hatching 18A-18A shown in Figure 18 B.
Then, impose the photoetching etching step, patterning the 6th dielectric layer 256 exposes top metal level 240 to form a plurality of contact holes 257, its along the profile of hatching 18A-18A shown in Figure 18 C.
See also Figure 19 A-19C, deposition-Di three metal levels 150 and are inserted contact hole 257 and are formed contact bolts 258 on the 6th dielectric layer 256.Then, impose the photoetching etching step, patterning the 3rd metal level 150 becomes many leads along second direction, and it is along profile such as Figure 19 B and Figure 19 C of hatching 19A-19A, as the bit line of phase-change memorizer device (bit line, BL).
Figure 20 is the schematic diagram of demonstration according to the same attitude of the phase-change memory array of the embodiment of the invention.See also Figure 20, a phase-change memory array, the square formation that is constituted with four Ovonics unified memory M11-M22 for example, each Ovonics unified memory is all the pattern of a transistor memory cell of collocation (1T-1R).The transistor of each Ovonics unified memory connects vertical type electrode structure 135 through a conductive plugs 130.One vertical type accumulation layer 140 and vertical type electrode structure about in the of 135 upright form stack and in 145 contact points as phase change memory cell.Word line 120 is connected in series each transistor and bit line 150 second directions are connected in series each vertical type accumulation layer 140 along first direction.
Figure 21 is the schematic diagram that shows according to another sample attitude of phase-change memory array of the embodiment of the invention.See also Figure 21, a phase-change memory array, the square formation that is constituted with four Ovonics unified memory M11-M22 for example, each Ovonics unified memory is all the pattern of transistor two memory cell of collocation (1T-2R).The transistor of each Ovonics unified memory connects vertical type electrode structure 135 through a conductive plugs 130.One first vertical type accumulation layer 140a and vertical type electrode structure about in the of 135 upright form stack, and in contact point 145a as first phase change memory cell.The second vertical type accumulation layer 140b and vertical type electrode structure about in the of 135 upright form stack, and in contact point 145b as second phase change memory cell.Word line 120 is connected in series each transistor along first direction.The first bit line 150a is along each first vertical type accumulation layer 140a of second direction serial connection, and the second bit line 150b is along each second vertical type accumulation layer 140b of second direction serial connection.
Figure 22 is the schematic diagram that shows according to another sample attitude of phase-change memory array of the embodiment of the invention.See also Figure 22, a phase-change memory array, for example with four Ovonics unified memory M11-M22 and the staggered square formation that is constituted of Ovonics unified memory N11, each Ovonics unified memory is all the pattern of transistor two memory cell of collocation (1T-2R).The transistor of each Ovonics unified memory connects vertical type electrode structure 135 through a conductive plugs 130.One first vertical type accumulation layer 140a and vertical type electrode structure about in the of 135 upright form stack, and in contact point 145a as first phase change memory cell.The second vertical type accumulation layer 140b and vertical type electrode structure about in the of 135 upright form stack, and in contact point 145b as second phase change memory cell.Word line 120 is connected in series each transistor along first direction.The first bit line 150a is along each first vertical type accumulation layer 140a of second direction serial connection, and the second bit line 150b is along each second vertical type accumulation layer 140b of second direction serial connection.
Phase-change memory array comprises one first group transistor array (corresponding to the position of conductive plugs 130a-130d) and one second group transistor array (corresponding to the position of conductive plugs 130e).First group of time transistor array is positioned at that (m, n) on the position of grid point, second group transistor array is positioned at that (m+1/2, n+1/2) on the position of grid point, wherein m, n are integer.More particularly, first group transistor array becomes (1/2,1/2) translation symmetry with second group transistor array.
[feature of the present invention and advantage]
Feature of the present invention and advantage are to utilize vertical type electrode structure and vertical type phase change means of storage, dwindle the contact area of phase change memory cell, and utilize a transistor two phase change memory cell structures (1T-2R structure) of arranging in pairs or groups, reach and dwindle the effect that the memory element unit are promptly increases integrated level.Moreover, with two transistors time array collocation 1T-2R memory cell structure, can further increase the integrated level of Ovonics unified memory.
Though the present invention discloses as above with embodiment; right its is not in order to limiting scope of the present invention, anyly has the knack of this skill person, without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention is as the criterion when looking appended the claim person of defining.
Claims (37)
1. phase-change memorizer device comprises:
Current controling element is arranged on the substrate;
The vertical type electrode structure is electrical connected with this current controling element; And
The first vertical type accumulation layer stacks and contacts in first make contact with upright form about this vertical type electrode structure, and wherein the first make contact of this vertical type electrode structure and this first vertical type accumulation layer intersection is as first phase change memory cell.
2. phase-change memorizer device as claimed in claim 1, wherein this vertical type electrode structure is the metal wall structure.
3. phase-change memorizer device as claimed in claim 2, wherein this first vertical type accumulation layer is the single face metal wall.
4. phase-change memorizer device as claimed in claim 1, wherein this vertical type electrode structure uprightly intersects with the thickness face with this first vertical type accumulation layer, and its cross angle comprises vertical or non-perpendicular.
5. phase-change memorizer device as claimed in claim 2, wherein this vertical type electrode structure is made of dystectic electric conducting material, comprises alloy, nitride, carbide or the nitrogen carbide of transition metal, thulium or above-mentioned metallic element.
6. phase-change memorizer device as claimed in claim 3, wherein this first vertical type accumulation layer is made of the phase change storage medium, reaches the effect of storage by the state of control generation phase.
7. phase-change memorizer device as claimed in claim 6, wherein this phase change storage medium comprises the alloy of III, IV, V, VI family metallic element or above-mentioned metallic element.
8. phase-change memorizer device as claimed in claim 1, wherein this current controling element is a transistor unit.
9. phase-change memorizer device as claimed in claim 2, also comprise the second vertical type accumulation layer, stack and contact in second contact point with upright form about this vertical type electrode structure, wherein this second contact point of this vertical type electrode structure and this second vertical type accumulation layer intersection is as second phase change memory cell.
10. phase-change memorizer device as claimed in claim 9, wherein this second vertical type accumulation layer is the single face metal wall.
11. phase-change memorizer device as claimed in claim 9, wherein this vertical type electrode structure uprightly intersects with the thickness face with this second vertical type accumulation layer, and its cross angle comprises vertical or non-perpendicular.
12. phase-change memorizer device as claimed in claim 10, wherein this second vertical type accumulation layer is made of the phase change storage medium, reaches the function of storage by the state of control generation phase.
13. phase-change memorizer device as claimed in claim 12, wherein this phase change storage medium comprises the alloy of III, IV, V, VI family metallic element or above-mentioned metallic element.
14. phase-change memorizer device as claimed in claim 9, wherein this first vertical type accumulation layer is connected to two different leads respectively with the second vertical type accumulation layer, and wherein each lead corresponding to the bit line of this phase-change memorizer device.
15. phase-change memorizer device as claimed in claim 1 also comprises:
The array that a plurality of these first phase change memory cells are constituted, the array that corresponding a plurality of this current controling element is constituted is on this substrate;
Many word lines are connected in series each current controling element along first direction; And
Multiple bit lines, along each first vertical type accumulation layer of second direction serial connection,
This first direction and this second direction quadrature in fact wherein.
16. phase-change memorizer device as claimed in claim 9 also comprises:
The array that a plurality of these first phase change memory cells and this second phase change memory cell are constituted, the array that corresponding a plurality of this current controling element is constituted is on this substrate;
Many word lines are connected in series each current controling element along first direction;
Many first bit lines are along each first vertical type accumulation layer of second direction serial connection; And
Many second bit lines, along each second vertical type accumulation layer of this second direction serial connection, this first direction and this second direction quadrature in fact wherein.
17. phase-change memorizer device as claimed in claim 16, wherein the array that this a plurality of current controling element constituted comprises first group transistor array and second group transistor array.
18. phase-change memorizer device as claimed in claim 17, wherein this first group transistor array becomes (1/2,1/2) translation symmetry with this second group transistor array.
19. the manufacture method of a phase-change memorizer device comprises:
Substrate is provided, has current controling element thereon;
Form the vertical type electrode structure on this substrate, and be electrical connected with this current controling element; And
Form the vertical type accumulation layer on this vertical type electrode structure, and stack as phase change memory cell with upright form.
20. the manufacture method of phase-change memorizer device as claimed in claim 19, wherein this current controling element is a transistor unit.
21. the manufacture method of phase-change memorizer device as claimed in claim 19, wherein this substrate comprises that also first dielectric layer and conduction are bolted in this first dielectric layer, and wherein this conductive plugs electrically connects this current controling element and vertical type electrode structure.
22. the manufacture method of phase-change memorizer device as claimed in claim 21, the step that wherein forms this vertical type electrode structure comprises:
Form second dielectric layer on this first dielectric layer;
This second dielectric layer of patterning exposes this conductive plugs to form square aperture;
Compliance deposition the first metal layer is on this second dielectric layer and this square aperture;
Deposit the 3rd dielectric layer on the first metal layer and fill up this square aperture;
Planarization the 3rd dielectric layer and this first metal layer are until the surface of exposing this second dielectric layer, to form the metal wall structure.
23. the manufacture method of phase-change memorizer device as claimed in claim 22, wherein this first metal layer is made of dystectic electric conducting material, comprises alloy, nitride, carbide or the nitrogen carbide of transition metal, thulium or above-mentioned metallic element.
24. the manufacture method of phase-change memorizer device as claimed in claim 22, the step that wherein forms this vertical type accumulation layer structure comprises:
Form the 4th dielectric layer on the 3rd dielectric layer;
Patterning the 4th dielectric layer is to form square island structure;
Compliance forms second metal level on the 4th dielectric layer and the 3rd dielectric layer;
This second metal level of anisotropic etch-back is to form the clearance wall structure on this square island structure; And
With two subtend clearance wall insulatings of parallel first direction, the two subtend clearance wall structures that keep parallel second direction are this second metal level, respectively as the first vertical type accumulation layer and the second vertical type accumulation layer.
25. the manufacture method of phase-change memorizer device as claimed in claim 24, wherein this second metal level is made of the phase change storage medium, reaches the effect of storage by the state of control generation phase.
26. the manufacture method of phase-change memorizer device as claimed in claim 25, wherein this phase change storage medium comprises the alloy of III, IV, V, VI family metallic element or above-mentioned metallic element.
27. the manufacture method of phase-change memorizer device as claimed in claim 24 wherein comprises the step of two subtend clearance wall insulatings of parallel first direction with ion implantation and injects the two subtend clearance walls insulation that oxygen or nitrogen ion make parallel first direction.
28. the manufacture method of phase-change memorizer device as claimed in claim 24 also comprises along second direction forming first bit line, connects this first vertical type accumulation layer, and forms second bit line, connects this second vertical type accumulation layer.
29. the manufacture method of phase-change memorizer device as claimed in claim 28, the step that wherein forms this first bit line and this second bit line comprises:
Deposit the 5th dielectric layer on the 4th dielectric layer and with its planarization;
Etching the 5th dielectric layer to be forming first groove and second flute along second direction, and exposes this first vertical type accumulation layer and the second vertical type accumulation layer;
Deposit the 3rd metal level in the 5th dielectric layer and insert this first groove and this second flute; And
Etching the 3rd metal level becomes this first bit line and this second bit line.
30. the manufacture method of phase-change memorizer device as claimed in claim 22, the step that wherein forms this vertical type accumulation layer structure comprises:
Form the 4th dielectric layer on the 3rd dielectric layer;
Patterning the 4th dielectric layer is to form the strip island structure along first direction;
Form the 5th dielectric layer on the 3rd dielectric layer and the 4th dielectric layer, and with the 5th dielectric layer flatening;
Form the top metal level on the 5th dielectric layer;
This top metal level of patterning and the 5th dielectric layer are to form square island structure;
Compliance forms second metal level on this top metal level and the 4th dielectric layer; And
This second metal level of anisotropic etch-back is to form the clearance wall structure on this square island structure;
Wherein between this second metal level of two subtend clearance walls of parallel first direction and this vertical type electrode structure every insulating with this strip island structure, and this second metal level of two subtend clearance walls of parallel second direction, respectively as the first vertical type accumulation layer and the second vertical type accumulation layer.
31. the manufacture method of phase-change memorizer device as claimed in claim 30, wherein this second metal level is made of the phase change storage medium, reaches the effect of storage by the state of control generation phase.
32. the manufacture method of phase-change memorizer device as claimed in claim 31, wherein this phase change storage medium comprises the alloy of III, IV, V, VI family metallic element or above-mentioned metallic element.
33. the manufacture method of phase-change memorizer device as claimed in claim 30 also comprises along second direction forming first bit line, connects this first vertical type accumulation layer, and forms second bit line, connects this second vertical type accumulation layer.
34. the manufacture method of phase-change memorizer device as claimed in claim 33, the step that wherein forms this first bit line and this second bit line comprises:
Deposit the 6th dielectric layer on the 5th dielectric layer and with its planarization;
Etching the 6th dielectric layer exposes this top metal level to form a plurality of contact holes;
Deposit the 3rd metal level on the 6th dielectric layer and insert this a plurality of contact holes, to form a plurality of contact bolts; And
Become multiple bit lines along second direction etching the 3rd metal level.
35. the manufacture method of a phase-change memorizer device comprises:
Substrate is provided, has the array that a plurality of current controling element constitutes and be connected in series each current controling element along first direction with many word lines;
Form the vertical type electrode structure on this substrate in corresponding each current controling element place, and be electrical connected with this current controling element;
Form the first vertical type accumulation layer and this vertical type electrode structure up and down upright form stack and contact in first make contact, as second phase change memory cell; And
Form the second vertical type accumulation layer and this vertical type electrode structure up and down upright form stack and contact in second contact point, wherein this second contact point of this vertical type electrode structure and this second vertical type accumulation layer intersection is as second phase change memory cell, and in parallel with this first phase change memory cell.
36. the manufacture method of phase-change memorizer device as claimed in claim 35, wherein this array comprises first group transistor array and second group transistor array.
37. the manufacture method of phase-change memorizer device as claimed in claim 36, wherein this first group transistor array becomes (1/2,1/2) translation symmetry with this second group transistor array.
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| CNA200710112002XA CN101330091A (en) | 2007-06-19 | 2007-06-19 | Phase-changing storage device and manufacture method thereof |
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| CNA200710112002XA CN101330091A (en) | 2007-06-19 | 2007-06-19 | Phase-changing storage device and manufacture method thereof |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107636833A (en) * | 2015-05-14 | 2018-01-26 | 美光科技公司 | The cross point memory array of memory construction and its correlation, electronic system and the method for forming memory construction |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107636833A (en) * | 2015-05-14 | 2018-01-26 | 美光科技公司 | The cross point memory array of memory construction and its correlation, electronic system and the method for forming memory construction |
| CN107636833B (en) * | 2015-05-14 | 2019-03-01 | 美光科技公司 | Memory construction and its relevant cross point memory array, electronic system and the method for forming memory construction |
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