CN101325084B - Method for providing dynamic voltage off-set for decussation type memory array and implementing circuit thereof - Google Patents
Method for providing dynamic voltage off-set for decussation type memory array and implementing circuit thereof Download PDFInfo
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Abstract
The invention belongs to the integrated circuit technology field, and particularly relates to a method for providing dynamic bias voltage for a cross-shaped resistance conversion type storage unit array. A cross-type storage array performs the selecting operation through electrical signals applied to two crossed metal wires. The method can dynamically generate the bias voltage applied on the other non-operational metal wire pairs according to the difference in the resistance distribution condition of the array and the additional operation signals, so as to allow the resistance conversion type storage unit cross-shaped array with higher ratio between a high impedance state and a low impedance state to be reliably operated.
Description
Technical field
The invention belongs to the large-scale digital ic technical field, be specially a kind of method and realization circuit thereof that the resistive storage array of chiasma type is provided the dynamic electric voltage biasing.
Background technology
Storer occupies an important position in semi-conductor market, and only DRAM (Dynamic Random Access Memory) and FLASH just account for 15% of market for two kinds, and along with constantly popularizing of portable electric appts, nonvolatile memory market is also increasing.Yet the size of traditional nonvolatile memory is near its physics limit, and the limit that report prediction FLASH technology is arranged is about 32nm, and this just forces people to seek the more superior nonvolatile memory of future generation of performance.The resistance conversion hysteria can read memory device (RRAM at random recently, resistive random access memory) because its high density, low-power consumption, cheaply characteristics cause show great attention to the SrZrO3[2 that employed material has phase-change material [1], mixes], ferroelectric material PbZrTiO3[3], ferromagnetic material Prl-xCaxMnO3[4], binary metal oxide material [5], organic material [6] etc.
The 1T1R structure of the structure that present resistance conversion hysteria memory device mainly adopts, promptly a gating device (as diode, triode, field effect transistor etc.) and a memory resistor constitute a storage unit.This storage unit has simple in structure, disturb between the unit little, advantage such as reading speed is fast, and periphery circuit design is simple, thereby be widely adopted.Fig. 1 shows the storage array that this 1T1R unit is constituted.Yet for highdensity mass memory, the cellular construction of 1T1R has really limited the further raising of storage density again, following two reasons are arranged: 1) as a rule transistor area is greater than the area of memory resistor, thereby storage density is subjected to the restriction of transistor area; 2) gate transistor owing to each storage unit all will consume the area of silicon chip and memory resistor can't be carried out the stacked three-dimensional storage array that forms.
At above two problems, a more satisfactory solution can be made reliable chiasma type (cross-point) storage array exactly.Chiasma type (cross-point) storage array is meant there is not gating device in the storage unit, and memory resistor is positioned at the place that two metal line are intersected, by two cross one another metal wires are added different voltage, to the memory resistor implementation and operation of infall.Be illustrated in figure 2 as the storage array figure of chiasma type.
The critical problem of design chiasma type (cross-point) storage array is exactly the influence that can reduce leakage current by the design of peripheral circuit.Because for the resistive storage array of chiasma type, actual is to have constituted an ohmic network, and this network has complicated leakage current path, therefore can produce very big undesired signal, influences the function correctness of storage array operation.
For the chiasma type storage array, in order to reduce the influence of leakage current, common way provides the bias voltage Veq[7 of clamp], the effect of this bias voltage is to make non-selected storage unit two ends keep the current potential that equates, thus the path of limit leakage current.In traditional realization, fixing value of the general employing of the bias voltage of this clamp, modal is V/2 and V/3 bias scheme [8], and the bias voltage of fixed size is difficult to the variation of adaptive and institute's add operation signal of adaptation array, so can't guarantee the reliably working of chiasma type storage array.
The present invention proposes provides dynamic bias voltage to the chiasma type storage array, it is characterized in that voltage bias can regulate according to the residing state of each resistance in the array and the operation signal that adds, and makes bias voltage Veq obtain optimal value.Such dynamic bias scheme can guarantee that the chiasma type storage array works reliably.
Summary of the invention
The objective of the invention is to propose a kind of method that the chiasma type storage array is provided the dynamic electric voltage biasing.The situation that this dynamic bias voltage can distribute according to array resistors and add operation signal and dynamically adjust enables to restrain leakage current with the size of the best, improves the reliability of chiasma type storage array work.The realization circuit of this dynamic electric voltage biasing also is provided simultaneously.
What the present invention proposed provides the method for dynamic electric voltage biasing to the chiasma type storage array, comprises the chiasma type storage array that adopts dynamic bias and two parts of algorithm of generation dynamic bias voltage.Wherein, the unit of the chiasma type storage array of described dynamic bias is made of resistance conversion hysteria storage medium.In this array, adopt the algorithm that produces dynamic bias voltage to obtain dynamic bias voltage.Algorithm selects the electric current of bit line to sample by when operation to flowing into storage array, produces dynamic biasing according to the signal of being sampled.This algorithm can be sought the optimum value of dynamic bias effectively.Concrete steps are as follows:
(1) apply voltage Vread earlier on the bit line that storage array is selected, voltage Vread size is 1V～5V;
(2) apply dynamic bias voltage Veq on the bit line in non-selected word line and non-choosing, the initial value of Veq voltage is zero;
(3) sampling flows into the electric current on the selected bit line, if this electric current is non-vanishing, then voltage Veq is added a little step value Δ Veq, repeats for (2) step; If this electric current approaches zero, then continue next step; Here generally getting Δ Veq is 0.01V～0.05V;
(4) voltage Veq is produced a little side-play amount, be applied to non-selected word line and the non-bit line of choosing; The size of this side-play amount is generally 0.1V～0.2V;
(5) judge the state of selected storage unit according to flowing into electric current on the bit line.
The present invention proposes a kind of scheme that designs the chiasma type electric resistance transition memory.This scheme can be applied to the resistor conversion memory unit that the binary states resistance differs greatly.
Description of drawings
Fig. 1 adopts the storage array of 1T1R (gating device and a memory resistor) cellular construction.
Fig. 2 chiasma type resistance converting storage array.
Parasitic leakage circulation flow path in Fig. 3 chiasma type resistance converting storage array.
The peripheral circuit diagram of Fig. 4 chiasma type electric resistance transition memory.
The read operation clamp bias scheme of Fig. 5 chiasma type resistance converting storage array.
Figure is implemented in the read operation of Fig. 6 chiasma type resistance converting storage array.
Fig. 7 chiasma type resistance converting storage array read operation signal noise analogous diagram.
The dynamic bias of Fig. 8 chiasma type resistance converting storage array produces algorithm.
The logic diagram of the dynamic offset generating circuit of Fig. 9 chiasma type resistance converting storage array.
Figure 10 produces a kind of embodiment of dynamic bias voltage.
Figure 11 uses the read operation current simulations of the chiasma type resistance converting storage array of dynamic bias scheme.
Embodiment
Hereinafter more specifically describe the present invention, the invention provides preferred embodiment, but should not be considered to only limit to embodiment set forth herein in conjunction with diagram and reference example.
At this reference diagram is the synoptic diagram of idealized embodiment of the present invention, and embodiment shown in the present should not be considered to only limit to the given shape in the zone shown in the figure.
Should be appreciated that when claiming an element when " on another element " or " on another element, extending ", this element can be directly at " on another element " or directly " on another element, extending ", or also may have insertion element.On the contrary, when claiming an element " directly on another element " or " directly on another element, extending ", there is not insertion element.When claiming an element with " another element is connected " or " coupling with another element ", this element can directly connect or be couple to another element, also can have insertion element.On the contrary, when claiming an element, there is not insertion element directly with " another element is connected " or direct " coupling " with another element.
Fig. 1 shows the resistance converting storage array that adopts the 1T1R cellular construction.Storage unit is made of a programmable resistance 120 and 1 gating device 100.Gating device 100 can be a diode as shown in the figure, also can be the device that metal-oxide-semiconductor, bipolar transistor etc. have on-off action.In this storage array, can keep apart mutually by gating device between the storage unit, thereby reduce interference between the unit.For example operation 120 o'clock, having only gating device 100 was conductings, and remaining gating device all turn-offs, and the electric signal that so just has only memory resistor 120 to be added acts on.
Fig. 2 shows the resistive conversion memory unit array of chiasma type (cross-point).Storage unit 120 is connected between plain conductor 200 and 210.Storage unit in location, place that plain conductor (200～201) and plain conductor (210～213) intersect.With operation store unit 120 is example, need apply different voltage signals on plain conductor 200 and 210, and two electric signal act on simultaneously, just can operate accordingly it.For the unit (as 121) that does not need in the array to operate, wish the influence that it is not subjected to electric signal, preserve original state.Yet, wherein exist the path of some parasitic leakage currents because these resistive storage unit constitute an ohmic network.Parasitic leakage fails to be convened for lack of a quorum the performance of storer is seriously descended, even produces wrong operation, can show as: 1) misread out, because the influence of leakage current makes other sensitive flourishing device can not correctly distinguish the state of memory resistor; 2) mistake writes, and leakage current makes its state that undesirable upset take place to the effect of unchecked unit.
Fig. 3 shows the parasitic leakage circulation flow path that may exist in the storage array of chiasma type.Storage unit 300 is the unit that need operation, applies driving voltage 330 on corresponding metal lead 311, simultaneously with plain conductor 321 ground connection.At this moment, the voltage swing at storage unit 300 two ends equals driving voltage.Yet in this resistive network, exist from 311 to 321 parasitic current path, shown in dotted line 350.This sneak path flows to ground through resistance 300, lead 320, resistance 302, resistance 303 until pass through lead 321.Suppose that the memory resistor of selecting 300 is high resistant, and unfortunately resistance 301,302,303 is low-resistance, this leakage current is very big to the influence of operating current so, even can influence normal work.If what apply is read operation to 300, so resulting electric current is actually and flows through 300 electric current and leakage current sum, thereby can not represent 300 resistance states.If what apply is write operation to 300, but memory resistor 301～302 also can be passed through bigger electric current or voltage signal, thereby their state is deflected.
Fig. 4 shows the system circuit diagram of chiasma type array memory.450～453 for constituting the resistance conversion hysteria storage unit of storage array, effect when they are subjected to word line circuit (400,401) and bit line circuit (420,421).Wherein the effect of word line circuit (400,401) is to import according to row address.Need to select the row of operation, and provide biasing Veq (410,411) the row that does not need to operate.Bit line circuit (421,422) is the row that the needs operation is selected in input according to column address, and input selects needs to be added in the electric signal of selecting on the bit line according to data.Sense amplifier 440 is used to read the resistance states of selected resistive memory cell.Owing in the chiasma type storage array, have bigger leakage current, so sense amplifier must be able to be eliminated the influence of leakage current.
Fig. 5 illustrates the bias scheme for the read operation of chiasma type storage array.VBLsel 500 is to the voltage bias of selecting bit line to apply, and VWLsel 510 is to selecting the voltage bias of word line, equaling earth potential.The voltage bias that non-selected bit line is applied is Veqb (520～524), and the voltage bias that non-selected word line is applied is Veqw (511～514).As we know from the figure, added voltage signal equals Vblsel 500 on the memory resistor of selection operation, and equals Veqb for the voltage signal at the memory resistor two ends on non-selection bit line and selected word line point of crossing.The voltage signal at other memory resistor two ends in the array then equals (Veqb-Veqw).The read operation of resistance conversion hysteria storage unit is by applying certain voltage on storage unit, distinguishing the size of its electric current then, so will reduce the influence of leakage current to marking current as far as possible.Desirable a kind of bias mode is to select Veqw=Veqb=VBLsel.In this case, equal to flow through the electric current of the memory resistor of choosing in theory from the electric current of selecting bit line to flow through, also have electric current to flow through in the memory resistor of selected word line and non-selected word line infall, but do not influence the marking current of reading.Other then do not have electric current to flow through in non-selected word line and the non-memory resistor of bit line infall of choosing, because their two ends are clamped on the equal current potential.Yet because in array, sneak path is along with the change in resistance of each storage unit, not and because not the matching of the parameter of switching tube, and reason such as bit line resistance, a fixing Veq can not well play clamped effect, so in this patent, proposed to produce the thought of dynamic Veq, make Veq carry out dynamic oneself's adjustment according to resistor network situation and the operating voltage that applies, reduce the influence of leakage current as much as possible.
Fig. 6 shows the readout scheme of chiasma type storer.600 is clamping voltage, and its effect is the size of limit leakage current.610 is the memory resistor that need read, and its two ends are connected on plain conductor 632 and 643.Select by plain conductor 632 and 643 actings in conjunction.Add certain voltage on the plain conductor 632, and plain conductor 643 ground connection, so just formed by 632 to 643 path.Read current through memory resistor 610, flows to ground from plain conductor 632 then.Sense amplifier flows into 632 electric current by perception, judges the resistance states of the storage unit of selection.Switch in this programme (as 620) can replace with the metal-oxide-semiconductor of N type, has less conducting resistance in order to satisfy it, selects it to have bigger breadth length ratio.Veq (600) is clamped voltage, it make not the word line of gating (as 640) and not the bit line of gating (as 630) be biased in equal current potential.If the voltage bias that is added on the plain conductor 632 is certain, the electric current that flows into it so is along with Veq changes.
Fig. 7 shows the simulation result for 256 * 16 chiasma type array read operation among Fig. 6.In emulation, we have adopted such parameter: low resistance state resistance is 2k, and high-resistance resistors is 100k.Because the resistance of low resistance state is lower, so have many parasitic leakage current branch roads.Our emulation the leakage current situation under two kinds of situations, be respectively: the 1) situation of leakage current maximum, promptly all unselected storage unit all are in low resistance state; 2) situation of leakage current minimum, promptly all unselected storage unit all are positioned at high-impedance state.In both cases.We again respectively emulation the unit selected be the situation of high-impedance state and resistance state.Curve 800 and 810 has been represented to flow into the situation of change of the electric current of selected bit line and selected memory resistor with Veq situation 1 time.Curve 840 has been represented signal noise ratio, and promptly actual flow is crossed the electric current of memory resistor and the ratio of leakage current.Can obtain such rule from figure, signal noise ratio increases along with the increase of Veq, reaches maximal value when a certain value.This value is near the voltage of reading on the selected bit line.Simultaneously we find that also the electric current that flows into selected bit line reduces along with the increase of Veq, and to make the electric current that flows into selected bit line be the value of 0 o'clock Veq and the value of the Veq of signal to noise ratio (S/N ratio) maximum is very approaching.Simply introduce the implication of other several curves below again.801,811,841 correspondences is the situation that situation 1 little selected storage unit is a low-resistance.802,812,842 correspondences be the situation that 2 times selected storage unit of situation are high resistants, and 803,813,843 correspondences is that memory resistor is the situation of low-resistance.
Fig. 8 shows the rudimentary algorithm that produces dynamic Veq.According to the simulation result of Fig. 7, we have drawn such conclusion, if suitable Veq can be provided, can make signal noise ratio reach bigger value, thereby can tell the difference of high resistant and low-resistance, and minimize the influence of leakage current.Arthmetic statement is as follows:
(1) apply voltage Vread on the bit line that storage array is selected, the Vread size is between 1V～5V;
(2) apply dynamic bias voltage Veq on the bit line in non-selected word line and non-choosing, the initial value of Veq voltage is zero;
(3) sampling flows into the electric current on the selected bit line, if this electric current is non-vanishing, then voltage Veq is added a little step value Δ Veq, repeats for second step; If this electric current approaches zero, then continue next step; Here generally getting Δ Veq is 0.01V～0.05V;
(4) voltage Veq is produced a little side-play amount, be applied to non-selected word line and the non-bit line of choosing; The size of this side-play amount is generally 0.1V～0.2V;
(5) judge the state of selected storage unit according to flowing into electric current on the bit line.
Fig. 9 shows the logic diagram of circuit that produces dynamic Veq.An output terminal of reading voltage generating module 900 links to each other with current sample module 901, the latter's output simultaneously is connected to dynamic electric voltage Veq generation module 902, the end of path selector switch S1 or S2 links to each other with the output of dynamic electric voltage Veq generation module, and the other end links to each other with current sample module 901.By following we each circuit module is analyzed.Module 900 is to read voltage module, and the voltage of generation acts on the bit line of selection.Read voltage and can make electric current flow into selected bit line, current sample module 901 is sampled to this current signal.The signal that sampling produces is as the input of module 902, and module 902 produces bias voltage Veq according to this signal.The variation of bias voltage Veq can influence the size that flows into selected bit line current again.When this loop reached balance, bias voltage Veq can make the electric current that flows into selected bit line reach a very little value, and this moment, we claimed that this bias voltage Veq is balanced voltage Veq.When finding this equilibrium point, we carry out a little skew with bias voltage Veq, and then read the current value that flows into bit line.
Figure 10 shows an enforcement circuit diagram that produces dynamic bias.A size is that several ohm of sampling resistors 1000 to hundreds of ohm (as 5 ohm-500 ohm) are connected on the bit line, the one end with read voltage generating module and link to each other, the other end links to each other with the bit line of selection operation.Simultaneously, the two ends of sampling resistor 1000 are connected respectively to the source end (or drain terminal) of metal-oxide-semiconductor 1040a and 1040b, the drain terminal of metal-oxide-semiconductor 1040a and 1040b (or source end) then is connected to positive and negative two input ends of amplifier 1010, and their grid then is connected to control signal 1020.The output of amplifier 1010 is connected to the grid of PMOS pipe 1030, and the drain terminal of PMOS pipe links to each other with resistance 1031, is connected to the base stage and the collector of triode 1032 simultaneously, and the emitter of triode 1032 is connected to resistance 1033.The source end (or drain terminal) of metal-oxide-semiconductor 1041a is connected to the collector of triode 1032, and the source end (or drain terminal) of metal-oxide-semiconductor 1041b is connected to the emitter of triode 1032.The grid of metal-oxide-semiconductor 1041a and 1041b is connected to control signal 1021.Its principle of work is: read current is sampled by Rsample1000, the current potential at Rsample two ends is input to Ampl by S1 and S2 then, this charge storage of 2 is at C1 (1050_a), among the C2 (1050_b), be used at S1 (1040_a), S2 (1040_b) g closes the voltage difference of two input ends of hold amplifier of having no progeny.In the process of carrying out the searching of bias voltage Veq equilibrium point, the S3 conducting.When reaching balance, the Veq of generation makes read current trend towards 0, because it is big more to flow through the electric current of Rsample, then amplifier Ampl (1010) output terminal current potential is high more, and the electric current that then flows through R1 is more little, and output voltage V eq is also just more little so.Otherwise the electric current that flows through Rsample is big more, and then output voltage V eq is just high more.Because the enlargement factor of amplifier very big (100db) can make the electric current that flows through Rsample remain on a very little value so.When control signal Φ (1020) was low level, S1, S2, S3 be by, S4 conducting, skew 0.1V～0.2V when at this time Veq is than balance, and this side-play amount can obtain with a triode that works in dark saturation region.This moment, dynamic bias voltage Veq was by the output of S4 gating.When this bias voltage Veq was applied to storage array, read current will inevitably increase, but the signal noise ratio of this moment is an optimum value or near optimum value, because can correctly read the resistance states of select storage unit.
Figure 11 shows implementing the simulation result of circuit.Figure 11 (a) shows the variation of bias voltage Veq, promptly obtains read operation bias level 1101 by equilibrium point level (1100) by level deviation.Figure (b) shows read current 1120 and flows through the situation of change of the electric current 1121 of storage unit with Veq.Before the Veq skew, two electric currents are all very little, are tending towards 0.When Veq is offset, obtain effective read current.Can see that 1120 is 5.3 μ A, and 1121 be 0.7 μ A, signal noise ratio is 7, near optimal cases, can correctly distinguish the state of memory resistor.
List of references
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Claims (3)
1. one kind provides the method for dynamic electric voltage biasing to the chiasma type storage array, it is characterized in that concrete steps are as follows:
(1) at first apply voltage Vread on the bit line that storage array is selected, voltage Vread size is 1V～5V; The storage array here adopts the chiasma type storage array of dynamic bias;
(2) apply dynamic bias voltage Veq on the bit line in non-selected word line and non-choosing, the initial value of voltage Veq is zero;
(3) sampling flows into the electric current on the selected bit line, if this electric current is non-vanishing, then voltage Veq is added a little step value Δ Veq, repeats for (2) step; If this electric current approaches zero, then continue next step; Here getting Δ Veq is 0.01V～0.05V;
(4) voltage Veq is produced a little side-play amount, be applied to non-selected word line and the non-bit line of choosing; The size of this side-play amount is 0.1V～0.2V;
(5) judge the state of selected storage unit according to flowing into electric current on the bit line.
2. one kind as claimed in claim 1ly provides the realization circuit of dynamic electric voltage biasing means to the chiasma type storage array, it is characterized in that forming by reading voltage generating module, current sample module, dynamic electric voltage Veq generation module and path selector switch S1 and S2; Wherein reading the voltage generating module output terminal links to each other with the current sample module, the latter's output simultaneously is connected to dynamic electric voltage Veq generation module, the end of path selector switch S1 or S2 links to each other with the output of dynamic electric voltage Veq generation module, and the other end links to each other with the current sample module; The voltage of reading the voltage generating module generation acts on the bit line of selection, reads voltage and can make electric current flow into selected bit line, and the current sample module is sampled to this current signal; The signal that sampling produces is as the input of dynamic electric voltage Veq generation module, and dynamic electric voltage Veq generation module produces bias voltage Veq according to this signal, and the variation of bias voltage Veq can influence the size that flows into selected bit line current again; When this loop reaches balance, bias voltage Veq can make the electric current that flows into selected bit line reach a very little value, claim that this bias voltage Veq is balanced voltage Veq this moment, when finding this equilibrium point, bias voltage Veq is carried out a little skew, and then read the current value that flows into bit line.
3. realization circuit according to claim 2 is characterized in that sampling resistor is connected on the bit line, the one end with read voltage generating module and link to each other, the other end links to each other with the bit line of selection operation; Simultaneously, the two ends of sampling resistor are connected respectively to the source end or the drain terminal of two metal-oxide-semiconductors, and the drain terminal of described two metal-oxide-semiconductors or source end then are connected to positive and negative two input ends of amplifier, and their grid then is connected to a control signal; The output of described amplifier is connected to the grid of a PMOS pipe, the drain terminal of PMOS pipe links to each other with first resistance, be connected to the base stage and the collector of a triode simultaneously, the emitter of described triode is connected to second resistance, the collector that the source end of first metal-oxide-semiconductor or drain terminal are connected to above-mentioned triode, the emitter that the source end of second metal-oxide-semiconductor or drain terminal are connected to above-mentioned triode; The grid of above-mentioned first metal-oxide-semiconductor and second metal-oxide-semiconductor is connected to a control signal.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN2338914Y (en) * | 1998-03-20 | 1999-09-15 | 戴俊中 | Dynamic class A power amplifier |
| CN1636316A (en) * | 2002-02-21 | 2005-07-06 | 艾利森公司 | Dynamic bias controller for power amplifier circuits |
| US20060145729A1 (en) * | 2005-01-05 | 2006-07-06 | Louis Luh | High speed sample-and-hold circuit |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN2338914Y (en) * | 1998-03-20 | 1999-09-15 | 戴俊中 | Dynamic class A power amplifier |
| CN1636316A (en) * | 2002-02-21 | 2005-07-06 | 艾利森公司 | Dynamic bias controller for power amplifier circuits |
| US20060145729A1 (en) * | 2005-01-05 | 2006-07-06 | Louis Luh | High speed sample-and-hold circuit |
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