CN101324868B - Device for connecting processor and BOOT FLASH and implementing method - Google Patents
Device for connecting processor and BOOT FLASH and implementing method Download PDFInfo
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- CN101324868B CN101324868B CN200810068466XA CN200810068466A CN101324868B CN 101324868 B CN101324868 B CN 101324868B CN 200810068466X A CN200810068466X A CN 200810068466XA CN 200810068466 A CN200810068466 A CN 200810068466A CN 101324868 B CN101324868 B CN 101324868B
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- boot flash
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Abstract
The invention discloses a connecting device between a processor and a BOOT FLASH, and a realization method thereof. The connecting device comprises a bus logic processing unit, a controlling unit anda startup register; the startup register is used for storing the start identification of the BOOT FLASH; the controlling unit is used for monitoring the start identification and determines whether theBOOT FLASH is started successfully or not, and if so, a control signal for directly transmitting a bus signal is sent to the bus logic processing unit; and if not, a control signal which performs reversal processing to the data bus signal in the bus according to the byte order and then transmits the data bus signal is sent to the bus logic processing unit; the bus logic processing unit is connected with the processor in a default connection manner, and the corresponding connection manner can also be adopted for connection according to the byte order of the BOOT FLASH. The dynamic selection ofthe connection manner of the byte orders between the CPU with different byte orders and the BOOT FLASH can be realized, the method is simple, and the cost is lower.
Description
Technical field
The present invention relates to a kind of the have processor of different syllable sequences and coupling arrangement and its implementation between BOOT FLASH (startup flash memory).
Background technology
In the Embedded System Design field, no matter hardware design or software design, syllable sequence is the problem that must consider.So-called syllable sequence is exactly the order of byte, is the access sequence of data in storer greater than a byte type, and big end syllable sequence (big endian) and both modes of small end syllable sequence (little endian) are arranged.
Big end syllable sequence is the mode of byte align order during two above data of byte of storage in the storer with byte unit address, at this moment, begins address ascending order storage according to storer from the byte of big end MSB.Syllable sequence is putting in order of byte, rather than the putting in order of bit, and the bit arrangement order in the byte is constant.
Fig. 1 represents to hold greatly the key diagram of syllable sequence.As shown in the figure, with big end syllable sequence 4 byte datas " 0X12345678 " being stored in the address is under the 0X1000-0X1003 situation, according to the ascending order of address digit, stores " 12 ", " 34 ", " 56 ", " 78 " successively.Promptly the byte that begins from MSB (Most Significant Bit) side is stored in the storer according to the address ascending order.
Fig. 2 represents the general structure that the CPU (processor) of big end syllable sequence under the 32 bit data bus situations is connected with storer.As shown in the figure, the data bus D[31:24 of CPU], D[23:16], D[15:8], D[7:0] be connected respectively to the D[7:0 of storer], D[15:8], D[23:16], D[31:24] on.
The small end syllable sequence is meant from the byte of small end LSB (Least Significant Bit) and begins mode according to the address ascending order storage of storer.
Fig. 3 represents the key diagram of small end syllable sequence.As shown in the figure, with the small end syllable sequence 4 byte datas " 0X12345678 " being stored in the address is under the 0X1000-0X1003 situation, according to the ascending order of address digit, stores " 78 ", " 56 ", " 34 ", " 12 " successively.
Fig. 4 represents the general structure that small end syllable sequence CPU is connected with storer under the 32 bit data bus situations.As shown in the figure, the data bus D[7:0 of CPU], D[15:8], D[23:16], D[31:24] be connected respectively to the D[7:0 of storer], D[15:8], D[23:16], D[31:24] on.
Hold syllable sequence, small end syllable sequence that 2 data storage more than byte sequence of byte stream in storer is opposite like this, greatly.Because have this species diversity, make in two ways at present: one is software mode more,, syllable sequence counter-rotating processing changes by being adapted to syllable sequence; One is hardware mode, and the means such as reversal connection in the data line wiring adapt to the variation of syllable sequence.But when storer adopts BOOT FLASH, can't change syllable sequence, bring great risk to hardware design like this by software mode.
Application number is data sharing device and the processor that 200410030047.9 Chinese patent discloses the different processor data sharing of a kind of syllable sequence, the realization of this invention is mainly based on the conversion to the data address of processor, though can't change the problem of syllable sequence when can be used for solving storer and being BOOT FLASH by software mode, but need carry out bigger improvement to processor, expend bigger cost, be unfavorable for realizing.
Summary of the invention
Technical matters to be solved by this invention provides a kind of processor of different syllable sequences and coupling arrangement and its implementation between BOOT FLASH, make processor select simply and flexibly and BOOT FLASH between the syllable sequence interface mode.
For solving the problems of the technologies described above, the present invention is achieved by the following technical solutions:
Coupling arrangement between a kind of processor and BOOT FLASH, this device comprises: bus logic processing unit, control module, successfully start register;
The described register that successfully starts, the startup sign that is used to store BOOT FLASH;
Described control module is used to monitor described startup sign, judges that in view of the above whether BOOT FLASH successfully starts, if start successfully, then sends the control signal of directly transmitting bus signals to the bus logic processing unit; Fail as if starting, then the control signal of to the transmission of bus logic processing unit is carried out by syllable sequence counter-rotating processing to the data bus signal in the bus after, transmitting again;
Described bus logic processing unit, adopt the connected mode of acquiescence to link to each other with described processor, and adopt corresponding connected mode to link to each other with BOOT FLASH according to the syllable sequence of BOOT FLASH, according to described control signal the bus signals between processor and BOOT FLASH is handled and transmitted.
Wherein, described control module also is used for sending reset signal to described processor after described data bus being carried out by syllable sequence counter-rotating processing, points out this processor to reset.
A kind of implementation method of coupling arrangement as mentioned above may further comprise the steps:
(1) the bus logic processing unit of this device adopts the connected mode of acquiescence to link to each other with the bus of processor, and adopt corresponding connected mode to link to each other with BOOTFLASH according to the syllable sequence of BOOT FLASH, the bus signals of processor is directly passed to BOOT FLASH, does not do any processing;
(2) control module of this device judges according to the startup sign that successfully starts in the register whether BOOT FLASH successfully starts, if start successfully, then described bus logic processing unit continues directly to transmit bus signals between processor and BOOT FLASH, does not do any processing; If start failure, then the bus logic processing unit reverses the data bus signal in the bus of processor earlier according to syllable sequence, carries out the transmission of bus signals again.
Wherein, described step also comprises in (2): after described data bus signal is reversed according to syllable sequence, send reset signal to described processor, point out this processor to reset.
Wherein, the connected mode of acquiescence is big end connected mode or small end connected mode in the described step (1).
Wherein, the syllable sequence of described processor is big end syllable sequence or small end syllable sequence.
The present invention has following beneficial effect:
No matter adopt the CPU of which kind of syllable sequence, CPU and BOOT FLASH and coupling arrangement of the present invention can adopt fixing hardware connection mode, when the syllable sequence of CPU and BOOT FLASH is inconsistent, coupling arrangement can carry out handling according to the syllable sequence counter-rotating to the data bus signals, thereby can realize the Dynamic Selection of syllable sequence connected mode between different syllable sequence CPU and BOOT FLASH, and method is easy, and cost is lower.
Description of drawings
Fig. 1 is a key diagram of holding syllable sequence greatly;
Fig. 2 is the CPU of big end syllable sequence in the prior art and the connection diagram of storer;
Fig. 3 is the key diagram of small end syllable sequence;
Fig. 4 is the connection diagram of the CPU and the storer of small end syllable sequence in the prior art;
Fig. 5 is a connection diagram of having used the CPU and the BOOT FLASH of coupling arrangement of the present invention;
Fig. 6 is the implementation method process flow diagram of coupling arrangement of the present invention.
Embodiment
The present invention is described in further detail below in conjunction with the accompanying drawings and the specific embodiments:
See also Fig. 5, this figure is a connection diagram of having used the CPU and the storer of coupling arrangement of the present invention, and coupling arrangement wherein is a programmable logic device (PLD), is the PLD device of ROM type; Storer is BOOT FLASH, and the NOR FLASH of 8 of common samplings of industry BOOT FLASH or 16 bit data bus width is not because there is the problem of syllable sequence in the situation of 8 bit data bus, so the present invention only need consider the situation of 16 bit data bus width; CPU can make big end syllable sequence, also can be the small end syllable sequence.
In application process, coupling arrangement is fixedlyed connected respectively with the bus interface of CPU and storer, and wherein the data bus of coupling arrangement and CPU adopts the connected mode (holding connected mode or small end connected mode greatly) of acquiescence.
Coupling arrangement comprises following a few part: bus logic processing unit, control module, successfully start register.
Success starts register, is used for the startup sign of memory, and its default value is 0; If storer successfully starts, then will start sign and change to non-0 data; If storer starts failure, then this startup sign is not operated.
Control module is used for monitoring and starts sign, judges that in view of the above whether storer successfully starts, if start successfully, then sends the control signal of directly transmitting bus signals to the bus logic processing unit; Fail as if starting, then the control signal of to the transmission of bus logic processing unit is carried out by syllable sequence counter-rotating processing to the data bus signal in the bus after, transmitting again; Also be used to control resetting of CPU.
The bus logic processing unit is used for carrying out between CPU and storer according to the control signal of control module the processing and the transmission of bus signals.
See also Fig. 6, this figure is the implementation method of coupling arrangement in the present embodiment, may further comprise the steps:
601, the bus logic processing unit adopts the big end connected mode of acquiescence to be connected with CPU, and the data-signal of importing is left intact, and directly delivers to storer.
If the code in 602 storeies can normally move, will write non-0 data to successfully starting register; If can not normally move, then do not operate, it is constant to keep starting the default value that identifies.In this process, control module constantly detects and successfully starts register, if detect non-0 data, it is consistent to show that CPU and storer connect the compiling syllable sequence of the syllable sequence that adopts and the code in the storer, be big end syllable sequence, then the bus logic processing unit directly transmits bus signals, does not do any processing; Otherwise, show that CPU is the small end syllable sequence, continues next step.
603, the bus logic processing unit reverses the data-signal of CPU according to syllable sequence.
604, control module sends reset signal in of short duration time-delay back to CPU, and cancellation resets then, begins start-up course once more, and CPU transmits bus signals by the bus logic processing unit again.
As from the foregoing, under the situation that hardware connects and start-up routine is all correct, after twice startup, the CPU of any byte sequence styles can carry out normal signal transmission with BOOT FLASH.
Below, the start-up course with the BOOT FLASH of big end syllable sequence CPU and small end syllable sequence CPU is that example is described respectively, BOOT FLASH side adopts big end connected mode:
Big end syllable sequence CPU:
I, because default situations adopts big end connected mode, coupling arrangement is left intact to data-signal, directly links to each other with BOOT FLASH, i.e. D_IN[0-15] with D_OUT[0-15] directly be connected.After powering on, hold syllable sequence CPU to read and move code among the BOOT FLASH greatly, and the successful startup register success_reg in B write non-0 data.
Ii, coupling arrangement constantly detect and successfully start register success_reg, and when detecting non-0 data, it is consistent to show that CPU and BOOT FLASH connect the compiling syllable sequence of the syllable sequence that adopts and the code among the BOOTFLASH.At this moment, coupling arrangement can not sent the reset signal of CPU, and BOOT FLASH starts successfully.
Small end syllable sequence CPU:
The process i of I, beginning process and big end syllable sequence CPU is identical, is 0 if coupling arrangement detects the data that successfully start register success_reg always, assert this time to start and fails.
II, coupling arrangement reverse according to syllable sequence to the data-signal of input, and reset signal is sent to CPU in of short duration time-delay back, and cancellation resets then.
III, begin start-up course once more.Through behind the restarting, small end syllable sequence CPU and BOOTFLASH just can carry out normal data transfer.
The above only is preferred embodiment of the present invention, not in order to restriction the present invention, all any modifications of being done within the spirit and principles in the present invention, is equal to and replaces and improvement etc., all should be included within protection scope of the present invention.
Claims (6)
1. the coupling arrangement between processor and BOOT FLASH is characterized in that this device comprises: bus logic processing unit, control module, successfully start register;
The described register that successfully starts, the startup sign that is used to store BOOT FLASH;
Described control module is used to monitor described startup sign, judges that in view of the above whether BOOT FLASH successfully starts, if start successfully, then sends the control signal of directly transmitting bus signals to the bus logic processing unit; Fail as if starting, then the control signal of to the transmission of bus logic processing unit is carried out by syllable sequence counter-rotating processing to the data bus signal in the bus after, transmitting again;
Described bus logic processing unit, adopt the connected mode of acquiescence to link to each other with described processor, and adopt corresponding connected mode to link to each other with BOOTFLASH according to the syllable sequence of BOOT FLASH, according to described control signal the bus signals between processor and BOOT FLASH is handled and is transmitted, be specially:
If start successfully, then described bus logic processing unit continues directly to transmit bus signals between processor and BOOTFLASH; If start failure, then the bus logic processing unit reverses the data bus signal in the bus of processor earlier according to syllable sequence, carries out the transmission of bus signals again.
2. the coupling arrangement between processor as claimed in claim 1 and BOOT FLASH, it is characterized in that, described control module also is used for sending reset signal to described processor after described data bus being carried out by syllable sequence counter-rotating processing, points out this processor to reset.
3. the implementation method of coupling arrangement according to claim 1 is characterized in that, may further comprise the steps:
(1) the bus logic processing unit of this device adopts the connected mode of acquiescence to link to each other with the bus of processor, and adopt corresponding connected mode to link to each other with BOOT FLASH according to the syllable sequence of BOOT FLASH, the bus signals of processor is directly passed to BOOT FLASH, does not do any processing;
(2) control module of this device judges according to the startup sign that successfully starts in the register whether BOOT FLASH successfully starts, if start successfully, then described bus logic processing unit continues directly to transmit bus signals between processor and BOOT FLASH, does not do any processing; If start failure, then the bus logic processing unit reverses the data bus signal in the bus of processor earlier according to syllable sequence, carries out the transmission of bus signals again.
4. the implementation method of coupling arrangement as claimed in claim 3 is characterized in that, described step also comprises in (2): after described data bus signal is reversed according to syllable sequence, send reset signal to described processor, point out this processor to reset.
5. as the implementation method of claim 3 or 4 described coupling arrangements, it is characterized in that the connected mode of acquiescence is big end connected mode or small end connected mode in the described step (1).
6. as the implementation method of claim 3 or 4 described coupling arrangements, it is characterized in that the syllable sequence of described processor is big end syllable sequence or small end syllable sequence.
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| Application Number | Priority Date | Filing Date | Title |
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| CN200810068466XA CN101324868B (en) | 2008-07-11 | 2008-07-11 | Device for connecting processor and BOOT FLASH and implementing method |
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| CN200810068466XA CN101324868B (en) | 2008-07-11 | 2008-07-11 | Device for connecting processor and BOOT FLASH and implementing method |
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| CN101324868A CN101324868A (en) | 2008-12-17 |
| CN101324868B true CN101324868B (en) | 2010-06-16 |
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| CN102722390B (en) * | 2012-06-05 | 2015-04-15 | 上海联影医疗科技有限公司 | Flash-sharing device for multiprocessors and firmware program loading and upgrading method |
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| EP0282969A2 (en) * | 1987-03-18 | 1988-09-21 | Hitachi, Ltd. | Computer system having byte sequence conversion mechanism |
| CN1003680B (en) * | 1984-10-31 | 1989-03-22 | 得克萨斯仪器公司 | Cache memory addressable by both physical and virtual addresses |
| US5968164A (en) * | 1995-02-24 | 1999-10-19 | International Business Machines Corporation | Mixed-endian computing environment for a conventional bi-endian computer system |
| KR20030050462A (en) * | 2001-12-18 | 2003-06-25 | 삼성전기주식회사 | Method for transmission of data between two cpu with different addressing |
| CN1148667C (en) * | 1999-05-31 | 2004-05-05 | 德国汤姆森-布兰特有限公司 | Data pack preprocessing method and bus interface and data processing unit thereof |
| CN1532722A (en) * | 2003-03-19 | 2004-09-29 | ���µ�����ҵ��ʽ���� | Data sharing device for shared data between different byte sequence processors and processor |
| CN101118525A (en) * | 2006-07-31 | 2008-02-06 | 松下电器产业株式会社 | Data transfer control device including endian conversion circuit |
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2008
- 2008-07-11 CN CN200810068466XA patent/CN101324868B/en not_active Expired - Fee Related
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1003680B (en) * | 1984-10-31 | 1989-03-22 | 得克萨斯仪器公司 | Cache memory addressable by both physical and virtual addresses |
| EP0282969A2 (en) * | 1987-03-18 | 1988-09-21 | Hitachi, Ltd. | Computer system having byte sequence conversion mechanism |
| US5968164A (en) * | 1995-02-24 | 1999-10-19 | International Business Machines Corporation | Mixed-endian computing environment for a conventional bi-endian computer system |
| CN1148667C (en) * | 1999-05-31 | 2004-05-05 | 德国汤姆森-布兰特有限公司 | Data pack preprocessing method and bus interface and data processing unit thereof |
| KR20030050462A (en) * | 2001-12-18 | 2003-06-25 | 삼성전기주식회사 | Method for transmission of data between two cpu with different addressing |
| CN1532722A (en) * | 2003-03-19 | 2004-09-29 | ���µ�����ҵ��ʽ���� | Data sharing device for shared data between different byte sequence processors and processor |
| CN101118525A (en) * | 2006-07-31 | 2008-02-06 | 松下电器产业株式会社 | Data transfer control device including endian conversion circuit |
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Effective date of registration: 20180427 Address after: California, USA Patentee after: Global innovation polymerization LLC Address before: 518057 Department of law, Zhongxing building, South hi tech Industrial Park, Nanshan District hi tech Industrial Park, Guangdong, Shenzhen Patentee before: ZTE Corp. |
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Granted publication date: 20100616 |