CN101322321A - Hardware multi-standard video decoder device - Google Patents
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/42—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation
- H04N19/436—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation using parallelised computational arrangements
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/42—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/44—Decoders specially adapted therefor, e.g. video decoders which are asymmetric with respect to the encoder
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/60—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using transform coding
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- H—ELECTRICITY
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- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/60—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using transform coding
- H04N19/61—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using transform coding in combination with predictive coding
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Abstract
The present invention provides a hardware multi-standard video decoder device. A command parser accesses a video stream and identifies a video encoding standard used for encoding the video stream. A plurality of hardware decoding blocks perform operations associated with decoding the video stream, wherein different subsets of the plurality of hardware decoding blocks are used for decoding video streams encoded using different video encoding standards.
Description
Technical field
Field described herein relates to video decode.More particularly, the present invention relates to a kind of hardware multi-standard video decoder device.
Background technology
Usually use one in many different coding standards to come encoded digital video stream.For instance, compressible digital video frequency flow is so that convert the data format that needs less bits to.This compression can be break-even, makes to create original video stream again after decoding, or can be lossyly, makes the accurate duplicate that can not create original video stream again, but wherein more efficient to the decoding of packed data.
Current, have the multitude of video coding standard, and new standard occurs just constantly.The example of current video coding standard comprises JPEG (JPEG (joint photographic experts group)), MPEG (motion picture expert group), MPEG-2, MPEG-3, MPEG-4, H.263, H.263+, H.264 and for example Lille video (Real Video) and windows media propriety standards such as (Windows Media).In order fully to realize the benefit of digital video, the user needs to use the decoder of all general coding standards of can decoding.
Many important use of crossfire video are relevant with real time communication.For instance, visual telephone needs real-time video decoding so that its can with the respective audio signal Synchronization.Therefore, also need to provide the real-time video decoding so that the application relevant with real time communication to be provided to the user.In addition, need the decode situation of a plurality of video flowings of user can appear.For instance, the current user who carries out video telephony call receives the appended drawings picture from the personnel with its conversation.In this example, when decoding is to the conversation necessary image, must keep real-time decoding to visual telephone stream.
Current, use one in two kinds of methods availalbes to carry out video decode: single standard hardware Video Decoder; With the programmable core based on software, it can come decoded video streams according to one or more video standards.Single standard hardware Video Decoder can provide real-time decoding functional.Yet, using the coded video flowing of specific coding standard in order to decode, the user must have the hardware video decoder that is used for described specific criteria.Owing to have a large amount of widely used video encoding standards,, thereby the user caused sizable money cost so the user will need many different single standard hardware Video Decoders to use the coded digital video of different video coding standard with access.In addition, typical computer system does not have the ability of adding a large amount of single standard hardware Video Decoders, thus the number of the further accessible video flowing of limited subscriber.
Current programmable core Video Decoder based on software can be used for providing the decoding of using one or more video encoding standards.The programmable core Video Decoder can comprise and is used to quicken the hardware-accelerated of decode functionality.Yet programmable core is carried out all decodings.The programmable core Video Decoder has the high overhead of handling usually, inefficiency, and than the much more power of single standard hardware Video Decoder consumption.In addition, because decoding is subjected to the domination of the processing requirements of whole computer system, so the programmable core Video Decoder can not continue to provide the real-time video decoding.
Therefore, current available digital video decoder can not be provided for the real-time video decoding of a large amount of widely used video encoding standards.Video decode when in addition, current available digital video decoder can not be provided for using the coded a plurality of stream of a large amount of widely used video encoding standards.In addition, current available digital video decoder a plurality of video flowings of can not decoding simultaneously, wherein at least one video flowing needs real-time decoding.Therefore, need a kind of new digital video decoder that overcome the restriction that prior art has.Described new digital video decoder should be provided for the real-time video decode functionality of a plurality of different video standards.It is functional that new digital video decoder should also provide when being used to use the coded a plurality of video flowing of a plurality of different video standards video decode.
Summary of the invention
Embodiments of the invention provide a kind of hardware multi-standard video decoder device, and its video decode that is used to be provided for a plurality of different video coding standards is functional.Embodiments of the invention can be provided for each real-time decoding of described a plurality of video encoding standards.
In one embodiment, the invention provides a kind of hardware multi-standard video decoder device.The order parser of described hardware multi-standard video decoder device can be operated with accessing video stream and can operate the video encoding standard that is used for encoded video streams with identification.Hardware multi-standard video decoder device also comprises a plurality of hardware decoding blocks that are used to carry out the operation that is associated with decoded video streams, and the different subclass of wherein said a plurality of hardware decoding blocks are used to decode and use the coded video flowing of different video coding standard.In one embodiment, hardware multi-standard video decoder device is implemented in the integrated circuit that is coupled to printed circuit board (PCB), and wherein printed circuit board (PCB) is coupled to connector, so that in removable mode printed circuit board (PCB) is coupled to computer system.
In one embodiment, the order parser can be operated to activate being used to decode and being used for first first subclass through the identification video coding standard of encoded video streams of described a plurality of hardware decoding blocks, makes the hardware decoding block that is not associated with the described video flowing of decoding not be activated.In one embodiment, the order parser can be operated to activate being used to decode and being used for second second subclass through the identification video coding standard of encoded video streams of described a plurality of hardware decoding blocks, makes the hardware decoding block that is not associated with the described video flowing of decoding not be activated.
In one embodiment, described a plurality of hardware decoding block is implemented in the multistage macroblock level pipeline.In one embodiment, the order parser can be operated with a level place at multistage macroblock level pipeline and not receive hardware decoding block in the described level of stopping using under the data conditions of video flowing.In one embodiment, hardware multi-standard video decoder device carries out access to memory cell after the complete decoding video flowing.
In one embodiment, hardware multi-standard video decoder device further comprises the hardware reprocessing piece that is used for decoded video stream is carried out post-processing operation.In one embodiment, it is a plurality of hardware decoding blocks of stopping using under the situation of decoded video stream that the order parser can be operated with the video flowing that receives in order parser place, makes hardware reprocessing piece carry out post-processing operation to decoded video stream.In one embodiment, hardware reprocessing piece comprises filter.
In another embodiment, the invention provides a kind of method that is used for decoded video streams, wherein use hardware multi-standard video decoder device to implement described method.Accessing video stream.Identification be used to the to encode video standard of described video flowing.Determine the decode hardware decoding block subclass of described video flowing of being used in a plurality of hardware decoding blocks of hardware multi-standard video decoder device, the different subclass of wherein said a plurality of hardware decoding blocks can be operated with decoding and be used the coded video flowing of different video coding standard.Use the described hardware decoding block subclass described video flowing of decoding.
In one embodiment, a plurality of registers comprise memory surface index register and frame level parameter register.In one embodiment, hardware multithread multi-standard video decoder device further comprises the hardware reprocessing piece that is used at least one decoded video stream is carried out post-processing operation.
In one embodiment, a plurality of video flowings comprise at least one digital still stream and digital movie stream.In the present embodiment, the several portions of a plurality of video flowings is the macro block of digital still stream and digital movie stream.In another embodiment, a plurality of video flowings comprise a plurality of digital movie streams.In the present embodiment, the several portions of a plurality of video flowings is the macro block of a plurality of digital movie streams.
In another embodiment, the invention provides a kind of method of a plurality of video flowings that are used to decode, wherein use hardware multithread multi-standard video decoder device to implement described method.The a plurality of video flowings of access.Identification be used to the to encode video standard of described video flowing.Determine the decode hardware decoding block subclass of described video flowing of being used in a plurality of hardware decoding blocks of hardware multithread multi-standard video decoder device, the different subclass of wherein said a plurality of hardware decoding blocks can be operated with decoding and be used the coded video flowing of different video coding standard.Use the described hardware decoding block subclass described a plurality of video flowing of decoding.In one embodiment, activate described a plurality of hardware decoding block subclass, make the hardware decoding block that is not associated not be activated with the described a plurality of video flowings of decoding.
Put it briefly, the present invention discloses a kind of hardware multi-standard video decoder device.Order parser accessing video stream and identification be used to the to encode video encoding standard of described video flowing.A plurality of hardware decoding blocks are carried out the operation that is associated with the described video flowing of decoding, the different subclass of the wherein said a plurality of hardware decoding blocks coded video flowing of use different video coding standard that is used to decode.
Description of drawings
By way of example but not with ways to restrain explanation the present invention, same reference numbers refers to similar components and wherein in the accompanying drawings in accompanying drawing is graphic:
Fig. 1 illustrates the overview of the basic module of computer system according to an embodiment of the invention.
Fig. 2 A explanation is implemented in the figure of the exemplary hardware Video Decoder card on the printed circuit board (PCB) according to an embodiment of the invention.
Fig. 2 B explanation comprises the figure of the demonstrative structure of hardware multi-standard video decoder device according to an embodiment of the invention.
The block diagram of the intraware of hardware multi-standard video decoder device is described in Fig. 3 explanation according to one embodiment of the invention.
The block diagram of the intraware of exemplary hardware multi-standard video decoder device is described in Fig. 4 explanation according to one embodiment of the invention.
Fig. 5 explanation wherein uses hardware multi-standard video decoder device to implement described method according to the flow chart of the method that is used for decoded video streams of the embodiment of the invention.
Fig. 6 shows the figure that describes the intraware of hardware multithread multi-standard video decoder device according to one embodiment of the invention.
Fig. 7 A and Fig. 7 B show the figure that describes the exemplary alternating share of a plurality of video flowings according to the embodiment of the invention.
Fig. 8 explanation is used to decode the flow chart of method of a plurality of video flowings according to the embodiment of the invention, wherein uses hardware multithread multi-standard video decoder device to implement described method.
Fig. 9 explanation is according to the flow chart of method of unordered macro block that is used to handle video flowing of the embodiment of the invention.
Figure 10 A and Figure 10 B explanation are according to the figure of the exemplary rotation of the macro block of the frame of the embodiment of the invention.
Figure 11 explanation is according to the flow chart of method that is used to rotate the frame macro block of the embodiment of the invention.
Embodiment
Now will be in detail referring to the preferred embodiments of the present invention, the example is described in the accompanying drawings.Although will describe the present invention in conjunction with the preferred embodiments, will understand and not wish to limit the invention to these embodiment.On the contrary, the present invention wishes to contain replacement scheme, modification and equivalent, and described replacement scheme, modification and equivalent can be included in the spirit and scope of the invention that defines as appended claims.In addition, in following detailed description, state that many details are so that provide thorough understanding of the present invention to the embodiment of the invention.Yet those skilled in the art will realize that not to have putting into practice the present invention under the situation of these details.In other example, do not describe well-known method, program, assembly and circuit as yet in detail, in order to avoid unnecessarily obscure the each side of the embodiment of the invention.
Symbol and term:
According to program, step, logical block, processing with to other symbolic representation of the operation of the data bit in the computer storage and represent some part of following detailed description.These descriptions and expression are that the technical staff of data processing field is used for most effectively its work purport being conveyed to others skilled in the art's means.Substantially program, computer executed step, logical block, process etc. are contemplated that self-compatibility step or the command sequence that causes required result herein.Described step is the step that need carry out physical manipulation to physical quantity.Usually (although may not), this tittle take to store in computer system, transmit, make up, relatively and the signal of telecommunication of handling in other mode or the form of magnetic signal.Mainly due to normally used reason, verified sometimes these signals to be called position, value, element, symbol, character, item, numeral etc. be easily.
Yet, should remember that all these and similar terms will be associated with the suitable physical amount and only be the convenient mark that is applied to this tittle.Unless have in addition from the conspicuous clearly statement of following argumentation, otherwise will understand in the present invention, utilize the argumentation of for example " identification " or " access " or " execution " or " decoding " or " activation " or " stopping using " or " determining " or " processing " or " reception " or " buffering " or " ordering " or " forwarding " or " analysis " or " interlocking " or " rotation " or " reorientating " or terms such as " storages " to refer to action and process with lower device all the time: hardware multi-standard video decoder device (for example, the hardware multi-standard video decoder device 150 of Fig. 3), hardware multithread multi-standard video decoder device (for example, the hardware multithread multi-standard video decoder device 600 of Fig. 6), microcode engine (for example, the microcode engine 260 of Fig. 2 B), rotary Engine (for example, the rotary Engine 450 of Fig. 4) or similar computing electronics, its manipulation is expressed as the data of physics (electronics) amount in the RS of computer system and converts thereof into and is expressed as computer system memory or register or the storage of other this type of information similarly, other data of physical quantity in transmission or the display unit.
Computer system platform:
Fig. 1 illustrates illustrative computer system 100, can put into practice embodiments of the invention thereon.Usually, computer system 100 comprises: bus 110, and it is used for transmission information; Processor 101, itself and bus 110 are coupled and are used for process information and instruction; Volatile memory 102 also is called random-access memory (ram), and itself and bus 110 are coupled and are used to store information and the instruction that is used for processor 101; And nonvolatile memory 103, this paper also is called read-only memory (ROM), and itself and bus 110 are coupled and are used to store static information and the instruction that is used for processor 101.
In one embodiment, computer system 100 comprises optional data storage device 104 (for example disk or CD and disc driver), and itself and bus 110 are coupled and are used for stored information and instruction.In one embodiment, computer system 100 comprises: be used for the selectable user output device to computer user's display message, for example be coupled to the display unit 105 of bus 110; Be used for information and command selection are sent to the selectable user input unit of processor 101, for example be coupled to the alphanumeric input device that comprises alphanumeric and function key 106 of bus 110; And/or be used for user's input information and command selection are sent to the selectable user input unit of processor 101, for example be coupled to the cursor control device 107 of bus 110.In addition, optionally I/O (I/O) device 108 is used for computer system 100 is coupled to (for example) network.
In one embodiment, computer system 100 also comprises hardware multi-standard video decoder device 150, also is called decoder device 150 in this article, the video flowings of its codings of using a plurality of video encoding standards of being used for decoding.Decoder device 150 comprises a plurality of hardware decoding blocks, and it is used to carry out the required decode operation of described a plurality of video encoding standard.Should be appreciated that decoder device 150 can be configured to decode according to the video of any combination of video encoding standard, comprising digital still and digital movie.For instance, decoder device 150 can be configured to decoding and use JPEG, MPEG-4, H.263, H.263+, H.264 and (WMV9/VC-1) video of any one coding in the form of windows media (Windows Media).
Should be appreciated that, decoder device 150 can be embodied as discrete component, through design with (for example via connector, AGP groove, PCI-Express groove etc.) be coupled to discrete graphics card, the discrete integrated circuit small pieces (for example, being directly installed on the motherboard) of computer system 100 or be included in integrated decoder device in the integrated circuit circuit small pieces of computer system chipset assembly.In addition, can comprise be used for decoder device 150 local graphic memory to be used for storage.
Fig. 2 A explanation is implemented in the figure of the exemplary hardware Video Decoder card 200 on the printed circuit board (PCB) according to an embodiment of the invention.Hardware video decoder cards 200 comprises printed circuit board (PCB) (PCB) 210, integrated circuit (IC) chip 220, data wire 225 and connector 230.IC chip 220 comprises hardware multi-standard video decoder device 150.The connector (for example, AGP groove, PCI-Express groove etc.) that connector 230 is configured for use in via computer system is coupled to computer system (for example, the computer system 100 of Fig. 1).Data wire 225 is used for transmitting data (for example, bit stream) between computer system and IC chip 220.
Fig. 2 B explanation comprises the figure of the demonstrative structure 250 of hardware multi-standard video decoder device 150 according to an embodiment of the invention.Structure 250 comprises microcode engine 260, hardware multi-standard video decoder device 150 and memory 270.In one embodiment, the operation of microcode engine 260 control hardware multi-standard video decoder devices 150.Microcode engine 260 comprises the operation that hardware multi-standard video decoder device 150 must be carried out, thereby serves as the translation layer between machine instruction and the hardware unit decoder 150.In one embodiment, in microcode engine 260, carry out bit stream analysis and length-changeable decoding (VLD).Decoder device 150 uses memory 270 so that the video flowing that has received is carried out decoding and post-processing operation.An embodiment of operational store 270 is described at memory 330 places of Fig. 3.
Referring to Fig. 2 B, in one embodiment, the invention provides at microcode engine 260 places rearrangement macro block.As described below, decoder device 150 is supported different post-processing operation, for example removes to go outside piece (for example, de-blocking filter 440 places in loop) and the loop piece and/or decyclization (for example, at loop outer filter 442 places) in the loop.In various embodiments, go piece to receive macro block in the loop with raster scan order de-blocking filter place in loop.Yet, for example H.264 wait some video standard to support with non-raster scan order transmission and reception macro block.Therefore, the invention provides, remove piece to support to be used to support with non-raster scan order transmission and to receive in the loop of video standard of macro block with raster scan order ordering macro block.
In one embodiment, carry out pretreatment operation at microcode engine 260 places.In one embodiment, in microcode engine 260, carry out bit stream analysis and length-changeable decoding (VLD).Microcode engine 260 is configured to the described macro block of ordering before macro block is sent to hardware decoder device 150.The packed data of a frame of microcode engine 260 bufferings.In one embodiment, the run length coding packed data of a frame of microcode engine 260 bufferings.In one embodiment, microcode engine 260 analyses are imported bit stream into and are then carried out VLD.If microcode engine 260 detects unordered macro block, it cushions described data and waits for all macro blocks of reception so.Microcode engine 260 is followed with raster scan order ordering macro block and is sent it to hardware decoder device 150.
By macro block still for packed data time buffering macro block, microcode engine 260 only needs to cushion the run length coding packed data of maximum frames, the video data of its ratio decoder is a lot of less.In addition, the buffer compression macro block is also saved power.Video flowing via radio reception also often suffers many errors.The bit stream analysis is divided into microcode engine 260 also has the advantage of improving the error recovery.
The hardware multi-standard video decoder device structure
Fig. 3 shows the figure that describes the intraware of hardware multi-standard video decoder device 150 according to one embodiment of the invention.As illustrated in fig. 3, decoder device 150 comprises order parser 305, a plurality of hardware decoding block 310 to 318, hardware reprocessing piece 320 and memory 330.Decoder device 150 can be operated with a plurality of video encoding standards of decoding.
Described a plurality of hardware decoding block 310 to 318 is used to carry out the operation that is associated with the described video flowing of decoding.Should be appreciated that 310 to 318 representatives of hardware decoding block are according to the required different decoding functions of implementing in the Video Decoder 150 of video standard decoded video streams.For example video encoding standard such as MPEG-4 need be carried out specific operation with decoded video streams, makes all MPEG-4 decoders MPEG-4 video flowing of all can decoding.Should be appreciated that carrying out the required operation of decoding according to various standards is well-known for the those skilled in the art.
In one embodiment, the hardware decoding block of decoder device 150 is configured in macroblock level (for example, 8 * 8 pixel macroblock) executable operations.Yet, should be appreciated that decoder device 150 can be included in the hardware decoding block of other size level (for example frame level) executable operations.
The different subclass of hardware decoding block 310 to 318 are used to decode and use the video flowing of different video coding standard coding.For instance, the first exemplary video standard need use hardware decoding block 312 and 316 in decoded video streams.The second exemplary video standard need use hardware decoding block 310,312,314 and 318 in decoded video streams.Therefore, in various embodiment of the present invention, those only that decoded video streams is required hardware decoding blocks are used to decode and use the video flowing of the video standard coding of having discerned.
In one embodiment, order parser 305 can be operated only to activate needed those hardware decoding blocks of video flowing that are used to decode and received, makes the hardware decoding block that is not associated with the described video flowing of decoding not be activated.For instance, activation through the first hardware decoding block subclass of identification video coding standard (for example is used to decode first, hardware decoding block 312 and 316), make the hardware decoding block (for example, the hardware decoding block 310,314 and 318) that is not associated not be activated with the described video flowing of decoding.In another example, activation through the second decoding block subclass of identification video coding standard (for example is used to decode second, hardware decoding block 310,312,314 and 318), make the hardware decoding block (for example, the hardware decoding block 316) that is not associated not be activated with the described video flowing of decoding.In one embodiment, order parser 305 is the unique movable components in the decoder device 150.Activate the hardware decoding block on demand according to video standard and data flow through identification.
In one embodiment, the hardware decoding block of decoder device 150 is implemented in the multistage macroblock level pipeline.Such as among Fig. 3 displaying, decoder device 150 is embodied as three grades of macroblock level pipelines, the pipeline stages 2 that wherein comprises the pipeline stages 1 that comprises hardware decoding block 310 and 312 and comprise hardware decoding block 314,316 and 318.In one embodiment, the macro block of order parser 305 direct video stream 302 enters the hardware decoding block of pipeline stages 1.In one embodiment, an above macro block can reside in the pipeline stages 1, and pipeline stages 2 and 3 is limited to a resident macro block is only arranged.In one embodiment, hardware decoding block 312,316 and 318 is arranged in the remaining data path, and hardware decoding block 310 and 314 is arranged in the prediction data path.In one embodiment, remaining data path process errors or variance data, and the data that are associated with previous frame or macro block of predicted path access.
In one embodiment, order parser 305 can be operated with a level place at multistage macroblock level pipeline and not receive hardware decoding block in the described level of stopping using under the data conditions of described video flowing.For instance, in the decoding of video flowing 302, when the final data of video flowing 302 leaves pipeline stages 1 and does not receive data at pipeline stages 1 place, all hardware decoding block of off-stream pipeline level 1.Therefore, realize the excess power saving by all hardware decoding block of off-stream pipeline level, even need those hardware decoding blocks to be used for the video standard that is associated with video flowing 302.
In one embodiment, by complete decoding, video flowing 302 just enters or leaves memory 330 up to video flowing 302.Should be appreciated that memory 330 can be the embedding memory cell of external memory unit (for example, the volatile memory 102 of Fig. 1 or nonvolatile memory 103) or decoder device 150.By access memory 330 just after complete decoding video flowing 302, decoder device 150 uses less power.
In one embodiment, decoder device 150 further comprises the hardware reprocessing piece 320 that is used for decoded video stream is carried out post-processing operation.In one embodiment, hardware reprocessing piece 320 comprises de-blocking filter.Should be appreciated that de-blocking filter can be that interior de-blocking filter of loop or loop remove piece and/or decyclization filter outward.De-blocking filter was carried out before access memory 330 and is removed block operations in the loop.Loop goes piece and decyclization filter to go piece and decyclization operation to carrying out from the data of memory 330 accesses outward.Yet, should be appreciated that hardware reprocessing piece 320 can carry out the post-processing operation of any kind.In addition, can there be hardware reprocessing piece 320 in order to any number of carrying out a plurality of post-processing operation.
In one embodiment, order parser 305 can be operated to be inactive all hardware decoding block under the situation of decoded video flowing at video flowing 302, makes 320 pairs of decoded video flowings of hardware reprocessing piece carry out post-processing operation.In other words, decoder device 150 also can only be used as the hardware after-treatment device.If 150 places receive decoded video flowing at decoder device, all hardware decoding block of stopping using so, and described decoded video flowing carried out post-processing operation.
The block diagram of the intraware of exemplary hardware multi-standard video decoder device 400 (also being called decoder device 400) is described in Fig. 4 explanation according to one embodiment of the invention.Decoder device 400 is configured to as JPEG, MPEG-4, H.263, H.263+, H.264 or any one operation in the WMV9/VC-1 decoder.Therefore, decoder device 400 comprises being used for carrying out being used to decode and uses JPEG, MPEG-4, H.263, H.263+, H.264 or the hardware decoding block of necessary all decode operations of video flowing of any one coding of WMV9/VC-1 standard.Yet, should be appreciated that the present invention can be used to support other video standard flexibly, and the present invention is without wishing to be held to the embodiment described in Fig. 4.
As illustrated in fig. 4, decoder device 400 comprises order parser 402, a plurality of hardware decoding block, a plurality of hardware reprocessing piece and memory 460.Order parser 402 is used for accessing video stream 401 (for example, bit streams).Should be appreciated that video flowing 401 can comprise digital still data (for example, JPEG encodes) or the digital movie data (for example, MPEG-4).In one embodiment, from microcode engine (for example, the microcode engine 260 of Fig. 2 B) receiver, video stream 401.Video flowing 401 is according to the coded compressing video frequency flows in a plurality of video encoding standards.402 identifications of order parser are used for the video encoding standard of encoded video streams 401.In one embodiment, before order parser 402 accessing videos stream 401, carry out bit stream analysis and length-changeable decoding (VLD).Bit stream analysis and VLD can be carried out by host CPU (for example, the processor 101 of Fig. 1) or microcode engine.Should be appreciated that,, do not carry out decode operation so if video flowing 401 is to use the video standard that is different from the video standard that decoder device 400 is configured to decode to encode.In one embodiment, order parser 402 sends indication to computer system, and indication can not be carried out decoding to the video flowing that uses non-support standard code.
Be used for the video standard of encoded video streams 401 in identification after, order parser 402 is directed to the suitable hardware decoding block that is used for institute's identification video standard with the macro block of video flowing 401.In one embodiment, the order parser activates the suitable hardware decoding block that is used for institute's identification video standard, makes the hardware decoding block that does not need to be used for institute's identification video standard be deactivated.Order parser 402 also circulates control data to move through decoder device 400 by the control clock.In one embodiment, order parser 402 is the unique movable components in the decoder device 400.Activate the hardware decoding block on demand according to video standard of being discerned and data flow.
The hardware decoding block of decoder device 400 (for example comprises intra prediction mode engine 404, motion vector (MV) prediction engine 406, coefficient, running length (RD) or go to quantize) engine 408, AC/DC (for example, AC/DC prediction or go to quantize) prediction engine 410, infra-frame prediction engine 414, rotary Engine 415, motion compensation engine 416,4 * 4 reciprocal transformation engines 418,8 * 8 inverse discrete cosine transform (IDCT) engines 420, IDCT format converter engine 422, infra-frame prediction buffer 432, prediction sampling 434 and rest block 436.Decoder device 400 further comprises multiplexer 405,409,417,419,439 and adder 435.Decoder device 400 also comprises hardware reprocessing piece according to circumstances: de-blocking filter 440, loop outer filter 442 and rotary Engine 450 in the loop.
As mentioned above, decoder device 400 can operate with decoding according to JPEG, MPEG-4, H.263, H.263+, H.264 or any one video flowing of WMV9/VC-1 standard.Described hardware decoding block is carried out according to needed all decode operations of institute's support standard.The concrete operations of hardware decoding block are well-known and for being appreciated by one of skill in the art that, describe described operation as described in each of standard.Therefore, this paper is not described in detail the concrete operations of hardware decoding block.
In one embodiment, in predicted path, MV parameter and infra-frame prediction parameter are delivered to MV prediction engine 406 and intra prediction mode engine 404 respectively.These engines calculate actual motion vector or intra prediction mode based on the video standard of programming, and it is delivered to motion compensation engine 416 or infra-frame prediction engine 414 respectively.Motion compensation engine 416 or infra-frame prediction engine 414 calculate institute's data predicted.In one embodiment, motion compensation engine 416 comprises rotary Engine 415.Rotary Engine 415 be used for the rotary reference frame with import frame of video into and aim at.When in decoded video streams, using motion compensation engine, activate rotary Engine 415.Simultaneously, process errors data in the required subclass of coefficient engine 408, AC/DC prediction engine 410,4 * 4 reciprocal transformation engines 418,8 * 8IDCT engine 420 and IDCT format converter engine 422.
Add the error information of being recovered to data predicted, and then it further is delivered to pipeline stages 3.If necessary, further handle gained data and be written into memory 460 with to be shown.De-blocking filter is used for H264 and WMV9/VC-1 pattern in the loop.In the WMV9/VC-1 pattern, de-blocking filter 440 is used to implement overlapping smothing filtering in the loop.Loop outer filter 442 can be used for any video flowing to improve the quality of decoded picture.In one embodiment, loop outer filter 442 moves simultaneously with the remainder of decoder device 400.After frame decoding is in memory 460, should trigger loop outer filter 442.Decoded image also can be rotated at rotary Engine 450 places before the memory in being written to pipeline stages 3 460.
Hardware multi-standard video decoder device is at the example operation of support video standard
Following examples are described decoder device 400 at each the operation in the support video standard:
JPEG: the JPEG decoding does not need the hardware decoding block of predicted path, because the JPEG video flowing is used for creating again digital still.Therefore, at all inactive intra prediction mode engine 404 of JPEG decoding, MV prediction engine 406, infra-frame prediction engine 414, rotary Engine 415, motion compensation engine 416, infra-frame prediction buffer 432 and prediction sampling 434.And the JPEG decoding does not need 4 * 4 reciprocal transformation engines 418, and therefore it be deactivated.Order parser 402 activity coefficient engines 408, AC/DC prediction engine 410,8 * 8IDCT engine 420, extraction IDCT engine 438, IDCT format converter engine 422 and rest block 436.Order parser 402 will be from the data route of the video flowing 401 movable hardware decoding block by the JPEG encoded video streams that is used to decode.Should be appreciated that, stipulate by Joint Photographic Experts Group by operation and operating sequence that the hardware decoding block is performed.
The JPEG decoding only needs to use 8 * 8IDCT engine 420 and extract one in the IDCT engine 438.In one embodiment, order parser 402 can operate with identification to activate 8 * 8IDCT engine 420 and which person who extracts in the IDCT engine 438 at described video flowing.Activate 8 * 8IDCT engine 420 to be used for the complete decoding video flowing, extract IDCT engine 438 and under the situation that the video flowing indication is extracted, activate.IDCT format converter engine 422 can be operated to carry out format conversion.For instance, IDCT format converter engine 422 can be carried out format conversion between any following form: YUV 4:4:4, YUV 4:2:2, YUV 4:2:2R and YUV 4:2:0.Should be appreciated that, also can carry out other format conversion, and IDCT format converter engine 422 is not limited to cited form.
Decoded JPEG video flowing leaves pipeline stages 2.In one embodiment, decoded JPEG video flowing is stored in the memory 330.In another embodiment, before being stored in decoded JPEG video flowing in the memory 330, it is carried out post-processing operation.
MPEG-4/H.263: MPEG-4 and H.263 decode closely similar each other for the purposes of decoder device 400.In particular, the MPEG-4 standard needs the MPEG-4 decoder can operate the video flowing of H.263 encoding with decoding.MPEG-4 and H.263 the decoding do not need intra prediction mode engine 404, infra-frame prediction engine 414, IDCT format converter engine 422 and 4 * 4 reciprocal transformation engines 418, it all is deactivated.In addition, also at de-blocking filter 440 in the inactive loop of post-processing operation.Therefore, the order parser activates MV prediction engine 406, coefficient engine 408, AC/DC prediction engine 410, rotary Engine 415, motion compensation engine 416,8 * 8IDCT engine 420, infra-frame prediction buffer 432, prediction sampling 434 and rest block 436.Order parser 402 will be from the data route of video flowing 401 by being used to decode the MPEG-4 or the movable hardware decoding block of encoded video streams H.263.Should be appreciated that operation of being carried out by the hardware decoding block and operating sequence are by MPEG-4 and H.263 standard code.
Order parser 402 can be operated macro block is directed to suitable residual paths or predicted path hardware decoding block.In one embodiment, can be when the MV prediction engine 406 in the pipeline stages 1 be managed predictive frame (P frame) everywhere, frame (I frame) in the coefficient engine 408 of residual paths and AC/DC prediction engine 410 are managed everywhere.At synchronous I frame in pipeline stages 2 places and P frame.Order parser 402 also can be operated to activate the suitable hardware decoding block of 8 * 8IDCT engine 420.
Decoded MPEG-4/H.263 video flowing leaves pipeline stages 2.In one embodiment, decoded MPEG-4/H.263 video flowing is stored in the memory 330.In another embodiment, before being stored in decoded MPEG-4/H.263 video flowing in the memory 330, it is carried out post-processing operation.In another embodiment, at loop outer filter 442 places decoded MPEG-4/H.263 video flowing is carried out post-processing operation.In one embodiment, loop outer filter 442 is de-blocking filters.In another embodiment, loop outer filter 442 is decyclization filters.In another embodiment, loop outer filter 442 is de-blocking filter and decyclization filter.Should be appreciated that loop outer filter 442 can be embodied as any piece and/or decyclization filter of going.
H.263+: H.263+ codec class is similar to aforesaid MPEG-4/H.263 decoding.H.263+ the part with decode operation is displaced to VLD, and it was carried out before order parser 402 accessing videos stream 401.Except do not need and therefore stop using intra prediction mode engine 404, infra-frame prediction engine 414,4 * 4 reciprocal transformation engines 418 and loop outer filter 442, order parser 402 also stop using coefficient engine 408 and AC/DC prediction engine 410.In others, H.263+ codec class is similar to aforesaid MPEG-4/H.263 decoding.Should be appreciated that operation of being carried out by the hardware decoding block and operating sequence are by H.263+ standard code.
H.264: H.264 decoding does not need AC/DC prediction engine 410,8 * 8IDCT engine 420 and IDCT format converter engine 422, and it all is deactivated.Therefore, order parser 402 Active Frame inner estimation mode engines 404, MV prediction engine 406, coefficient engine 408, infra-frame prediction engine 414, rotary Engine 415, motion compensation engine 416,4 * 4 reciprocal transformation engines 418, infra-frame prediction buffer 432, prediction sampling 434 and rest block 436.Infra-frame prediction buffer 432 can be operated with storage from the top line pixel of previous macro block, make infra-frame prediction engine 414 can be when handling the next line macro block previous " leveling " pixel of access.Order parser 402 will be from the data route of video flowing 401 by being used to decode the H.264 movable hardware decoding block of encoded video streams.Should be appreciated that operation of being carried out by the hardware decoding block and operating sequence are by H.264 standard code.
Order parser 402 can be operated macro block is directed to suitable residual paths or predicted path hardware decoding block.In one embodiment, can in pipeline stages 1, handle a plurality of frames simultaneously in residual paths and predicted path place.At the synchronous described frame in pipeline stages 2 places.
Decoded H.264 video flowing leaves pipeline stages 2.In one embodiment, before being stored in decoded H.264 video flowing in the memory 330, it is carried out post-processing operation in the loop.In another embodiment, at loop outer filter 442 places decoded H.264 video flowing is carried out post-processing operation outside the loop.Should be appreciated that loop outer filter 442 can be embodied as any de-blocking filter and/or decyclization filter.
WMV9/VC-1: the WMV9/VC-1 decoding does not need intra prediction mode engine 404 and infra-frame prediction engine 414, and it all is deactivated.Therefore, order parser 402 activates MV prediction engine 406, coefficient engine 408, AC/DC prediction engine 410, rotary Engine 415, motion compensation engine 416,4 * 4 reciprocal transformation engines 418,8 * 8IDCT engine 420, infra-frame prediction buffer 432, prediction sampling 434 and rest block 436.Order parser 402 will be from the data route of the video flowing 401 movable hardware decoding block by the WMV9/VC-1 encoded video streams that is used to decode.Should be appreciated that operation of being carried out by the hardware decoding block and operating sequence are by the WMV9/VC-1 standard code.
Order parser 402 can be operated macro block is directed to suitable residual paths or predicted path hardware decoding block.In one embodiment, can in pipeline stages 1, handle a plurality of frames simultaneously in residual paths and predicted path place.At the synchronous described frame in pipeline stages 2 places.
Decoded WMV9/VC-1 video flowing leaves pipeline stages 2.In one embodiment, before being stored in decoded WMV9/VC-1 video flowing in the memory 330, it is carried out post-processing operation in the loop.In one embodiment, de-blocking filter 440 is used to implement overlapping smothing filtering in the loop.In another embodiment, at loop outer filter 442 places decoded WMV9/VC-1 video flowing is carried out post-processing operation.Should be appreciated that loop outer filter 442 can be embodied as any piece and/or decyclization filter of going.
Post-processing operation
The pipeline stages 3 of decoder device 400 comprises three hardware reprocessing pieces: de-blocking filter 440, loop outer filter 442 and rotary Engine 450 in the loop.H.264 de-blocking filter 440 is used for and the WMV9/VC-1 pattern in the loop.In one embodiment, in the WMV9/VC-1 pattern, de-blocking filter 440 is used to implement overlapping smothing filtering in the loop.
Loop outer filter 442 can be used for any video flowing to improve the quality of decoded picture.In one embodiment, loop outer filter 442 moves simultaneously with the remainder of decoder device 400.After frame decoding is in memory 460, should trigger loop outer filter 442.
Should be appreciated that any piece and/or decyclization filter of going can be used for loop outer filter 442.For instance, International Organization for Standardization (being used for supervising the tissue of the many video standards that can implement at device 150) usually comprises the de-blocking filter of being advised in the standardization publication.For instance, loop outer filter 442 can comprise ISO publication ISO/IEC 14496-2, the de-blocking filter described in 2001 the F.3.1 chapters and sections.
Decoded image also can be rotated at rotary Engine 450 places before the memory in being written to pipeline stages 3 460.Rotary Engine 450 is configured to provide based on indicated swing macro block rotation in service, wherein rotates each macro block and places it in the reposition of described frame.Referring to following argumentation, to obtain detailed argumentation to the operation of rotary Engine 450 to Figure 10 A, 10B and 11.
Be used to use the method for hardware multi-standard video decoder device decoded video streams
Fig. 5 explanation wherein uses hardware multi-standard video decoder device to implement described method according to the flow chart of the method that is used for decoded video streams 500 of the embodiment of the invention.Though disclosed concrete steps in method 500, described step is exemplary.That is to say that the embodiment of the invention is suitable for carrying out the modification of the step described in various other steps or Fig. 5 fully.In one embodiment, decoder device 150 manners of execution 500 by Fig. 3.
At step 510 place of process 500, accessing video stream.At step 520 place, identification be used to the to encode video standard of described video flowing.Hardware multi-standard video decoder device is configured to according to a plurality of video standards described video flowing of decoding.
At step 530 place, determine the decode hardware decoding block subclass of described video flowing of being used in a plurality of hardware decoding blocks of hardware multi-standard video decoder device.The different subclass of described a plurality of hardware decoding blocks can be operated the video flowing that uses different video coding standard coding with decoding.In one embodiment, show, activate described hardware decoding block subclass, make the hardware decoding block that is not associated not be activated with the described video flowing of decoding as step 540 place.
At step 550 place, use described hardware decoding block subclass to come decoded video streams.In one embodiment, show as step 560 place, if do not receive the data of video flowing at a level place of multistage macroblock level pipeline, the hardware decoding block in the described level of stopping using so.Should be appreciated that step 540 and 560 provides excess power to save and is optional.
At step 570 place, access memory unit after the described video flowing of decoding.In one embodiment, decoded video flowing is stored in the memory for demonstration.In one embodiment, show, decoded video flowing is carried out post-processing operation as step 580 place.Should be appreciated that, can before or after execution in step 570, carry out post-processing operation.In one embodiment, rotate decoded video flowing.In another embodiment, de-blocking filter in the loop is applied to decoded video flowing.Before access memory unit, carry out in rotation and the loop and remove piece.In one embodiment, after access memory unit, go piece and decyclization filter applies in decoded video flowing outward loop.
Use the hardware multi-standard video decoder device decoding to use a plurality of streams of different video standard code
The embodiment of hardware multi-standard video decoder device of the present invention also can operate with a plurality of video flowings of decoding simultaneously.The several portions of staggered described video flowing, for example macro block or frame.The decoder device consecutive access is through staggered part.Therefore, decoder device is to carrying out decode operation through staggered part.For instance, can carry out decode operation to the macro block of two video flowings.Staggered described video flowing makes the macro block of described video flowing replace.In each clock circulation, can carry out decode operation to the video flowing that replaces.
Fig. 6 shows the figure that describes the intraware of hardware multithread multi-standard video decoder device 600 according to one embodiment of the invention.As illustrated in fig. 6, decoder device 600 comprises video flowing interleaver 605, order parser 305, a plurality of hardware decoding block 310 to 318, hardware reprocessing piece 320, memory 330, register set 610 and register set 620.Decoder device 600 can be operated with a plurality of video encoding standards of decoding, and operates in the mode of the decoder device 150 that is similar to Fig. 3.Decoder device 600 is different from decoder device 150, a plurality of video flowings because register set 610 and 620 permission decoder devices 600 are decoded simultaneously.
Video flowing interleaver 605 can be operated the several portions with a plurality of video flowings of access and staggered described video flowing.As shown in the figure, video flowing interleaver 605 accessing videos stream 601 and 602.Yet, should be appreciated that video flowing interleaver 605 can operate receiving the video flowing of any number, and the embodiment that is not limited among Fig. 6 to be showed.In one embodiment, from microcode engine (for example, the microcode engine 260 of Fig. 2 B) receiver, video stream 601 and 602.
Fig. 7 A and 7B show the figure according to the exemplary alternating share of describing a plurality of video flowings of the embodiment of the invention.Referring to Fig. 7 A, show two interlaced video streams, one of them stream for still video transmission stream (for example, JPEG) and another stream flow (for example, MPEG-4) for digital movie.As shown in the figure, only comprise at video flowing under the situation of a digital movie streams, can be at macroblock level place interlaced video stream.In particular, rest image macro block 704 and 708 and digital movie macro block 702 and 706 staggered makes that the macro block from each video flowing replaces cross-current 700 in.Under the situation of macroblock level place interlaced video stream, the macro block data in the software driver buffer system memory of decoder device 600 is with the decoding of management interlaced video stream.
Referring to Fig. 7 B, showed two staggered video flowings, wherein said two streams all are digital movie stream.As shown in the figure, comprise at video flowing under the situation of a plurality of digital movie streams, at frame level place interlaced video stream.In particular, the first digital movie frame 752 and the 756 and second digital movie frame 754 and 758 interlock, and feasible frame from each video flowing replaces in cross-current 750.Under the situation of frame level place interlaced video stream, the frame data in the software driver buffer system memory of decoder device 600 are with the decoding of management interlaced video stream.
Referring to Fig. 6, order parser 305, hardware decoding block 310 to 318, hardware reprocessing piece 320 and memory 330 are operated as described in Figure 3 like that.By order parser 305 remaining data and other decoder parameters are delivered to decoder device.To be routed to residual paths (hardware decoding block 312,316 and 318) or predicted path (hardware decoding block 310 and 314) to data from order parser 305.To prepare/take out at predicted path under the data conditions of previous frame or previous macro block, residual paths is with process errors or variance data.
In order to manage the decoding of interlaced video stream, in pipeline stages 1, keep two register set 610 and 620.In one embodiment, register set 610 and 620 is memory surface index 612 and 622 respectively, and difference storage frame level parameter 614 and 624.Each of described register set is used for storing the parameter that is associated with one of video flowing.For instance, register set 610 is used to store the parameter that is associated with video flowing 601, and register set 620 is used to store the parameter that is associated with video flowing 602.In case handled arbitrary part of a video flowing in pipeline stages 1, suitable parameter just is delivered to downstream line level 2 and 3 with remaining data or prediction data with packet form.Having rest image based on macro block still is digital movie type and decoded data are routed to appropriate area in the memory.Should be appreciated that decoder device 600 can be configured to make each stream to be decoded have the register set that is associated by the decode video flowing of any number of the register set of adding proper number.
Fig. 8 explanation is used to decode the flow chart of method 800 of a plurality of video flowings according to the embodiment of the invention, wherein uses hardware multithread multi-standard video decoder device to implement described method.Though disclosed concrete steps in method 800, described step is exemplary.That is to say that embodiments of the invention are suitable for carrying out the modification of the step described in various other steps or Fig. 8 fully.In one embodiment, by decoder device 600 manners of execution 800 of Fig. 6.
At step 810 place of process 800, a plurality of video flowings of access.At step 820 place, identification be used to the to encode video standard of described video flowing.Hardware multithread multi-standard video decoder device is configured to according to a plurality of video standard decoded video streams.At step 830 place, the several portions of staggered described video flowing.In one embodiment, only comprise under the situation of a digital movie streams several macro blocks of staggered described video flowing at video flowing.In another embodiment, comprise under the situation of a plurality of digital movie streams some frames of staggered described video flowing at video flowing.Should be appreciated that, can any order execution in step 820 and 830.
At step 840 place, determine the decode hardware decoding block subclass of described a plurality of video flowings of being used in a plurality of hardware decoding blocks of hardware multi-standard video decoder device.The different subclass of described a plurality of hardware decoding blocks can be operated the video flowing that uses different video coding standard coding with decoding.In one embodiment, show, activate described hardware decoding block subclass, make the hardware decoding block that is not associated not be activated with the described video flowing of decoding as step 850 place.
At step 860 place, use the described hardware decoding block subclass described video flowing of decoding.At step 870 place, access memory unit after the described video flowing of decoding.In one embodiment, decoded video flowing is stored in the memory for demonstration.In one embodiment, show, at least one decoded video flowing is carried out post-processing operation as step 880 place.Should be appreciated that, can before or after execution in step 870, carry out post-processing operation.In one embodiment, rotate decoded video flowing.In another embodiment, de-blocking filter in the loop is applied to decoded video flowing.Before access memory unit, carry out in rotation and the loop and remove piece.In one embodiment, after access memory unit, go piece and decyclization filter applies in decoded video flowing outward loop.
Handle the unordered macro block of video flowing
Referring to Fig. 2 B, in one embodiment, the invention provides at microcode engine 260 places buffering and rearrangement macro block.The invention provides with raster scan order ordering macro block and remove piece to support to be used to support with non-raster scan order transmission and to receive in the loop of video standard of macro block.Microcode engine 260 is configured to receive the packed data of macro block of the frame of expression video flowing.In one embodiment, at least one macro block is by unordered reception.Microcode engine 260 is configured to cushion described packed data and is configured macro block for the described frame that sorts with raster scan order.
Fig. 9 explanation is according to the flow chart of method 900 of unordered macro block that is used to handle video flowing of the embodiment of the invention.Though disclosed concrete steps in method 900, described step is exemplary.That is to say that embodiments of the invention are suitable for carrying out the modification of the step described in various other steps or Fig. 9 fully.In one embodiment, by microcode engine 260 manners of execution 900 of Fig. 2 B.
At step 910 place of method 900, receive the packed data of the macro block of the frame of representing video flowing, wherein at least one macro block is by unordered reception.At step 920 place, cushion described packed data.In one embodiment, cushion described packed data at the buffer place of microcode engine 260.At step 930 place, analyze video flowing and video flowing is carried out VLD.Should be appreciated that step 930 is optionally, and video flowing is analyzed and VLD can carry out by the hardware decoder device.Should be further appreciated that at step 930 place and can carry out other or additional pre-treatment operation video flowing.
At step 935 place, determine whether video flowing needs to go in the loop piece.In one embodiment, packed data comprises whether will carrying out the indication of removing piece in the loop to video flowing.Remove piece in the loop if desired, with the macro block of raster scan order ordering frame, show so as step 940 place.In one embodiment, before with raster scan order ordering macro block, all macro blocks of buffered frame.Then, method 900 advances to step 950.Perhaps, if do not need to go in the loop piece, method 900 directly advances to step 950 so.
In step 950 place, decoded video streams.In one embodiment, with the raster scan order decoded macroblock.In one embodiment, by hardware multi-standard video decoder device (for example, the decoder device 400 of the decoder device 150 of Fig. 3 or Fig. 4) decoded video streams.In one embodiment, according to method 500 decoded video streams of Fig. 5.
At step 960 place, to removing piece in the decoded macro block execution macroblock level loop.In step 970 place, access memory unit.In one embodiment, will go piece and decoded video flowing to be stored in the memory for demonstration.
At step 980 place, decoded frame is carried out the outer reprocessing of frame level loop.In one embodiment, the outer reprocessing of loop comprises piece and decyclization operation.Should be appreciated that step 980 is optional.Then, method 900 turns back to step 970, in step 970 place access memory unit.In one embodiment, will go piece, decyclization and decoded video flowing are stored in the memory for demonstration.
By macro block still for packed data time buffering macro block, microcode engine 260 only needs to cushion the run length coding packed data of maximum frames, it lacks a lot than the video data through decoding.In addition, the buffer compression macro block is also saved power.Video flowing via radio reception also often suffers many errors.The bit stream analysis is divided into microcode engine 260 also has the advantage of improving the error recovery.
The rotation in service of the macro block of video flowing
Embodiments of the invention provide a kind of rotary Engine that is used for " in service " rotating video stream before video flowing is written to memory.Embodiments of the invention can be by reorientating macro block and come rotating video stream with its rotation and based on described being rotated in when receiving the macro block of video flowing in the frame.Embodiments of the invention can be by operating rotating video stream to macro block and not needing carry out second around reason through decoded frame before decoded macroblock is written to memory.
In one embodiment, the invention provides a kind of rotary Engine, its be configured to according to swing come rotating video stream frame macro block and described macro block is repositioned onto reposition in the described frame, wherein reposition is based on swing.In one embodiment, video decoder devices further comprises and is used to store macro block for the memory that shows.In one embodiment, described rotary Engine is configured at rotation macro block before the access memory and reorientates described macro block in frame.
Figure 10 A and 10B explanation are according to the figure of the exemplary rotation of the macro block of the frame of the embodiment of the invention.Although Figure 10 A and 10B describe the operation of the rotary Engine 450 of Fig. 4, should be appreciated that described embodiment can implement in the video decoder devices of any kind, and be not limited to use the hardware multi-standard video decoder device 400 of Fig. 4.For instance, rotary Engine can be included in single standard hardware decoder or the software decoder.
Referring to Figure 10 A, Figure 100 0 explanation uses the rotary Engine 450 of Fig. 4 to rotate frame 1010.Frame 1010 comprises many macro blocks.Macro block 1012 is shown as first macro block that rotary Engine 450 places receive.In one embodiment, receive macro block with raster scan order, wherein macro block 1012 is first macro blocks that received, because it is upper left macro block.
The operation of the use clockwise direction 90 degree swings of Figure 100 0 explanation rotary Engine 450.With macro block 1012 rotation clockwise directions 90 degree.Rotary Engine 450 is also reorientated macro block 1012, makes the macro block 1012 (being shown as the macro block 1022 that rotates in the frame 1020) that has rotated be in the same position with respect to all other macro blocks of frame 1020.
Embodiments of the invention also are provided at and rotate frame on the macroblock level, wherein unordered reception macro block.Referring to Figure 10 B, Figure 105 0 explanation uses the rotary Engine 450 of Fig. 4 to rotate frame 1060.Macro block 1062 is shown as first macro block that rotary Engine 450 places receive.In the present embodiment, do not receive macro block, because macro block 1062 is first macro blocks that received but is not the upper left side macro block with raster scan order.
Figure 11 explanation is according to the flow chart of method 1100 of macro block that is used to rotate frame of the embodiment of the invention.Though disclosed concrete steps in the method 1100, described step is exemplary.That is to say that embodiments of the invention are suitable for carrying out the modification of the step described in various other steps or Figure 11 fully.In one embodiment, by rotary Engine 450 manners of execution 1100 of Fig. 4.
In step 1110 place, decoded video streams.In one embodiment, by hardware multi-standard video decoder device (for example, the decoder device 400 of the decoder device 150 of Fig. 3 or Fig. 4) decoded video streams.In one embodiment, come decoded video streams according to the method 500 of Fig. 5.Should be appreciated that step 1110 is optionally, and described video flowing is decoded before handling.
At step 1120 place, the swing of the described video flowing of access.In one embodiment, swing is one in the following: clockwise direction 90 degree, counter clockwise direction 90 degree and 180 degree.Yet, should be appreciated that, can use any swing.At step 1130 place, the macro block of accessing video stream.
At step 1140 place, according to swing rotation macro block.At step 1150 place, macro block is repositioned onto reposition in the frame, wherein reposition is based on swing.Should be appreciated that, reorientate macro block so that macro block is in the same position with respect to all other macro blocks of the frame that once rotated.In one embodiment, before access memory, carry out the rotation of macro block and reorientating of macro block.
At step 1160 place, macro block is stored in the memory for demonstration.In one embodiment, show, decoded macro block is carried out removed block operations as step 1170 place.Should be appreciated that step 1170 is optional.In addition, should be appreciated that step 1170 can comprise carrying out in the loop goes piece or loop to remove piece and decyclization outward.
In this way, embodiments of the invention provide a kind of new hardware multi-standard video decoder device structure, and its support is carried out hardware based decoding according to a plurality of video standards to video flowing.Embodiments of the invention can provide real-time decoding in described a plurality of video encoding standards each.Embodiments of the invention provide the post-processing operation to decoded video stream.One embodiment of the present of invention provide a kind of hardware decoder device, its provide to use JPEG, MPEG-4, H.263, H.263+, H.264 with the WMV9/VC-1 video standard in any one video flowing carry out video decode.
Embodiments of the invention provide a kind of hardware multithread multi-standard video decoder device, and video decode was functional when it was used to be provided for a plurality of different video coding standard.Embodiments of the invention a plurality of interlaced video streams of can decoding simultaneously.
Embodiments of the invention provide a kind of video decoder structure, and it is used to provide video flowing is carried out removing piece in the loop and do not need to be used for extra memory with raster scan order ordering macro block.Can in microcode engine, the sort macro block of video flowing of embodiments of the invention.Embodiments of the invention can provide using a plurality of video flowings of supporting one in video standard coding to decode and loop removes piece and/or decyclization outward.
Embodiments of the invention provide a kind of rotary Engine that is used for " in service " rotating video stream before video flowing is written to memory.Embodiments of the invention can be by reorientating macro block and come rotating video stream with its rotation and based on described being rotated in when the macro block of receiver, video stream in the frame.Embodiments of the invention can be by operating rotating video stream to macro block and not needing carry out second around reason through decoded frame before decoded macro block is written to memory.
For explanation and description purpose, represented previous description to the specific embodiment of the invention.Do not wish describedly to be described as detailed or to limit the invention to the precise forms that disclosed, and can make many modifications and variations in view of above teaching.Selecting and describing described embodiment is in order to explain principle of the present invention and its practical application best, and then makes others skilled in the art can utilize the present invention and various embodiment with the various modifications that are suitable for desired special-purpose best.Wish that scope of the present invention is defined by appended claims and its equivalent.
Claims (10)
1. method that is used to decode, described method is to use hardware multi-standard video decoder device to implement, and described method comprises:
Access first video flowing, described first video flowing are one in a plurality of video flowings;
Identification be used to encode first video standard of described first video flowing;
Determine the decode first hardware decoding block subclass of described first video flowing of being used in a plurality of hardware decoding blocks of described hardware multi-standard video decoder device, the different subclass of wherein said a plurality of hardware decoding blocks can be operated the video flowing that uses different video coding standard coding with decoding; With
Use the described first hardware decoding block subclass described first video flowing of decoding.
2. method according to claim 1, it further comprises the described hardware decoding block subclass of activation, makes not to be activated with the unconnected hardware decoding block of described first video flowing of decoding.
3. method according to claim 1, wherein said a plurality of hardware decoding blocks are implemented in multistage macroblock level pipeline.
4. method according to claim 3, if it further comprises the data that do not receive described first video flowing at a level place of described multistage macroblock level pipeline, the hardware decoding block in the described level of stopping using so.
5. method according to claim 1, it further is included in described first video flowing of described decoding access memory unit afterwards.
6. method according to claim 1, it further comprises:
The described a plurality of video flowings of access;
Identification is used for second video standard of the video flowing of described a plurality of video flowings;
The several portions of staggered described a plurality of video flowings;
Determine a plurality of hardware decoding block subclass in described a plurality of hardware decoding block; With
Use described a plurality of hardware decoding block subclass described a plurality of video flowing of decoding.
7. method according to claim 6, wherein said a plurality of video flowings comprise at least one digital still stream and digital movie stream.
8. method according to claim 7, the described part of wherein said a plurality of video flowings are frames of described digital still stream and described digital movie stream.
9. method according to claim 6, wherein said a plurality of video flowings comprise a plurality of digital movie streams.
10. method according to claim 9, the described part of wherein said a plurality of video flowings are macro blocks of described a plurality of digital movie streams.
Applications Claiming Priority (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US11/299,057 | 2005-12-09 | ||
| US11/299,057 US9204158B2 (en) | 2005-12-09 | 2005-12-09 | Hardware multi-standard video decoder device |
| US11/299,055 | 2005-12-09 | ||
| US11/299,055 US9210437B2 (en) | 2005-12-09 | 2005-12-09 | Hardware multi-stream multi-standard video decoder device |
| PCT/US2006/046741 WO2007070343A2 (en) | 2005-12-09 | 2006-12-06 | A hardware multi-standard video decoder device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN101322321A true CN101322321A (en) | 2008-12-10 |
Family
ID=38163412
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNA2006800455918A Pending CN101322321A (en) | 2005-12-09 | 2006-12-06 | Hardware multi-standard video decoder device |
Country Status (6)
| Country | Link |
|---|---|
| JP (1) | JP4891335B2 (en) |
| KR (2) | KR101065546B1 (en) |
| CN (1) | CN101322321A (en) |
| DE (1) | DE112006003307T8 (en) |
| TW (1) | TW200735667A (en) |
| WO (1) | WO2007070343A2 (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN107529059A (en) * | 2011-04-22 | 2017-12-29 | 杜比国际公司 | Lossy compression method coded data method and apparatus and corresponding reconstruct data method and equipment |
| CN109600619A (en) * | 2018-12-11 | 2019-04-09 | 晶晨半导体(上海)股份有限公司 | A kind of time-sharing multiplexing method of decoding hardware |
| CN112672166A (en) * | 2020-12-24 | 2021-04-16 | 北京睿芯高通量科技有限公司 | Multi-code stream decoding acceleration system and method of video decoder |
| CN114339257A (en) * | 2022-01-26 | 2022-04-12 | 稿定（厦门）科技有限公司 | Method and apparatus for decoding video file |
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| US8705630B2 (en) * | 2006-02-10 | 2014-04-22 | Nvidia Corporation | Adapting one type of encoder to another type of encoder |
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| WO2004051982A1 (en) * | 2002-12-04 | 2004-06-17 | Koninklijke Philips Electronics N.V. | Method and apparatus for selecting particular decoder based on bitstream format detection |
| JP2005267172A (en) * | 2004-03-18 | 2005-09-29 | Sony Corp | Content reception system, device and method, recording medium, and program |
| US7590059B2 (en) * | 2004-05-21 | 2009-09-15 | Broadcom Corp. | Multistandard video decoder |
| US8705632B2 (en) * | 2005-03-30 | 2014-04-22 | Intel Corporation | Decoder architecture systems, apparatus and methods |
| KR100668346B1 (en) * | 2005-10-04 | 2007-01-12 | 삼성전자주식회사 | Filtering apparatus and method for a multi-codec |
-
2006
- 2006-12-06 KR KR1020087016391A patent/KR101065546B1/en active IP Right Grant
- 2006-12-06 WO PCT/US2006/046741 patent/WO2007070343A2/en active Application Filing
- 2006-12-06 JP JP2008544512A patent/JP4891335B2/en active Active
- 2006-12-06 DE DE200611003307 patent/DE112006003307T8/en not_active Expired - Fee Related
- 2006-12-06 KR KR1020107008555A patent/KR20100046284A/en not_active Application Discontinuation
- 2006-12-06 CN CNA2006800455918A patent/CN101322321A/en active Pending
- 2006-12-07 TW TW095145665A patent/TW200735667A/en unknown
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107529059A (en) * | 2011-04-22 | 2017-12-29 | 杜比国际公司 | Lossy compression method coded data method and apparatus and corresponding reconstruct data method and equipment |
| CN109600619A (en) * | 2018-12-11 | 2019-04-09 | 晶晨半导体(上海)股份有限公司 | A kind of time-sharing multiplexing method of decoding hardware |
| CN112672166A (en) * | 2020-12-24 | 2021-04-16 | 北京睿芯高通量科技有限公司 | Multi-code stream decoding acceleration system and method of video decoder |
| CN112672166B (en) * | 2020-12-24 | 2023-05-05 | 北京睿芯高通量科技有限公司 | Multi-code stream decoding acceleration system and method for video decoder |
| CN114339257A (en) * | 2022-01-26 | 2022-04-12 | 稿定（厦门）科技有限公司 | Method and apparatus for decoding video file |
| CN114339257B (en) * | 2022-01-26 | 2023-11-28 | 稿定（厦门）科技有限公司 | Method and apparatus for decoding video file |
Also Published As
| Publication number | Publication date |
|---|---|
| WO2007070343A3 (en) | 2008-01-17 |
| KR20100046284A (en) | 2010-05-06 |
| KR101065546B1 (en) | 2011-09-19 |
| DE112006003307T8 (en) | 2009-01-29 |
| KR20080082676A (en) | 2008-09-11 |
| TW200735667A (en) | 2007-09-16 |
| JP4891335B2 (en) | 2012-03-07 |
| JP2009518960A (en) | 2009-05-07 |
| WO2007070343A2 (en) | 2007-06-21 |
| DE112006003307T5 (en) | 2008-10-23 |
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