CN101320320B - Bit stream summator and bit stream multiplier using the same, and phase discriminator - Google Patents

Abstract

The invention discloses a bit stream adder and a bit stream multiplier and a phase discriminator adopting the bit stream adder. The bit steam adder consists of two multi-digit stream adders, two delay cells and a two times circuit. The input end of a first multi-digit stream adder is connected with stream signals a, b. The carry of the stream adder is the output of the stream adder. The first delay output of the sum of the first multi-digit stream adder is sent to the input end of a second multi-digit stream adder via the two times circuit. The second delay output of the sum of the stream adder is sent to other input end of the second multi-digit stream adder. The output of the second multi-digit stream adder is sent to the first multi-digit stream adder. The bit stream circuit of the invention brings about little noise and has simple structure. And the bit stream circuit can be used to process the bit stream signals produced by a single bit Sigma-Delta modulator directly. The bit stream adder has the advantages of little hardware resource occupation, high processing accuracy, etc.

Description

The bit stream multiplier of a kind of bit stream totalizer and employing bit stream totalizer

Technical field

The present invention relates to bit stream multiplier, the phase detector of a kind of bit stream totalizer and employing bit stream totalizer.

Background technology

In recent decades since with the muting sensitivity characteristic of VLSI process compatible and analog element, the Sigma-delta modulation technique more and more becomes a kind of widely used technology in modulus and digital analog interface circuit.But Digital Signal Processing (DSP) is the computing of the multistation digital signal under the Nyquist sampling rate, can not directly handle the bit stream signal of Sigma-delta modulation.The utilization digital signal technique is handled bit stream signal, at first will adopt decimation filter, and bit stream signal is converted to the computing of multistation digital signal ability; Just can obtain bit stream signal behind digital signal process interpolation filter after the processing and the re-quantization coding.Directly handle bit stream signal and then avoided this complicated process; In addition, directly handle the line that bit stream signal also reduces signal effectively, reduce the figure place of computing, reach the advantage of economize on hardware resource.

At present at home the research of the direct processing of bit stream signal is also rarely had report, the external nineties existing bibliographical information, but progress is very slow, visible in recent years report is less.Bit stream addition and multiplier are the most basic computings during bit stream signal is directly handled, and also are form other computing basic.First bit stream totalizer by P Oleary and F Malobetti in nineteen ninety system independently propose, the method that it adopts is the direct addition of bit stream signal to input, the carry signal of addition is as the output of totalizer, and and with next input value addition constantly.This totalizer handle and be used as noise, and only carried out the noise shaping of single order, therefore for by one, that the bit stream signal of second order Sigma-delta modulators modulate carries out the addition effect is also more satisfactory, then inapplicable for the bit stream signal of higher order modulator modulation.Also have a kind of bit stream totalizer to be put forward in 2002 by people such as H.Fujisaka, it adopts the direct addition of incoming bit stream signal to obtain divided by 2, for then adopting output+1 and-1 in turn with the situation that is zero.This bit stream totalizer has been because adopted algorithm divided by 2, and the signal amplitude after the summation has only original half, thereby influenced the signal to noise ratio (S/N ratio) of signal, causes carrying out the continuous several times addition; And must adopt symmetrical structure when realizing multiplying with it.People such as C.W.Ng have proposed the many input summers of bit stream, and are used for realizing the bit stream multiplier, but the noise source of introducing is many, and bad to the noise shaping effect, are not suitable for the realization of Higher-Order Circuit.

Summary of the invention

For solving the existing existing above-mentioned technical matters of bit stream computing circuit, the invention provides bit stream multiplier, the phase detector of a kind of noise bit stream totalizer few, simple in structure and employing bit stream totalizer.

The technical scheme that the present invention solves the problems of the technologies described above is:

A kind of bit stream totalizer, take advantage of 2 circuit to form by two multibit adders, two delay cell and one, input termination bit stream signal a, the b of first multibit adder, its carry is the output of bit stream totalizer, itself and time lag of first order output after taking advantage of 2 circuit, deliver to an input end of second multibit adder, itself and secondary postpone another input end that second multibit adder is delivered in output, first multibit adder is delivered in the output of second multibit adder.

A kind of bit stream multiplier that adopts the bit stream totalizer, by 16 XOR gate, six delay cells, 16 scramblers, four bit stream totalizer is formed, bit stream signal a, the output terminal of b is connected in series three delay cells successively, the input end that delays at different levels and the bit stream signal a of bit stream signal b and bit stream signal b delivered to four XOR gate respectively, these four XOR gate outputs are as the 1-4 position input of 16 scramblers, the delays at different levels of bit stream signal b and bit stream signal b and the first order of bit stream signal a are postponed the input end that four XOR gate are delivered in output respectively, these four XOR gate outputs are as the 5-8 position input of 16 scramblers, the delays at different levels of bit stream signal b and bit stream signal b and the second level of bit stream signal a are postponed the input end that four XOR gate are delivered in output respectively, these four XOR gate outputs are as the 9-12 position input of 16 scramblers, the delay outputs at different levels of bit stream signal b and bit stream signal b and the third level of bit stream signal a are postponed the input end that four XOR gate are delivered in output respectively, these four XOR gate outputs are as the 13-16 position input of 16 scramblers, the input end of four bit stream totalizers is received in 4 outputs of 16 scramblers, and the output terminal of four bit stream totalizers is the output terminal of bit stream multiplier.

A kind of bit stream phase frequency detector that adopts bit stream totalizer and bit stream multiplier, form by 12 bit stream multipliers and six bit stream totalizers, the input end of eight multipliers arranged side by side is as the input end of bit stream phase frequency detector, the output of per in order two bit stream multipliers is as the input end of a bit stream totalizer, the output terminal of eight multipliers arranged side by side is connected to the input end of four totalizers arranged side by side successively, the output of four totalizers arranged side by side connects four input ends of four multipliers, four input ends in addition of four multipliers connect the 4th totalizer successively, the 3rd totalizer, first adder, the input of second adder, four multipliers are delivered to the input end of two totalizers in order respectively, and the output of these two totalizers constitutes the phase detector output terminal.

Technique effect of the present invention is: bit stream totalizer of the present invention and bit stream multiplier architecture are simple, and noise is little, and have realized digital bit stream phase detection discriminator, effectively raise the performance and the economize on hardware resource of circuit.Adopt basic circuit of the present invention, have the second order shaping effect, can not introduce a large amount of noises, the signal-to-noise performance of phaselocked loop is good.

The present invention is further illustrated below in conjunction with accompanying drawing.

Description of drawings

Fig. 1 is the circuit diagram of bit stream totalizer among the present invention.

Fig. 2 is the circuit diagram of bit stream multiplier among the present invention.

Fig. 3 is the signal spectrum of bit stream totalizer and the comparison diagram of theoretical analysis result.Dotted line is the theoretical value of the noise spectrum that obtains according to formula (5) among the figure, and solid line is the signal that obtains after through the addition of bit stream totalizer of the sinusoidal bit stream data of two same frequencys and the spectrogram of noise.

Fig. 4 is the signal spectrum of bit stream multiplier and the comparison diagram of theoretical analysis result.Dotted line is the theoretical value of the noise spectrum that obtains according to formula (5) among the figure, and solid line is the signal that obtains after through the bit stream multiplier of the sinusoidal bit stream data of two different frequencies and the spectrogram of noise.

Fig. 5 is a bit stream all-digital phase-locked loop circuit application circuit structure.

Concrete technical scheme

Referring to Fig. 1, Fig. 1 is the circuit structure of bit stream totalizer among the present invention.The bit stream adder circuit is by two multibit adders (is circular expression, and is square expression), two delay cell z ^-1With one take advantage of 2 circuit to form.The output of the multibit adder of square expression is divided into two parts, carry c _OutWith and sum.Carry is the output signal of bit stream totalizer; With through twice delay with take advantage of 2 backs to form a second-order noise shaping circuit.Concrete realization theory is as follows:

Incoming bit stream signal a, b, output bit stream signal are c and for sum, can get time-domain representation by the circuit structure schematic diagram and be:

c(n)+sum(n)＝a(n)+b(n)+[2×sum(n-1)-sum(n-2)] (1)

Arrangement, through Z-conversion (corresponding letter is represented with capitalizing), can export bit stream signal and be:

C _out(z)＝[A(z)+B(z)-(1-z ^-1) ²sum(z)] (2)

By following formula as can be known, in the signal band output signal equal input signal and.In order to realize the bit stream circuit, 2 multibit adders have been adopted.The bit stream totalizer is produced output with noise then by function (1-z ^-1) ²Carried out the second order shaping, therefore the noise that produces can be removed by low-pass filter.

Circuit of the present invention has been considered the noise of bit stream adder circuit, and it has been carried out the high-order shaping, and circuit structure is simple, realizes simple.

Referring to Fig. 2, Fig. 2 is the circuit diagram of bit stream multiplier.The bit stream multiplier circuit is similar to the second-order noise shaping circuit of bit stream totalizer, 16 scramblers and a plurality of delay cell z by one ^-1, XOR gate

Form.What represent among Fig. 2 is the bit stream multiplier on one 4 rank.Input signal a, b is continuous to postpone for 4 times and obtains 16 output datas through intersecting behind the XOR, and they are encoded into one 4 positive integer after through 16 scramblers.This positive integer through one with the second-order noise shaping circuit that is similar to the bit stream totalizer after obtain the bit stream data output c of multiplier _OutIn like manner, in the noise shaping circuit, the output of the multibit adder of square expression is divided into two parts, carry c _OutWith and sum.Carry is the output signal of bit stream multiplier; With postpone through twice multidigit and take advantage of 2 backs to form a second-order noise shaping circuit, the delay here and to take advantage of 2 circuit are multidigit computings.Concrete realization theory is as follows:

Incoming bit stream signal a, b, output bit stream signal are c and for sum, can get bit stream multiplier mathematical notation by the circuit structure schematic diagram and be in time domain:

$2^m\×c\left(n\right)+\mathrm{sum}\left(n\right)=\underset{i=n-L+1}{\overset{n}{\mathrm{\Σ}}}\underset{i=n-L+1}{\overset{n}{\mathrm{\Σ}}}a\left(i\right)b\left(i\right)+[2\×\mathrm{sum}(n-1)-\mathrm{sum}(n-2)]---\left(3\right)$

After the arrangement, conversion can get being expressed as of frequency domain through Z-:

$C_{\mathrm{out}}\left(z\right)=\frac{1}{2^m}\left[\underset{i=n-L+1}{\overset{n}{\mathrm{\Σ}}}\underset{i=n-L+1}{\overset{n}{\mathrm{\Σ}}}A\left(z\right)B\left(z\right)z^{(i+j)-2n}\right]-\frac{1}{2^m}{(1-z^{-1})}^2\mathrm{SUM}\left(z\right)---\left(4\right)$

If 2 ^m=L ², i.e. m=2 * log ₂L, following formula is exactly the tree-like bit stream multiplier of time domain in the signal band so

The Z-conversion, promptly realized the multiplying of bit stream signal.

The present invention has realized the bit stream multiplication, has avoided classical tree structure, and circuit structure is fairly simple.Only adopt the bit stream totalizer of input more than 2, and only introduced a noise source, improved the signal to noise ratio (S/N ratio) of output signal.Equally, carried out the second order shaping to what multidigit bit stream totalizer was exported with noise, be similar to the bit stream adder circuit, therefore the noise that produces can be removed by low-pass filter.

For the circuit with second order shaping effect, its power spectrum signal can be estimated by following formula in theory:

P(f)＝2·sin ²(πf) (5)

Accompanying drawing 3,4 has provided the signal spectrum of bit stream totalizer and bit stream multiplier and the comparison diagram of theoretical analysis result.As seen from the figure, the circuit measured result is better than theoretical analysis, and this is because also do not consider the noise of signal in the theoretical analysis, and the linearization mould instrument of torture that adopts in the theoretical analysis has limitation.Do not have harmonic wave in the output signal of multiplier circuit, promptly circuit does not exist intermodulation and distortion.Wherein the sinusoidal bit stream signal of the different amplitudes of same frequency is adopted in the totalizer experiment, and multiplier adopts the sinusoidal bit stream signal of different frequency and different amplitudes.

Bit stream totalizer of the present invention and bit stream multiplier circuit are applied to phaselocked loop, have obtained bit stream all-digital phase-locked loop circuit.Its principle of work is described below: whole bit stream all-digital phase-locked loop basic circuit structure is shown in Fig. 5 (a), and by digital bit stream phase frequency detector, bit stream low-pass filter and Sigma-Delta oscillator three parts are formed.The Sigma-Delta oscillator is a numerically controlled digital oscillator that is similar to analog vco, and it is output as bit stream signal, and output signal is made up of real part and imaginary part.The bit stream low-pass filter is a kind of low-pass filter based on the Sigma-Delta technology, and its input and output all are bit stream signals.The bit stream phase frequency detector is finished the input signal and the frequency of Sigma-Delta oscillator output signal, bit comparison mutually of phase-locked loop circuit, and output signal still is a bit stream signal.When entire circuit was in the lock state, the mean value of bit stream phase frequency detector output was 0.The bit stream phase frequency detector adopts by the present invention designed bit stream addition and bit stream mlultiplying circuit and realizes, shown in Fig. 5 (b).Wherein input signal is the real part of Sigma-Delta oscillator output signal and the real part i of imaginary part and phaselocked loop input signal _RWith imaginary part i _I, in like manner, the output bit stream signal equally also exists real part and imaginary part, still, only gets real part z (n) in phase-locked loop, through the digital controlled signal of controlled Sigma-Delta oscillator behind the low-pass filter.

This phase-locked loop circuit can be realized by digital technology, and circuit is simple, and the hardware resource that takies is few, helps current lsi technology and realizes.Mainly by the performance decision of bit stream totalizer and bit stream multiplier, therefore, this phaselocked loop has good performance to performance in the circuit.

Claims (2)

1. bit stream totalizer, it is characterized in that: take advantage of 2 circuit to form by two multibit adders, two delay cell and one, input termination bit stream signal a, the b of first multibit adder, its carry is the output of bit stream totalizer, itself and time lag of first order output after taking advantage of 2 circuit, deliver to an input end of second multibit adder, itself and secondary postpone another input end that second multibit adder is delivered in output, first multibit adder is delivered in the output of second multibit adder.

2. bit stream multiplier that adopts the bit stream totalizer, it is characterized in that: comprise 16 XOR gate, six delay cells, 16 scramblers, four bit stream totalizers, bit stream signal a, the output terminal of b is connected in series three delay cells successively, the input end that delays at different levels and the bit stream signal a of bit stream signal b and bit stream signal b delivered to four XOR gate respectively, the output of these four XOR gate is as the 1-4 position input of 16 scramblers, the delays at different levels of bit stream signal b and bit stream signal b and the first order of bit stream signal a are postponed the input end that four XOR gate are delivered in output respectively, these four XOR gate outputs are as the 5-8 position input of 16 scramblers, the delays at different levels of bit stream signal b and bit stream signal b and the second level of bit stream signal a are postponed the input end that four XOR gate are delivered in output respectively, these four XOR gate outputs are as the 9-12 position input of 16 scramblers, the delay outputs at different levels of bit stream signal b and bit stream signal b and the third level of bit stream signal a are postponed the input end that four XOR gate are delivered in output respectively, these four XOR gate outputs are as the 13-16 position input of 16 scramblers, the input end of four bit stream totalizers is received in 4 outputs of 16 scramblers, the output terminal of four bit stream totalizers is the output terminal of bit stream multiplier, described four bit stream totalizers are by two multibit adders, two delay cell and one take advantage of 2 circuit to form, 4 outputs of 16 scramblers of input termination of first multibit adder, its carry is the output of bit stream multiplier, itself and time lag of first order output after taking advantage of 2 circuit, deliver to an input end of second multibit adder, first multibit adder and secondary postpone another input end that second multibit adder is delivered in output, first multibit adder is delivered in the output of second multibit adder.

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