CN101316364A - Image compression system - Google Patents

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CN101316364A
CN101316364A CN 200810022482 CN200810022482A CN101316364A CN 101316364 A CN101316364 A CN 101316364A CN 200810022482 CN200810022482 CN 200810022482 CN 200810022482 A CN200810022482 A CN 200810022482A CN 101316364 A CN101316364 A CN 101316364A
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wavelet transformation
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陈苏婷
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Nanjing University of Information Science and Technology
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Abstract

The invention discloses an image compression system which comprises an image collecting module used for collecting images at real time, a buffer module used for realizing the caching of the images, a segmentation module used for the segmentation of the images, a wavelet transformation module used for realizing the wavelet transformation of the images, a compression module used for encoding a wavelet coefficient after transformation, an output module used for outputting a data stream after encoding, wherein, the image collecting module collects the images at real time and sends the collected images to the buffer module; the segmentation module segments the images after caching into a plurality of image blocks and sends the image blocks after segmentation to the wavelet transformation module which carries out the wavelet transformation to the images and sends the images after transformation to the compression module; the images are compressed and encoded in the compression module and outputted by the image output module. The image compression system has high integration level and flexible configuration, can realize the compression of the images with large area and high resolution ratio and is widely applied to the real-time compression of the images with high resolution ratio.

Description

Image compression system
Technical field
The present invention relates to a kind of image compression system, specifically a kind of image compression system of big battle array high-definition picture.
Background technology
Popular image real-time compression system is 512 * 512 with size at present, and data resolution is that the image of 8bit/10bit is main, and the Real Time Compression of big face battle array high-definition picture, as resolution sizes 2k*2k, data throughout is big, needs to handle the bandwidth height.At high-definition picture, particularly how the continuous big Array CCD data of magnanimity realize that image compression is the difficult point in the practical engineering application.
Summary of the invention
In order to realize high-definition picture, particularly the compression of the continuous big Array CCD of magnanimity the purpose of this invention is to provide a kind of image compression system, and this image compression system can be realized the compression of big face battle array high-definition picture.
The objective of the invention is to be achieved through the following technical solutions:
A kind of image compression system is characterized in that: it comprises image capture module, cache module, cuts apart module, wavelet transformation module, compression module and output module, and image capture module is used for real-time images acquired; Cache module is used to realize the buffer memory to image; Cutting apart module is used for image is cut apart; Wavelet transformation module: be used to realize wavelet transformation to image; Compression module: be used to realize that the wavelet coefficient to after the conversion encodes; Output module: be used for the output of the data flow behind the coding;
The real-time images acquired of image capture module wherein, and an image of gathering is sent into cache module, behind buffer memory, cut apart the image segmentation of module after and become a plurality of image blocks buffer memory, and the image block after will cutting apart is delivered to the wavelet transformation module image is carried out wavelet transformation, then the image after the conversion is sent into compression module, and in compression module, realize image compression encoding, export via image output module at last.
Among the present invention, described image capture module adopts the cache image transducer to come real-time images acquired.Described image buffer storage imageing sensor is CCD or CMOS camera.
Cache module is made of SDRAM, and the read-write control of SDRAM wherein realizes by a state machine is set in FPGA.
Cut apart module and become a plurality of image blocks by the image segmentation of address switchover mode after buffer memory.
Wherein wavelet transformation is (5,3) small echo; This small echo implementation method adopts the synthetic wavelet transformation that wavelet transformation module and BORDER PROCESSING unit are united two into one, and this conversion is divided into incipient stage, interstage and ending phase with every capable view data;
Incipient stage: low frequency and high frequency processing method are respectively
c[i 0]＝x[i 0]-x[i 0+1]
Figure A20081002248200041
Interstage: low frequency and high frequency processing method are respectively
Figure A20081002248200051
Figure A20081002248200052
Ending phase: low frequency and high frequency processing method are respectively
c[i l]＝x[i l]-x[i l+1]
Figure A20081002248200053
X[n in the formula] be primary signal, c[n], d[n] be respectively wavelet low frequency and high fdrequency component, symbol
Figure A20081002248200054
The expression rounding operation.
This small echo implementation method is:
At first, to inputing to the view data of FPGA, through the pixel clock counter in the FPGA, send into mode selecting unit, in mode selecting unit, judge by the numerical value of counter lowest order and the register pair odd even address and the border of mode selecting unit, calculate low frequency and high fdrequency component according to above-mentioned small wave converting method;
Then, carrying out odd and even data at the dateout of mode selecting unit decomposes, after the decomposition, even address data one tunnel are directly sent into computing circuit, computing circuit is sent into after sending into register R1 time-delay again in another road, to guarantee synchronous sum operation, with the data addition of corresponding odd address, produce odd address high-frequency sub-band data after the even address data processing;
Send into computing circuit again after when wherein the odd address data are sent into register earlier and prolonged R2, to guarantee handling back data synchronization addition with even address, the even address data are directly sent into the preceding high-frequency sub-band data addition behind computing circuit and the process time-delay R1, send into the R3 time-delay simultaneously, data after the processing and the corresponding even address data addition that register R4 sends produce even address low frequency sub-band data;
Wherein, register R1 is the delay data of even address, and register R2 is the delay data of odd address, and register R3 is the high-frequency sub-band delay data of odd address, and register R4 is the delay data of even address.
Compression module comprises overall control unit, descendants's coefficient significant element, importance scanning element and bit plane output unit;
Wherein, overall control unit is used for control and compiles encoder and switch between each module by algorithm flow; Descendants's coefficient significant element stores the maximum among all descendants of descendants's node, so that judge fast whether certain set relative threshold is important; The importance scanning element obtains F by former wavelet coefficient matrix is scanned from generating the tree data C, F dAnd F lMark bit map and inheritance each other; F wherein CFigure is used to point out the position of significant coefficient, F dFigure is used to refer to the position of important offspring's set, F lFigure is used to refer to the position of all offspring's set except that immediate successor.
Cutting apart module comes image is cut apart according to the size of image size and processor interior storage capacity.
The present invention is by the real-time images acquired of image capture module, and an image of gathering is sent into cache module, behind buffer memory, cut apart the image segmentation of module after and become a plurality of image blocks buffer memory, image block after will cutting apart is then delivered to the wavelet transformation module and is carried out wavelet transformation, via sending into compression module after the conversion of wavelet transformation module, in compression module, realize image compression encoding, export via image output module at last.
Integrated level height of the present invention, flexible configuration; Realized high-definition picture, the particularly compression of the continuous big Array CCD of magnanimity, effect is remarkable.
Description of drawings
Fig. 1 is a structured flowchart of the present invention;
Fig. 2 is the read/write state transition diagram of SDRAM;
Fig. 3 is a structural representation of cutting apart module;
Fig. 4 is the schematic diagram of wavelet transformation module;
Fig. 5 is the hardware implementation structure of compression module;
Fig. 6 is a workflow diagram of the present invention.
Embodiment
A kind of image compression system, as shown in Figure 1, it comprises image capture module 1, cache module 2, cuts apart module 3, wavelet transformation module 4, compression module 5 and output module 6, image capture module 1 is used for real-time images acquired; Cache module 2 is used to realize the buffer memory to image; Cutting apart module 3 is used for image is cut apart; Wavelet transformation module 4 is used to realize the wavelet transformation to image; Compression module 5 is used to realize that the wavelet coefficient to after the conversion encodes; Output module 6 is used for the output of the data flow behind the coding.
Image capture module 1 comprises imageing sensor and sensor interface, and wherein imageing sensor can be CCD camera, CMOS camera or other imageing sensors.The subsequent treatment of image is general all at the image sensor interface circuit of a correspondence of imageing sensor output employing for convenience, is used to realize that the image the imageing sensor collection takes out from sensor internal.Imageing sensor adopts the 4M15CCD camera that Dalsa company produces in the present embodiment, and the camera data interface adopts high speed Camera Link interface.
Cache module 2 comprises that memory and storage control unit constitute.Memory can be a dual port RAM, SRAM, SDRAM.Especially SDRAM such as the HY57V281620HCT that HYNIX company produces, adopts the internal structure of sync cap and complete streamline, makes it have great data rate, is fit to very much the storage of big throughput.Storage control unit adopts FPGA to realize, by at FPGA internal structure sdram controller, realizes the buffer memory to original image.Sdram controller adopts state machine to realize.This state machine comprises following state: init state, idle condition, read-write state, precharging state, Flushing status, state of activation.Behind system power-on reset, at first finish the initialization of SDRAM.Initialization comprises the initialization time-delay, and initialization precharge, initialization refresh and the setting of initialize mode register.Consider efficiency, the mode register working method is the full page burst, and fixation of C AS (read command is input to data output time-delay) is 2 clock cycle.After initialization finished, SDRAM entered idle condition.When idle condition, as sending read-write requests to SDRAM, sdram controller enters the line activating state, laggardly goes into the read/write state and just can read and write SDRAM through two clock cycle.
After SDRAM entered the write data state, owing to adopt full page burst working method, then a write operation can have been write data line.It is noted that at last once write operation and finish before next write operation, current line must be closed and carry out the preliminary filling order.Behind the precharging state, after two clock cycle, could activate next line again and carry out write operation next time.Because all there is the periodic refreshing problem in dynamic memory, behind the data write storage unit, want data and do not lose, need in given interval, to refresh, promptly enter Flushing status.As seen, under the control of SDRAM high-frequency clock speed,, can finish image data transmission at line blanking period fully to delegation for the video image of gathering by full page burst write operations mode.When receiving the next line view data, repeat aforesaid operations, all write SDRAM until the entire image data.
After SDRAM entered the read data state, after the time, the SDRAM data terminal can sense data through CAS (read command is input to data output time-delay) for palpus.Because the full page burst mode is all adopted in the SDRAM read/write operation, therefore after SDRAM runs through data line, then finished single reading according to operation.Carry out the preliminary filling order current line is closed this moment.Behind precharging state, need again after two clock cycle, could activate next line again.Because SDRAM adopts the capacitance stores data message, and is the same with write operation, need carry out periodic refreshing to data equally.After refresh operation finishes, just can send out read command once more, all read until frame data.The state transition diagram of whole SDRAM is seen Fig. 2.
Cut apart module 3 and be used to realize that the view data to reading through cache module 2 cuts apart.To a big face system of battle formations picture, be divided into polylith according to processor internal capacity size.For example, the image of a 1K * 1KByte, the processor interior storage capacity is 256 * 256Byte, that need give into 4 * 4 to image, promptly 16.Cut apart by the address of reading of control buffer memory and realize.Still be example with 1K * 1KByte, as shown in Figure 3, read order and be followed successively by the 1st to 16, producing row address when reading successively is 0-255, column address is 0-255,256-511,512-767 and 768-1023, row address is 256-511, column address is 0-255,256-511,512-767 and 768-1023, row address is 512-767, column address is 0-255,256-511,512-767 and 768-1023, row address is 768-1023, and column address is 0-255,256-511,512-767 and 768-1023.
Realize image segmentation by the address switchover mode like this, can reduce the complexity of process, and do not need the overhead memory cell, can improve the integrated level of system effectively.Image for different sizes according to the size of processor interior storage capacity, can be divided into different pieces, so highly versatile.
Wavelet transformation module 4 realizes the wavelet transformation of piecemeal subimage is decomposed.Choose (5,3) wavelet transformation and realize wavelet transformation, and handle when realizing sharp point and middle normal data unit by mode selecting unit.Whole mathematical algorithm only can be realized with adder and shift unit, has avoided a large amount of multiply operations of traditional wavelet, and operand is little.And logic control element is simple in structure, has reduced system complexity effectively.
Wherein (5,3) Wavelet Transformation Algorithm is:
Figure A20081002248200081
Figure A20081002248200082
X[n in the formula] be primary signal, c[n], d[n] be respectively wavelet low frequency and high fdrequency component, symbol
Figure A20081002248200083
The expression rounding operation.
Formula (1) and formula (2) have provided the principle of (5,3) wavelet transformation, and putative signal is an endless here.Yet the picture signal in the reality all is time-limited.Therefore, must carry out continuation to signal boundary.The size of supposing image is 256 * 256, and then each line data address arrangement is 0-255.According to (5,3) wavelet algorithm (1), (2) can get, and the processing of being expert at is carried out in the finding the solution of odd address high-frequency sub-band data d, the d[255 when asking line data to finish] time, need x[256], and these data do not exist; Equally in carrying out the finding the solution of even address low frequency sub-band data, during 0 address low frequency sub-band data when asking line data to begin, need d[-1], these data do not exist yet.Therefore must carry out boundary extension.
As margin processing module is independent of outside the wavelet transformation module as separate modular, the area of hardware will be increased.Here, adopted a kind of synthetic wavelet transformation module.Its core concept is wavelet transformation module and BORDER PROCESSING unit are united two into one, and once finishes.Implementation method is as follows: every capable view data is divided into following three stages: incipient stage, interstage, ending phase.If image pixel resolution is l * l, then each row of data pixel scope is i 0To i L-1Wherein, the incipient stage is first pixel i of every capable view data 0Interstage is that the pixel scope is from i 1To i L-2Ending phase is last pixel i L-1Adopt piecewise function thought, wavelet transformation is divided into 3 stages.The computing formula in per stage is as follows:
Incipient stage: low frequency and high frequency processing method are respectively (3), (4) formula.
Interstage: low frequency and high frequency processing method are respectively (1), (2) formula.
Ending phase: low frequency and high frequency processing method are respectively (5), (6) formula.
c[i 0]＝x[i 0]-x[i 0+1] (3)
Figure A20081002248200084
c[i l]＝x[i l]-x[i l+1] (5)
Figure A20081002248200085
At above-mentioned 3 stages of wavelet transformation decomposing module 4, Fig. 4 has provided the operating process of wavelet transformation module 4: at first, to inputing to the view data of FPGA, through the pixel clock counter in the FPGA, send into mode selecting unit.In mode selecting unit, judge by the numerical value of counter lowest order and the register pair odd even address and the border of mode selecting unit, in this way the beginning on border and end signal, then press formula (3), (4), (5) respectively, (6) operation, otherwise press normal mode (1), (2) operation.
Then, carrying out odd and even data at the dateout of mode selecting unit decomposes.
Even data after the decomposition is sent into two register cells simultaneously and is realized buffer memory respectively.The first via is guaranteed synchronous sum operation through the time-delay even data input computing circuit of R1 register cell; The second tunnel time-delay even data through the R4 register cell is then passed through and the data addition of corresponding odd address, produce odd address high-frequency sub-band data.
Odd data after the decomposition is sent into computing circuit after sending into register R2 time-delay earlier again, to guarantee handling back data synchronization addition with even address.The R3 time-delay is sent in preceding high-frequency sub-band data addition after delaying time with process then simultaneously.Corresponding even address data addition through the data after the time-delay of R3 register cell are sent with register R4 after adder and shifted divider output produces even address low frequency sub-band data.
Wherein, the R1 register is the delay data of even address, and R2 is the delay data of odd address, and R3 is the high-frequency sub-band delay data of odd address, and R4 is the delay data of even address.
The compressed encoding that compression module 5 is realized wavelet coefficient after the conversion.On the basis of classical spiht algorithm, replace big capacity chained list by adopting mark bit map, reduced the complexity that hardware algorithm is realized.
Classical spiht algorithm is a kind of image compression encoding algorithm based on zero tree structure.Decompose if image has carried out K level wavelet transformation, then formed (3K+1) individual subband, form " direction in space tree " structure from low to high by its frequency band, tree root is the node of lowest frequency subband.The core concept of zerotree image algorithm is with the following prerequisite that is assumed to be: if be positioned at the wavelet coefficient of " tree " last higher level is zero, and then the wavelet coefficient on the lower level of its pairing the same space position equidirectional also is zero.This shows " zero tree " that can detect existence, thereby reaches the purpose of compression.
Spiht algorithm at first need realize gathering efficiently segmentation strategy.Algorithm is defined as the segmentation strategy of gathering according to " direction in space tree " structure:
D(i，j)＝L(i，j)+O(i，j)
O(i，j)＝{(2i+1，2y)，(2i+1，2y+1)，(2i，2y+1)，(2i，2y+1)}
L(i，j)＝∑D(k，l)，(k，l)∈O(i，j)
Wherein, O (i, j) expression node (i, the coordinate set of direct descendent node j) (i.e. four child nodes), D (i, j) expression node (i, the coordinate set of all descendent node j), L (i, j) expression node (i, the coordinate set of all descendant nodes except that immediate successor j).
Then, algorithm carries out the test of significance of a coefficient sets T according to the set after dividing according to following function (8).
S n ( &Gamma; ) = 1 , max ( i , j &Element; &Gamma; ) { | T ( i , j ) | } &GreaterEqual; 2 n 0 , max ( i , j &Element; &Gamma; ) { | T ( i , j ) | } < 2 n - - - ( 7 )
Promptly the wavelet coefficient collection is divided into some set T m, reduce 1 n for circulating one by one, seek those greater than 2 nCoefficient, if T mIn all coefficients all inessential, encoder will be exported a "No" information (subclass is inessential), correspondingly, decoder receives this "No" information and just knows T mIn all coefficients all less than 2 nIf T mIn significant coefficient is arranged, " agreement " that an encoder and decoder observe jointly will be arranged so set T mResolve into littler subclass T M, l, and implement above-mentioned importance for new subclass and detect.Such set is divided and is repeated, and all carries out the scanning of coefficient importance, all subclass T up to all subclass mThe all elements of the inside is all inessential.
At last, mark off three ordered lists (being respectively: zerotree root table (LIS), significant coefficient table (LSP) and non-significant coefficient table (LIP)) according to the material information of wavelet conversion coefficient and come recording-related information, thereby realize efficient compression.
The spiht algorithm flow process is as follows:
Step1: initialization:
Figure A20081002248200102
Wherein, n represents higher bit plane (being most important bit-planes).| c (i, j) | expression (i, wavelet coefficient j).
Step2: according to the set segmentation strategy, carry out importance scanning according to formula (7), and with relevant information records in LIS, LIP, LSP tabulation.
Step3: make n=n-1,, go to step 2) if n is not 0; N=0 finishes coding.
Classical spiht algorithm is remarkable image compression encoding algorithm.Yet in implementation procedure, (LIS, LIP LSP), are unfavorable for the hardware realization to need three in order big capacity chained lists of storage.Compression module (5) with the hardware implementation platform of FPGA as compression algorithm, by opening up the big capacity chained list that three ram region storage mark bitmaps replace classical spiht algorithm, has reduced hard-wired complexity on the basis of classical spiht algorithm.Fig. 5 has provided the implementation structure of compression module 5.
This implementation structure mainly is made up of following unit: overall control unit, descendants's coefficient (arbitrary node (i behind the wavelet transformation, j) all descendent node coefficient sets) significant element, importance scanning element and bit plane output unit (formed binary bits plane in the wavelet coefficient scanning process).Simultaneously, open up three RAM districts in FPGA inside and be used for storage mark bitmap F respectively C, F DAnd F L(F CFigure is used to point out the position of significant coefficient, F dFigure is used to refer to the position of important offspring's set, F lFigure is used to refer to the position of all offspring's set except that immediate successor).
Wherein, overall control unit is used for controlled encoder and switches between each module by algorithm flow.
The importance scanning element is promptly carried out the importance judgement to generating the tree data according to formula (7), to determine F by wavelet coefficient being carried out importance scanning C, F DAnd F LMark bit map and mutual relation.This unit is the core of whole compression algorithm.
Descendants's coefficient significant element stores the maximum among all descendants of descendants's node, so that judge fast whether certain set relative threshold is important.
The wavelet coefficient information that the bit plane output unit obtains the importance scanning element according to the sequence of importance ordering (at first transmit most important bit-planes (
Figure A20081002248200111
), transmit least important bit-planes (n=0) at last) the binary bits plane that obtains.
Output module 6 is structure FIFO buffer unit in FPGA mainly, realizes the encoded data stream behind the compressed encoding is exported.
The workflow of this image compression system is seen accompanying drawing 6:
The one S01 is to the image capture module 1 of input, at first by the buffer memory of cache module 2 realizations to raw image data.In cache module 2, buffer is selected SDRAM for use, by construct sdram controller in FPGA, realizes the real-time buffer memory of big capacity continuous data stream.Data behind the buffer memory input to FPGA by cutting apart module 3.
The 2nd S02 when the SDRAM read data, according to block image thought, is cut apart module 3 and is switched by control and logic to the SDRAM address, realizes cutting apart original image.
Three S's 03 to cutting apart the subimage of module 3 outputs, at first realizes wavelet decomposition through wavelet transformation module 4.
The 4th S04, the wavelet conversion coefficient to 4 outputs of wavelet transformation module inputs to compression module 5.In compression module 5, handle the data flow of exporting after compressing by compression.
The 5th S05, the data that compressed encoding module 5 is exported input in the output module 6, by at FPGA internal build FIFO buffer unit, realize the output to the data flow after the image compression.
As seen, by above-mentioned functions module and corresponding operating process, realized image Real Time Compression based on FPGA.
The present invention can be widely used in the high-definition picture Real Time Compression.

Claims (8)

1, a kind of image compression system, it is characterized in that: it comprises image capture module (1), cache module (2), cuts apart module (3), wavelet transformation module (4), compression module (5) and output module (6), and image capture module (1) is used for real-time images acquired; Cache module (2) is used to realize the buffer memory to image; Cutting apart module (3) is used for image is cut apart; The wavelet transformation module is used to realize the wavelet transformation to image; Compression module is used to realize that the wavelet coefficient to after the conversion encodes; Output module is used for the output of the data flow behind the coding;
The real-time images acquired of image capture module (1) wherein, and an image of gathering is sent into cache module (2), behind buffer memory, cut apart module (3) image segmentation behind the buffer memory is become a plurality of image blocks, and the image block after will cutting apart is delivered to wavelet transformation module (4) image is carried out wavelet transformation, then the image after the conversion is sent into compression module (5), and in compression module (5), realized image compression encoding, export via image output module (6) at last.
2, image compression system according to claim 1 is characterized in that: described image capture module (1) adopts the cache image transducer to come real-time images acquired.
3, image compression system according to claim 2 is characterized in that: described image buffer storage imageing sensor is CCD or CMOS camera.
4, image compression system according to claim 1 is characterized in that: described cache module (2) is made of SDRAM, and the read-write control of SDRAM wherein realizes by a state machine is set in FPGA.
5, image compression system according to claim 1 is characterized in that: the described module (3) of cutting apart becomes a plurality of image blocks by the image segmentation of address switchover mode after buffer memory.
6, image compression system according to claim 1 is characterized in that: described wavelet transformation is (5,3) small echo; This small echo implementation method adopts the synthetic wavelet transformation that wavelet transformation module and BORDER PROCESSING unit are united two into one, and this conversion is divided into incipient stage, interstage and ending phase with every capable view data; This small echo implementation method is:
At first, to inputing to the view data of FPGA, through the pixel clock counter in the FPGA, send into mode selecting unit, in mode selecting unit, judge by the numerical value of counter lowest order and the register pair odd even address and the border of mode selecting unit, calculate low frequency and high fdrequency component according to above-mentioned small wave converting method;
Then, carrying out odd and even data at the dateout of mode selecting unit decomposes, after the decomposition, even address data one tunnel are directly sent into computing circuit, computing circuit is sent into after sending into register R1 time-delay again in another road, to guarantee synchronous sum operation, with the data addition of corresponding odd address, produce odd address high-frequency sub-band data after the even address data processing;
Send into computing circuit again after when wherein the odd address data are sent into register earlier and prolonged R2, to guarantee handling back data synchronization addition with even address, the even address data are directly sent into the preceding high-frequency sub-band data addition behind computing circuit and the process time-delay R1, send into the R3 time-delay simultaneously, data after the processing and the corresponding even address data addition that register R4 sends produce even address low frequency sub-band data;
Wherein, register R1 is the delay data of even address, and register R2 is the delay data of odd address, and register R3 is the high-frequency sub-band delay data of odd address, and register R4 is the delay data of even address.
7, image compression system according to claim 1 is characterized in that: described compression module (5) comprises overall control unit, descendants's coefficient significant element, importance scanning element and bit plane output unit;
Wherein, overall control unit is used for control and compiles encoder and switch between each module by algorithm flow; Descendants's coefficient significant element stores the maximum among all descendants of descendants's node, so that judge fast whether certain set relative threshold is important; The importance scanning element obtains F by former wavelet coefficient matrix is scanned from generating the tree data C, F dAnd F lMark bit map and inheritance each other; F wherein CFigure is used to point out the position of significant coefficient, F dFigure is used to refer to the position of important offspring's set, F lFigure is used to refer to the position of all offspring's set except that immediate successor.
8, image compression system according to claim 1 is characterized in that: the described module (3) of cutting apart comes image is cut apart according to the size of image size and processor interior storage capacity.
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