CN101316352A - Method and device for implementing multiple pictures of conference television system, video gateway and implementing method thereof - Google Patents
Method and device for implementing multiple pictures of conference television system, video gateway and implementing method thereof Download PDFInfo
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Abstract
The invention discloses a method for realizing multiple pictures of a video conferphone system, which comprises the steps that: a digital signal processor and a video bit stream input and output module are configured according to instructions of the system; when a video bit stream is inputted, the digital signal processor decodes and encodes videos inputted from each path. The invention also discloses a device for realizing the multiple pictures of the video conferphone system, which comprises a storage module, a master CPU, the video bit stream input and output module, a connecting module, a display module and a plurality of digital signal processors. The device is easy for resource collocation and has good extendibility and high design flexibility ratio. In addition, the invention also discloses a video gateway which comprises the storage module, the master CPU, a data input and output module, the connecting module and a plurality of digital signal processors. When in work, the digital signal processors and the data input and output module are configured according to the instructions of the system; when data is inputted, the digital signal processors decode and encode the data of each path, thus being capable of collocating resources flexibly.
Description
Technical field
The present invention relates to video processing technique, be specifically related to implementation method and device, a kind of video gateway and its implementation of a kind of multiple pictures of conference television system.
Background technology
Video conferencing has obtained in the field of demand counterpart using widely as a kind of advanced person's means of communication.These applications comprise government's meeting, remote teaching, remote diagnosis and trans-regional enterprise's meeting etc.TV conference system makes the participant that is separated by thousands of miles as poly-one, and is on the spot in person, exchanges conveniently, directly perceived, accurate, and for the user has saved spending, improved operating efficiency.
The implement device of existing multiple pictures of conference television system mainly is made of master cpu, display module and number of digital signal processor, the general tree topology that adopts of this device, be that master cpu and all digital signal processors are connected on same the high-speed bus, and between each digital signal processor by high-speed interface, transmit direction according to data predicted stream and connect, here, a group of pictures can only be realized by signal processing by the set of number signal processor that the high-speed interface interconnection is arranged.When the implement device of existing multiple pictures of conference television system moves, at first according to system command video code flow is distributed to each digital signal processor by high-speed bus by master cpu, after the digital signal processor of interconnection carries out signal processing, the video code flow of finishing dealing with is sent to master cpu by high-speed bus, by master cpu video code flow is sent to display module at last and shows.
Be not difficult to find out, the implement device of existing multiple pictures of conference television system, because transmitting direction according to data predicted stream between each digital signal processor connects, so, the quantity of digital signal processor in the device, the function of each digital signal processor and the flow direction of the video code flow between digital signal processor are relatively-stationary, be that TV conference system can picture displayed group number, and the frame numbers that every group of pictures specifically comprises is relatively-stationary, so, the implement device of existing multiple pictures of conference television system is easy care not, poor expandability, and the flexible design degree is low, and, in the implement device of existing multiple pictures of conference television system, master cpu and all digital signal processors are connected on same the high-speed bus, the video code flow between each part of system or the transmission of instruction all need by this high-speed bus, so, limited to the HD video code stream disposal ability that the video codes flow is bigger, be unfavorable for the realization of high definition multiple images.
In addition, in the prior art, the realization of video gateway is owing to be subjected to and the similar restriction of the implement device of multiple pictures of conference television system of the present invention, and when realizing the video coupling of multi-protocols, multiple speed code stream, multiple picture format, resource allocation is dumb.
Summary of the invention
In view of this, main purpose of the present invention is to provide a kind of implementation method and device of multiple pictures of conference television system, can improve many pictures image quality resolution, be easy to resource allocation, extensibility is good, flexible design degree height, and a kind of video gateway and its implementation proposed, when realizing the video coupling of multi-protocols, multiple speed code stream, multiple picture format, can the flexible allocation resource.
For achieving the above object, technical scheme of the present invention is achieved in that
A kind of implementation method of multiple pictures of conference television system, this method comprises:
A, master cpu download to each digital signal processor and operation respectively with the application program in the memory module;
B, master cpu are configured digital signal processor and video code flow input/output module according to system command;
C, in video code flow when input, arranged, after each road input video that digital signal processor transmits the video code flow input/output module is decoded and encoded, be sent to display module by the video code flow input/output module again and show.
Comprise step before the described step a: master cpu reads working procedure and the operation in the memory module.
The described application program of step a comprises coded program and decoding program.
Many pictures group number is carried in the described system command of step b at least, and every group of frame numbers that comprises respectively.
Step b is described to comprise step after the video code flow input/output module is configured: master cpu notice video code flow input/output module is opened the video code flow I/O channel.
Step b described to digital signal processor be configured into:
B1, master cpu determine the digital signal processor that will use, and determine the flow direction of video code flow between the function of described each digital signal processor and digital signal processor; Described function refers to be responsible for decoding or coding;
B2, master cpu are to the described digital signal processor transmitting control commands that will use of step b1;
B3, digital signal processor handle accordingly according to the control command of receiving;
The described video code flow input/output module is configured to: the input video code stream that the video code flow input/output module need be handled is configured on the input link of digital signal processor of the described responsible decoding of step b1; Video code flow after the digital signal processor processes that step b1 is responsible for encoding is configured on the output link of video code flow input/output module.
The function that the described control command of step b2 is carried digital signal processor at least; Digital signal processor is that control command is also carried the flow direction of handling the rear video code stream when being responsible for the digital signal processor of decoding.
Step b3 is described handle accordingly into: digital signal processor is according to control command operation decoding or coded program; Digital signal processor is when being responsible for the digital signal processor of decoding, also comprises the flow direction of set handling rear video code stream.
Step c comprises:
C1, video code flow input/output module are sent to each road input video the digital signal processor of corresponding responsible decoding;
After c2, the digital signal processor of being responsible for decoding are decoded to input video, the processed video code stream is sent to the digital signal processor of corresponding responsible coding;
C3, the digital signal processor of being responsible for encoding are also encoded the synthetic many image modes of multi-channel video code stream, and the processed video code stream are sent to the video code flow input/output module;
C4, video code flow input/output module are sent to display module with video code flow and show.
Realize star-like connection or mesh interconnect by link block between the described digital signal processor, described link block is the high-speed bus of high-speed bus exchange chip or netted connection.
A kind of implement device of multiple pictures of conference television system, this device is mainly become by memory module, master cpu, video code flow input/output module, link block, display module and a plurality of bank of digital signal processors, wherein,
Memory module is used to store the working procedure of master cpu, the application program of digital signal processor and the number information of digital signal processor;
Master cpu is used to obtain the working procedure and the operation of memory module; The application program of memory module is downloaded to each digital signal processor respectively; Digital Signal Processing reason device is numbered; According to system command digital signal processor and video code flow input/output module are configured;
The video code flow input/output module is used for the video code flow of different video source input is sent to the digital signal processor that each is responsible for decoding, and the video code flow that the digital signal processor that will be responsible for encoding sends is sent to display module;
Link block is used to realize the interconnection between the digital signal processor;
Display module is used for carrying out video according to the video code flow that the video code flow input/output module sends and shows;
Digital signal processor is used for the video code flow of input is encoded or decoded.
Described link block realizes by the high-speed bus of high-speed bus exchange chip or netted connection.
The digital signal processor of described responsible decoding is used for the video code flow that the video code flow input/output module sends is decoded, and the digital signal processor that the processed video code stream is sent to corresponding responsible coding; The digital signal processor of being responsible for coding is used for the multi-channel video code stream that the digital signal processor of being responsible for decoding sends is encoded, and the processed video code stream is sent to the video code flow input/output module.
A kind of implementation method of video gateway, this method comprises:
D, master cpu download to each digital signal processor and operation respectively with the application program in the memory module;
E, master cpu are configured digital signal processor and data input/output module according to system command;
F, in data when input, arranged, after each circuit-switched data that digital signal processor transmits according to input/output module is decoded and encoded, export by the data input/output module again.
Comprise step before the described steps d: master cpu reads working procedure and the operation in the memory module.
The described application program of steps d comprises coded program and decoding program.
The described system command of step e is carried the way and the every circuit-switched data that need deal with data at least and is handled the type of front and back.
Step e is described to comprise step after the data input/output module is configured: master cpu notification data input/output module is opened the data I/O channel.
Step e described to digital signal processor be configured into:
E1, the definite digital signal processor that will use of master cpu, and determine the function of described each digital signal processor and the data flow between digital signal processor; Described function refers to be responsible for decoding or coding;
E2, master cpu are to the described digital signal processor transmitting control commands that will use of step e1;
E3, digital signal processor handle accordingly according to the control command of receiving;
The described data input/output module is configured to: each circuit-switched data that the data input/output module need be handled is configured on the input link of digital signal processor of the described responsible decoding of step e1; Data configuration after the digital signal processor processes that step e1 is responsible for encoding is to the output link of data input/output module.
The function that the described control command of step e2 is carried digital signal processor at least; Digital signal processor is that control command is also carried the flow direction of handling the back data when being responsible for the digital signal processor of decoding.
Step e3 is described handle accordingly into: digital signal processor when being responsible for the digital signal processor of decoding, move corresponding decoding program according to control command, and the flow direction of data after the set handling; Digital signal processor is when being responsible for the digital signal processor of coding, according to control command operation respective coding program.
Step f comprises:
F1, data input/output module are sent to each road input data the digital signal processor of corresponding responsible decoding;
After f2, the digital signal processor of being responsible for decoding are decoded to the input data, the data after handling are sent to the digital signal processor of corresponding responsible coding;
F3, the digital signal processor of being responsible for encoding are encoded to the data of receiving, and the data after will handling send to the output of data input/output module.
Realize star-like connection or mesh interconnect by link block between the described digital signal processor, described link block is the high-speed bus of high-speed bus exchange chip or netted connection.
A kind of video gateway, this video gateway are mainly become by memory module, master cpu, data input/output module, link block and a plurality of bank of digital signal processors, wherein,
Memory module is used to store the working procedure of master cpu, the application program of digital signal processor and the number information of digital signal processor;
Master cpu is used to obtain the working procedure and the operation of memory module; The application program of memory module is downloaded to each digital signal processor respectively; Digital Signal Processing reason device is numbered; According to system command digital signal processor and video code flow input/output module are configured;
The data input/output module is used for the data of different pieces of information source input are sent to the digital signal processor that each is responsible for decoding, and the data of the digital signal processor transmission of coding are responsible in output;
Link block is used to realize the interconnection between the digital signal processor;
Digital signal processor is used for the data of input are encoded or decoded.
Described link block realizes by the high-speed bus of high-speed bus exchange chip or netted connection.
The digital signal processor of described responsible decoding be used for the data that the data input/output module sends are decoded, and the data after will handling sends to the digital signal processor of corresponding responsible coding; The digital signal processor of being responsible for coding is used for the data that the digital signal processor of being responsible for decoding sends are encoded, and the data after will handling send to the data input/output module.
The implementation method and the device of the multiple pictures of conference television system that the present invention proposes, make the multi-disc digital signal processor become star-like connection or mesh interconnect by link block, after master cpu is received system command, finish configuration according to system command to the flow direction of video code flow between digital signal processor and digital signal processor, when the video code flow input was arranged, the video code flow input/output module was decoded the digital signal processor that each road input video is sent to corresponding responsible decoding; The digital signal processor of being responsible for decoding sends to the processed video code stream digital signal processor of corresponding responsible coding again; The digital signal processor of being responsible for coding sends to the video code flow input/output module with the synthetic many image modes of multi-channel video code stream and after encoding with the processed video code stream; By the video code flow input/output module video code flow being sent to display module at last shows.Adopt the implementation method and the device of multiple pictures of conference television system of the present invention, owing to the interconnection that can realize flexibly by link block between the digital signal processor, so, be easy to resource allocation, good, the flexible design degree height of extensibility; Equally, video gateway and its implementation that the present invention proposes, owing to the interconnection that can realize flexibly by link block between the digital signal processor, so when realizing the video coupling of multi-protocols, multiple speed code stream, multiple picture format, can the flexible allocation resource.
Description of drawings
Fig. 1 is the implement device structure chart of multiple pictures of conference television system of the present invention;
Fig. 2 is the implementation method flow chart of multiple pictures of conference television system of the present invention;
Fig. 3 is a kind of structure chart of video gateway.
Embodiment
The present invention realizes that the basic thought of multiple pictures of conference television system is: make the multi-disc digital signal processor become star-like connection or mesh interconnect by link block, after master cpu is received system command, finish configuration according to system command to the flow direction of video code flow between digital signal processor and digital signal processor, when the video code flow input was arranged, the video code flow input/output module was decoded the digital signal processor that each road input video is sent to corresponding responsible decoding; The digital signal processor of being responsible for decoding sends to the processed video code stream digital signal processor of corresponding responsible coding again; The digital signal processor of being responsible for coding sends to the video code flow input/output module with the synthetic many image modes of multi-channel video code stream and after encoding with the processed video code stream; By the video code flow input/output module video code flow being sent to display module at last shows.Below in conjunction with specific embodiment and accompanying drawing the present invention is described in further detail.
Fig. 1 is the implement device structure chart of multiple pictures of conference television system of the present invention, as shown in Figure 1, the implement device of multiple pictures of conference television system of the present invention is mainly become by memory module, master cpu, video code flow input/output module, link block, display module and a plurality of bank of digital signal processors.Wherein,
Memory module is used to store the working procedure of master cpu, the application program of digital signal processor and the number information of digital signal processor;
Master cpu is used to obtain the working procedure and the operation of memory module; The application program of memory module is downloaded to each digital signal processor respectively; Digital Signal Processing reason device is numbered; According to system command digital signal processor and video code flow input/output module are configured;
The video code flow input/output module is used for the video code flow of different video source input is sent to the digital signal processor that each is responsible for decoding, and the video code flow that sends of the digital signal processor that will be responsible for encoding is sent to display module and shows;
Link block is used to realize the interconnection between the digital signal processor, can realize by the high-speed bus exchange chip, also can be by the high-speed bus realization of netted connection;
Display module is used for carrying out video according to the video code flow that the video code flow input/output module sends and shows;
Digital signal processor is divided into the digital signal processor of being responsible for decoding and the digital signal processor of being responsible for coding, be responsible for the digital signal processor of decoding, be used for the video code flow that the video code flow input/output module sends is decoded, and the digital signal processor that the processed video code stream is sent to corresponding responsible coding; The digital signal processor of being responsible for coding is used for the video code flow that the digital signal processor of being responsible for decoding sends is encoded, and the processed video code stream is sent to the video code flow input/output module.
Fig. 2 is the implementation method flow chart of multiple pictures of conference television system of the present invention, and as shown in Figure 2, the implementation method of multiple pictures of conference television system of the present invention mainly may further comprise the steps:
Step 201: after powering on, master cpu reads the working procedure and the operation of memory module.
Step 202: master cpu downloads to each digital signal processor and operation respectively with the application program in the memory module.
The application program that master cpu downloads to each digital signal processor is identical, includes coded program and decoding program.Here, master cpu also can be numbered each digital signal processor, promptly writes its corresponding sheet number in the specific register of each digital signal processor, and simultaneously, master cpu is kept at memory module with number information.
Step 203: master cpu receiving system instruction.
Here, the information that system command is carried generally comprises many pictures group number, and every group of frame numbers that comprises respectively, and system command can also be specified the image size of picture.
Step 204: master cpu is determined the digital signal processor that will use according to system command, and determines the flow direction of video code flow between the function of described each digital signal processor and digital signal processor.
Here, many pictures group number that master cpu carries according to system command, and the every group of definite digital signal processor that will use of the frame numbers that comprises; The function of determining described each digital signal processor is: determine digital signal processor be responsible for the decoding or responsible coding; The flow direction of determining video code flow between digital signal processor is: set the digital signal processor that the digital signal processor of being responsible for decoding sends to decoded video data by link block corresponding execution coding.
For example, comprise eight digital signal processors in the implement device of multiple pictures of conference television system altogether, be numbered digital signal processor 1～digital signal processor 8 respectively, if the video that system command indication TV conference system shows should comprise two group of pictures, one group comprises three pictures, another group comprises two pictures, then master cpu can be selected Applied Digital signal processor 1～digital signal processor 7, wherein, digital signal processor 1 and digital signal processor 2 are responsible for coding, digital signal processor 3～digital signal processor 7 is responsible for decoding, digital signal processor 3～digital signal processor 5 sends to digital signal processor 1 with decoded video data, digital signal processor 6～digital signal processor 7 sends to digital signal processor 2 with decoded video data, like this, the corresponding group of pictures of the output of digital signal processor 1, corresponding another group of pictures of the output of digital signal processor 2.Here, digital signal processor 8 is in wait state always.
Here, link block can realize by the high-speed bus exchange chip, also can realize by the high-speed bus of netted connection.
Step 205: master cpu is to the described digital signal processor transmitting control commands that will use of step 204, and digital signal processor handles accordingly according to control command.
Here, master cpu is according to the task of each digital signal processor and the number information of memory module, send different control commands or not transmitting control commands to digital signal processor, generally speaking, control command is carried the function of digital signal processor at least, for the control command that sends to the digital signal processor of being responsible for decoding, also should comprise the flow direction of handling the rear video code stream, if the image size of picture has been specified in system command, then send to the control command of the digital signal processor of being responsible for coding, also should comprise this parameter.
If master cpu sends to the control command designation number signal processor of digital signal processor 3 and is responsible for decoding, and its processed video code stream sends to digital signal processor 1, after then digital signal processor 3 is received control command, the operation decoding program, and digital signal processor 3 is set by link block decoded video code flow is sent to digital signal processor 1.
Step 206: master cpu is configured the video code flow input/output module.
Here, master cpu is configured the video code flow input/output module, be about to the video code flow after the digital signal processor processes of the described responsible coding of step 204 to be configured on the output link of video code flow input/output module on the input link of digital signal processor that input video code stream that the video code flow input/output module need handle is configured to the described responsible decoding of step 204.
Step 207: master cpu notice video code flow input/output module is opened the video code flow I/O channel.
Here, the video code flow input/output module is opened the video code flow I/O channel and is represented that the implement device of multiple pictures of conference television system is ready.
Step 208: when the video code flow input was arranged, the video code flow input/output module was sent to each road input video the digital signal processor of corresponding responsible decoding.
Step 209: after the digital signal processor of being responsible for decoding is decoded to input video, the processed video code stream is sent to the digital signal processor of corresponding responsible coding.
Step 210: the digital signal processor of being responsible for coding is also encoded the synthetic many image modes of multi-channel video code stream, and the processed video code stream is sent to the video code flow input/output module.
Step 211: the video code flow input/output module is sent to display module with video code flow and shows.
Adopt the implementation method of multiple pictures of conference television system of the present invention, and the implement device of multiple pictures of conference television system comprises under the situation of eight digital signal processors, if the input video code stream is the HD video code stream, the many pictures of single group are synthetic and coding is maximum can realize 7 pictures of 720P or 6 pictures of 1080I, can realize 2 pictures and 4 pictures of 720P when picture more than two groups is synthetic under the situation of no multicast simultaneously, perhaps realize 2 pictures of 720P and 3 pictures of 1080I simultaneously, under the situation of using multicast, conference group number and number of pictures also can further increase; If the input video code stream is a SD D1 video code flow, then can realize sprite more than 56 tunnel, promptly support many groups 16 frame sessions commonly used, sprite number and malti-screen are abundanter; And be the video conferencing of CIF for the resolution that generally adopts now, its conference group number and many frame numbers have several times to improve again than D1, so the present invention can improve many pictures image quality resolution, is easy to resource allocation, extensibility is good, flexible design degree height.
The implementation of multiple pictures of conference television system of the present invention is equally applicable to video gateway, and therefore, the present invention reintroduces a kind of video gateway.
Fig. 3 is a kind of structure chart of video gateway, and as shown in Figure 3, the video gateway that the present invention proposes is mainly become by memory module, master cpu, data input/output module, link block and a plurality of bank of digital signal processors.Wherein,
Memory module is used to store the working procedure of master cpu, the application program of digital signal processor and the number information of digital signal processor;
Master cpu is used to obtain the working procedure and the operation of memory module; The application program of memory module is downloaded to each digital signal processor respectively; Digital Signal Processing reason device is numbered; According to system command digital signal processor and video code flow input/output module are configured;
The data input/output module is used for the different input data in source are sent to the digital signal processor that each is responsible for decoding, and the data of exporting the digital signal processor transmission of described responsible coding;
Link block is used to realize the interconnection between the digital signal processor, can realize by the high-speed bus exchange chip, also can be by the high-speed bus realization of netted connection;
Digital signal processor is divided into the digital signal processor of being responsible for decoding and the digital signal processor of being responsible for coding, be responsible for the digital signal processor of decoding, be used for the input data that the data input/output module sends are decoded, and the data after will handling send to the digital signal processor of corresponding responsible coding; The digital signal processor of being responsible for coding is used for the data that the digital signal processor of being responsible for decoding sends are encoded, and the data after will handling send to the data input/output module.
The workflow of video gateway of the present invention comprises the steps:
Step 401: master cpu reads application program and the operation in the memory module.
Step 402: master cpu downloads to each digital signal processor and operation respectively with the application program in the memory module.
The application program that master cpu downloads to each digital signal processor is identical, includes coded program and decoding program.Because video gateway can relate to the data transaction of various protocols, multiple speed, multiple picture format, so described coded program generally comprises a plurality of different coded programs and decoding program with decoding program, with correspondence different coding requirement and decoding request.
Here, master cpu also can be numbered each digital signal processor, promptly writes its corresponding sheet number in the specific register of each digital signal processor, and simultaneously, master cpu is kept at memory module with number information.
Step 403: master cpu receiving system instruction.
Here, the system command information of carrying generally comprises the way that needs deal with data and the every circuit-switched data type before and after handling.
Step 404: master cpu is determined the digital signal processor that will use according to system command, and determines the flow direction of data between the function of described each digital signal processor and digital signal processor.
Here, the way of the master cpu need deal with data of carrying according to system command is determined the digital signal processor that will use; The function of determining each digital signal processor is: the type before and after handling according to every circuit-switched data, determine that digital signal processor is responsible for decoding or coding, and the decoding program or the coded program that need operation; The flow direction of determining data between digital signal processor is: set the digital signal processor that the digital signal processor of being responsible for decoding sends to decoded data by link block corresponding execution coding.
For example, video gateway comprises eight digital signal processors altogether, is numbered digital signal processor 1～digital signal processor 8 respectively, and the system command indication has two-way input data, one circuit-switched data is the A1 picture format, need be converted to the dateout that picture format is A2; The stream rate on another road is B1, need be converted to the dateout that stream rate is B2, then master cpu can Applied Digital signal processor 1～digital signal processor 4, wherein, digital signal processor 1 and digital signal processor 2 are responsible for coding, digital signal processor 3 and digital signal processor 4 are responsible for decoding, digital signal processor 3 sends to digital signal processor 1 with decoded data, digital signal processor 4 sends to digital signal processor 2 with decoded data, like this, the corresponding circuit-switched data of the output of digital signal processor 1, corresponding another circuit-switched data of the output of digital signal processor 2.Here, digital signal processor 5～digital signal processor 8 is in wait state always.This example is applicable to the HD video gateway that 720P is above, because, if the image resolution ratio in the video gateway is lower than 720P (as D1,4CIF, CIF), then only just can realizes coding and decoding function, and need not distribute two digital signal processors with a digital signal processor.
Here, link block can realize by the high-speed bus exchange chip, also can realize by the high-speed bus of netted connection.
Step 405: master cpu is to the digital signal processor transmitting control commands, and digital signal processor handles accordingly according to control command.
Here, master cpu is according to the task of each digital signal processor and the number information of memory module, send different control commands or not transmitting control commands to digital signal processor, generally speaking, control command is carried the digital signal processor function at least, be decoding program or the coded program that the designation number signal processor need move,, also should comprise the flow direction of handling the back data for the control command that sends to the digital signal processor of being responsible for decoding.
If master cpu sends to control command designation number signal processor operation decoding program x, the processing back data of digital signal processor 3 and sends to digital signal processor 1, after then digital signal processor 3 is received control command, operation decoding program x, and digital signal processor 3 is set by link block decoded data is sent to digital signal processor 1.
Step 406: master cpu is configured the data input/output module.
Here, master cpu is configured the data input/output module, be about to input data configuration that the data input/output module need handle to the input link of the digital signal processor of the described responsible decoding of step 404, with the data configuration after the digital signal processor processes of the described responsible coding of step 404 to the output link of data input/output module.
Step 407: master cpu notification data input/output module is opened the data I/O channel.
Here, the data input/output module is opened and is looked the data I/O channel and represent that video gateway is ready.
Step 408: when the data input was arranged, the data input/output module was sent to each road input data the digital signal processor of corresponding responsible decoding.
Step 409: after the digital signal processor of being responsible for decoding is decoded to the input data, the data after handling are sent to the digital signal processor of corresponding responsible coding.
Step 410: the digital signal processor of being responsible for coding is encoded to the data of receiving, and the data after will handling send to the data input/output module.
Step 411: data input/output module dateout.
The video gateway that adopts the present invention to propose, owing to can realize interconnection between the digital signal processor flexibly by the high-speed bus exchange chip, so, can effectively improve the efficient of the video coupling of multi-protocols, multiple speed code stream, multiple picture format.
The above is preferred embodiment of the present invention only, is not to be used to limit protection scope of the present invention.
Claims (26)
1, a kind of implementation method of multiple pictures of conference television system is characterized in that, this method comprises:
A, master cpu download to each digital signal processor and operation respectively with the application program in the memory module;
B, master cpu are configured digital signal processor and video code flow input/output module according to system command;
C, in video code flow when input, arranged, after each road input video that digital signal processor transmits the video code flow input/output module is decoded and encoded, be sent to display module by the video code flow input/output module again and show.
2, method according to claim 1 is characterized in that, comprises step before the described step a: master cpu reads working procedure and the operation in the memory module.
3, method according to claim 1 is characterized in that, the described application program of step a comprises coded program and decoding program.
4, method according to claim 1 is characterized in that, many pictures group number is carried in the described system command of step b at least, and every group of frame numbers that comprises respectively.
5, method according to claim 1 is characterized in that, step b is described to comprise step after the video code flow input/output module is configured: master cpu notice video code flow input/output module is opened the video code flow I/O channel.
6, method according to claim 1 is characterized in that, step b described to digital signal processor be configured into:
B1, master cpu determine the digital signal processor that will use, and determine the flow direction of video code flow between the function of described each digital signal processor and digital signal processor; Described function refers to be responsible for decoding or coding;
B2, master cpu are to the described digital signal processor transmitting control commands that will use of step b1;
B3, digital signal processor handle accordingly according to the control command of receiving;
The described video code flow input/output module is configured to: the input video code stream that the video code flow input/output module need be handled is configured on the input link of digital signal processor of the described responsible decoding of step b1; Video code flow after the digital signal processor processes that step b1 is responsible for encoding is configured on the output link of video code flow input/output module.
7, method according to claim 6 is characterized in that, the function that the described control command of step b2 is carried digital signal processor at least; Digital signal processor is that control command is also carried the flow direction of handling the rear video code stream when being responsible for the digital signal processor of decoding.
8, method according to claim 7 is characterized in that, step b3 is described handle accordingly into: digital signal processor is according to control command operation decoding or coded program; Digital signal processor is when being responsible for the digital signal processor of decoding, also comprises the flow direction of set handling rear video code stream.
9, according to the arbitrary described method of claim 6 to 8, it is characterized in that step c comprises:
C1, video code flow input/output module are sent to each road input video the digital signal processor of corresponding responsible decoding;
After c2, the digital signal processor of being responsible for decoding are decoded to input video, the processed video code stream is sent to the digital signal processor of corresponding responsible coding;
C3, the digital signal processor of being responsible for encoding are also encoded the synthetic many image modes of multi-channel video code stream, and the processed video code stream are sent to the video code flow input/output module;
C4, video code flow input/output module are sent to display module with video code flow and show.
According to the arbitrary described method of claim 1 to 8, it is characterized in that 10, realize star-like connection or mesh interconnect by link block between the described digital signal processor, described link block is the high-speed bus of high-speed bus exchange chip or netted connection.
11, a kind of implement device of multiple pictures of conference television system is characterized in that, this device is mainly become by memory module, master cpu, video code flow input/output module, link block, display module and a plurality of bank of digital signal processors, wherein,
Memory module is used to store the working procedure of master cpu, the application program of digital signal processor and the number information of digital signal processor;
Master cpu is used to obtain the working procedure and the operation of memory module; The application program of memory module is downloaded to each digital signal processor respectively; Digital Signal Processing reason device is numbered; According to system command digital signal processor and video code flow input/output module are configured;
The video code flow input/output module is used for the video code flow of different video source input is sent to the digital signal processor that each is responsible for decoding, and the video code flow that the digital signal processor that will be responsible for encoding sends is sent to display module;
Link block is used to realize the interconnection between the digital signal processor;
Display module is used for carrying out video according to the video code flow that the video code flow input/output module sends and shows;
Digital signal processor is used for the video code flow of input is encoded or decoded.
12, device according to claim 11 is characterized in that, described link block realizes by the high-speed bus of high-speed bus exchange chip or netted connection.
13, device according to claim 11, it is characterized in that, the digital signal processor of described responsible decoding is used for the video code flow that the video code flow input/output module sends is decoded, and the digital signal processor that the processed video code stream is sent to corresponding responsible coding; The digital signal processor of being responsible for coding is used for the multi-channel video code stream that the digital signal processor of being responsible for decoding sends is encoded, and the processed video code stream is sent to the video code flow input/output module.
14, a kind of implementation method of video gateway is characterized in that, this method comprises:
D, master cpu download to each digital signal processor and operation respectively with the application program in the memory module;
E, master cpu are configured digital signal processor and data input/output module according to system command;
F, in data when input, arranged, after each circuit-switched data that digital signal processor transmits according to input/output module is decoded and encoded, export by the data input/output module again.
15, method according to claim 14 is characterized in that, comprises step before the described steps d: master cpu reads working procedure and the operation in the memory module.
16, method according to claim 14 is characterized in that, the described application program of steps d comprises coded program and decoding program.
17, method according to claim 14 is characterized in that, the described system command of step e is carried the way and the every circuit-switched data that need deal with data at least and handled the type of front and back.
18, method according to claim 14 is characterized in that, step e is described to comprise step after the data input/output module is configured: master cpu notification data input/output module is opened the data I/O channel.
19, method according to claim 14 is characterized in that, step e described to digital signal processor be configured into:
E1, the definite digital signal processor that will use of master cpu, and determine the function of described each digital signal processor and the data flow between digital signal processor; Described function refers to be responsible for decoding or coding;
E2, master cpu are to the described digital signal processor transmitting control commands that will use of step e1;
E3, digital signal processor handle accordingly according to the control command of receiving;
The described data input/output module is configured to: each circuit-switched data that the data input/output module need be handled is configured on the input link of digital signal processor of the described responsible decoding of step e1; Data configuration after the digital signal processor processes that step e1 is responsible for encoding is to the output link of data input/output module.
20, method according to claim 19 is characterized in that, the function that the described control command of step e2 is carried digital signal processor at least; Digital signal processor is that control command is also carried the flow direction of handling the back data when being responsible for the digital signal processor of decoding.
21, method according to claim 20, it is characterized in that, step e3 is described handle accordingly into: digital signal processor when being responsible for the digital signal processor of decoding, move corresponding decoding program according to control command, and the flow direction of data after the set handling; Digital signal processor is when being responsible for the digital signal processor of coding, according to control command operation respective coding program.
22, according to the arbitrary described method of claim 19 to 21, it is characterized in that step f comprises:
F1, data input/output module are sent to each road input data the digital signal processor of corresponding responsible decoding;
After f2, the digital signal processor of being responsible for decoding are decoded to the input data, the data after handling are sent to the digital signal processor of corresponding responsible coding;
F3, the digital signal processor of being responsible for encoding are encoded to the data of receiving, and the data after will handling send to the output of data input/output module.
According to the arbitrary described method of claim 14 to 21, it is characterized in that 23, realize star-like connection or mesh interconnect by link block between the described digital signal processor, described link block is the high-speed bus of high-speed bus exchange chip or netted connection.
24, a kind of video gateway is characterized in that, this video gateway is mainly become by memory module, master cpu, data input/output module, link block and a plurality of bank of digital signal processors, wherein,
Memory module is used to store the working procedure of master cpu, the application program of digital signal processor and the number information of digital signal processor;
Master cpu is used to obtain the working procedure and the operation of memory module; The application program of memory module is downloaded to each digital signal processor respectively; Digital Signal Processing reason device is numbered; According to system command digital signal processor and video code flow input/output module are configured;
The data input/output module is used for the data of different pieces of information source input are sent to the digital signal processor that each is responsible for decoding, and the data of the digital signal processor transmission of coding are responsible in output;
Link block is used to realize the interconnection between the digital signal processor;
Digital signal processor is used for the data of input are encoded or decoded.
25, device according to claim 24 is characterized in that, described link block realizes by the high-speed bus of high-speed bus exchange chip or netted connection.
26, device according to claim 24, it is characterized in that, the digital signal processor of described responsible decoding be used for the data that the data input/output module sends are decoded, and the data after will handling sends to the digital signal processor of corresponding responsible coding; The digital signal processor of being responsible for coding is used for the data that the digital signal processor of being responsible for decoding sends are encoded, and the data after will handling send to the data input/output module.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102263930A (en) * | 2010-05-24 | 2011-11-30 | 杭州华三通信技术有限公司 | Method and device for broadcasting multiple pictures in video conference |
| CN104038394A (en) * | 2014-05-23 | 2014-09-10 | 北京航天发射技术研究所 | High-reliability electronic control system |
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| CN107124575A (en) * | 2017-04-14 | 2017-09-01 | 苏州科达科技股份有限公司 | A kind of media processing method, device and media server |
| CN109246449A (en) * | 2017-07-11 | 2019-01-18 | 中国移动通信集团重庆有限公司 | Video stream distributing method, device, equipment and computer storage medium |
| CN110602460A (en) * | 2019-09-20 | 2019-12-20 | 普联技术有限公司 | Video decoding wall-mounting control method, system and device |
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- 2008-07-01 CN CN2008101268619A patent/CN101316352B/en not_active Expired - Fee Related
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102263930A (en) * | 2010-05-24 | 2011-11-30 | 杭州华三通信技术有限公司 | Method and device for broadcasting multiple pictures in video conference |
| CN102263930B (en) * | 2010-05-24 | 2014-02-26 | 杭州华三通信技术有限公司 | Method and device for broadcasting multiple pictures in video conference |
| CN104038394A (en) * | 2014-05-23 | 2014-09-10 | 北京航天发射技术研究所 | High-reliability electronic control system |
| CN104038394B (en) * | 2014-05-23 | 2018-05-11 | 北京航天发射技术研究所 | High reliability electric-control system |
| CN106941598A (en) * | 2016-01-04 | 2017-07-11 | 中兴通讯股份有限公司 | Many picture bit stream synthetic methods, many picture bit streams synthesis control method and device |
| CN107124575A (en) * | 2017-04-14 | 2017-09-01 | 苏州科达科技股份有限公司 | A kind of media processing method, device and media server |
| CN109246449A (en) * | 2017-07-11 | 2019-01-18 | 中国移动通信集团重庆有限公司 | Video stream distributing method, device, equipment and computer storage medium |
| CN110602460A (en) * | 2019-09-20 | 2019-12-20 | 普联技术有限公司 | Video decoding wall-mounting control method, system and device |
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