CN101315762A - Image display system - Google Patents

Abstract

The invention provides an image display system which comprises a first pixel, a second pixel, a scanning signal line, a first data signal line and a second data signal line, wherein, the first pixel includes a first transistor coupled with an electrode of the first pixel and a first storage capacitor; the second pixel includes a second transistor coupled with the electrode of the second pixel and a second storage capacitor; whether the first transistor and the second transistor are conducted or not is determined by the scanning signal line; the first data signal line and the second data signal line respectively write a data voltage signal into the electrodes of the first pixel and the second pixel by the first transistor and the second transistor at a first time and a second time. The image display system of the invention is characterized in that: the first storage capacitor is designed according to voltage coupling offset generated by the electrode of the first pixel at the second time, so as to lead the first feed-through voltage of the electrode of the first pixel to compensate the voltage coupling offset.

Description

Image display system

Technical field

The present invention relates to a kind of image display system, will solve the colour cast problem of conventional image display system.

Background technology

The panel construction 100 of Fig. 1 diagram one traditional monitor, comprising a red pixel R, a green pixel G and a blue pixel B, each a free transistor T and a storage capacitors C _StConstitute.One scan signal wire Scan couples the gate terminal of described transistor T, transmits the described transistor T of one scan signal conduction.Above-mentioned pixel R, G, couple data signal line D respectively with the drain electrode end of the transistor T of B _r, D _g, and D _b

In order to reduce the input pin position of panel chip, above-mentioned panel 100 also comprises a demultiplexer 102, to make described pixel R, G, to share data voltage source Data with B.This demultiplexer 102 comprises three switch SW _r, SW _g, and SW _b, respectively by pulse signal CKH _r, CKH _g, and CKH _bControl.Fig. 2 is a kind of drive waveforms and the corresponding pixel voltage V of panel 100 _r, V _g, and V _bIn this illustrative examples, this panel 100 adopts a row inversion technique (row inversion).The above-mentioned pixel R of this sweep signal Scan conducting, G, with the transistor T of B during, this data voltage source Data will according to time sequencing transmits red, green, with blue pixel R, G, and the data voltage of B.For the data voltage on the Data of this data voltage source is sent in the corresponding pixel above-mentioned pulse signal CKH _r, CKH _g, and CKH _bWill to should data voltage the above-mentioned switch SW of source Data sequential start _r, SW _g, and SW _bObserve red, green, with the pixel voltage V of blue pixel _r, V _g, V _bCan find: the signal on the Data of this data voltage source will be in time point t ₁Write this red pixel R, in time point t ₂Write this green pixel G and in time point t ₃Write this blue pixel B.Because above-mentioned pixel R, G, with the voltage coupling each other of the pixel electrode of B, above-mentioned pixel R, G, with the pixel voltage V of B _r, V _g, V _bCan be with skew each other.As shown in the figure, in time point t ₂, green pixel voltage V _gVariation military order red pixel voltage V _rPromote (202) thereupon; In time point t ₃, blue pixel voltage V _bVariation military order green pixel voltage V _gPromote (204) thereupon, and and then make red pixel voltage Vr promote (206) thereupon.In this illustrative examples, the pixel voltage V of red pixel _rCan be subjected to green and blue pixel voltage V _g, V _bInfluence, its skew situation is the most serious.

In the illustrative examples of Fig. 2, this data voltage source Data offers above-mentioned pixel R, G, all identical with the data voltage size of B.This panel 100 adopts a NW (normally white) technology-be not printing opacity under the situation of voltage executing.Because in the NW panel, the voltage difference of pixel electrode and shared electrode (magnitude of voltage is Vcom) more then pixel is darker, so the serious red pixel R of skew will be the darkest, it will be the brightest not having the blue pixel B of voltage coupling skew.So panel 100 will be blue partially.If this panel 1 00 adopts be a NB (normally black) technology-do not execute under the situation of voltage light tight and voltage difference pixel electrode and shared electrode heal greatly then pixel brighter-then panel 100 will be red partially.

Summary of the invention

The present invention will provide a kind of image display system, not only as above-mentioned panel 100, can also eliminate the colour cast problem of above-mentioned panel 100 by sharing the pin number amount that this data voltage source Data reduces chip.

Being different from traditional panel 100 makes all pixels adopt identical storage capacitors C _St, the present invention will be the exclusive storage capacitors of each pixel design according to each pixel electrode because of the voltage coupling skew that the voltage coupling effect is produced.

As shown in Figure 2, this sweep signal Scan will be in time point t ₄The above-mentioned pixel R of stop conducting, G, with the transistor T of B.The voltage variety Δ V of this sweep signal Scan _Gate, will be respectively to above-mentioned pixel voltage V _r, V _g, and V _bProduce a feed-trough voltage (feedthrough voltage) V _Fr, V _Fg, and V _FbBecause above-mentioned feed-trough voltage is relevant with the storage capacitors of pixel.The present invention will be at the exclusive storage capacitors of each pixel design, by adjusting above-mentioned feed-trough voltage V _Fr, V _Fg, and V _Fb, compensate described pixel voltage V _r, V _g, V _bThe voltage coupling skew that is produced because of the voltage coupling effect (Fig. 2 202,204, with 206).

For above and other objects of the present invention, feature and advantage can be become apparent, cited below particularlyly go out preferred embodiment, and be described with reference to the accompanying drawings as follows.

Description of drawings

The panel construction of Fig. 1 diagram one traditional monitor;

Fig. 2 is a kind of drive waveforms and the corresponding pixel voltage V of Fig. 1 _r, V _g, and V _b

Fig. 3 is a kind of panel construction of the image display system of this case;

Fig. 4 is a kind of drive waveforms (R → G → B) and the corresponding pixel voltage V of Fig. 3 _r, V _g, and V _b

Fig. 5 adds panel construction shown in Figure 3 with transistorized stray capacitance in the liquid crystal capacitance of pixel and the pixel;

Fig. 6 is a kind of drive waveforms (B → G → R) and the corresponding pixel voltage V of Fig. 3 _r, V _g, and V _b

Fig. 7 is a kind of embodiment of this case;

Fig. 8 is the another kind of embodiment of this case; And

Fig. 9 is for using the device of this case.

The reference numeral explanation

100～traditional panel; 102～demultiplexer;

202,204,206～voltage coupling skew;

300～this case panel;

702～demultiplexer;

900～electronic installation; 902～picture element matrix;

904～display pannel; 906～input block;

B～blue pixel;

CKH _r, CKH _g, and CKH _b～frequency signal;

C _GdTransistorized grid leak utmost point stray capacitance in the～pixel;

C _LcThe liquid crystal capacitance of～pixel; The control signal of CS～demultiplexer;

C _St～storage capacitors;

C _Str, C _Stg, and C _StbThe storage capacitors of～red, green, blue pixel;

C _St1, C _St2, and C _St3～first, second, with the storage capacitors of the 3rd pixel;

Data～data voltage source;

D ₁, D ₂, and D ₃～data signal line;

D _r, D _g, and D _b～data signal line;

G～green pixel;

P ₁, P ₂, and P ₃～pixel;

R～red pixel;

Scan～scan signal line; SW _r, SW _g, and SW _b～switch;

T～transistor; T ₁, T ₂, and T ₃～transistor;

t ₁-t ₄～time point;

V _ComThe voltage of～shared electrode;

V _Fr, V _Fg, and V _FbThe feed-trough voltage of～red, green, blue pixel;

V _r, V _g, and V _b～red, green, blue pixel voltage;

V ₁, V ₂, and V ₃～first, second, with the 3rd pixel voltage;

The gap of the data voltage of Δ V～write pixel and the voltage of shared electrode;

Δ V _GateThe change in voltage of～sweep signal Scan; And

Δ V _r, Δ V _g, with Δ V _bThe voltage coupling skew of～red, green, blue pixel.

Embodiment

Fig. 3 is a kind of panel construction 300 of the application's image display system, comprising a red pixel R, a green pixel G and a blue pixel B.This red pixel R comprises and is coupled to a red pixel electrode (magnitude of voltage is V _r) a transistor T and a storage capacitors C _StrThis green pixel G comprises and is coupled to a green pixel electrode (magnitude of voltage is V _g) a transistor T and a storage capacitors C _StgThis blue pixel B comprises and is coupled to a blue pixel electrode (magnitude of voltage is V _b) a transistor T and a storage capacitors C _StbOne scan signal wire Scan couples the gate terminal of described transistor T, to transmit the described transistor T of one scan signal conduction.Above-mentioned pixel R, G, couple data signal line D respectively with the drain electrode end of the transistor T of B _r, D _g, and D _bIn order to reduce the input pin position of panel chip, panel 300 is the same with above-mentioned traditional panel 100, also comprises a demultiplexer 102, the described pixel R of military order, G, shares data voltage source Data with B.This demultiplexer 102 comprises three switch SW _r, SW _g, and SW _b, respectively by pulse signal CKH _r, CKH _g, and CKH _bControl.

Compare with Fig. 1, panel 300 is different from traditional panel 100 each pixel and all adopts identical storage capacitors C _St, panel 300 must be at each pixel R, G, the storage capacitors C exclusive with B design _Str, C _Stg, and C _Stb

Below with the magnitude of voltage V of drive waveforms shown in Figure 4 and each pixel electrode _r, V _g, V _bDescribed storage capacitors C is described _Str, C _Stg, and C _StbDesign concept.The driving of described pixel R, G and B is R → G → B in proper order.Signal on the Data of this data voltage source will be in time point t ₁Write this red pixel R, in time point t ₂Write this green pixel G and in time point t ₃Write this blue pixel B.This illustrative examples supposes that the character used in proper names and in rendering some foreign names horse parameter (gamma setting) of each pixel is all identical, and drives described pixel R, G and B with the same gray level value.This pixel voltage V _rIn time point t ₁～t ₂The magnitude of voltage that is locked will equal pixel voltage V _gIn time point t ₂～t ₃The magnitude of voltage that is locked, also will equal pixel voltage V _bIn time point t ₃～t ₄The magnitude of voltage that is locked, above-mentioned pixel voltage and is shared level V _ComGap be all Δ V.The voltage coupling each other of described pixel electrode, pixel voltage V are described as prior art _rWill be with pixel voltage V _gWith V _bThere is voltage coupling shifted by delta V in change _rAnd pixel voltage V _gWill be with pixel voltage V _bThere is voltage coupling shifted by delta V in change _g

Analyze pixel R shown in Figure 3, G, with the circuit structure of B, Fig. 5 also considers the liquid crystal capacitance C of each pixel _LcGrid leak utmost point stray capacitance C with transistor T in the pixel _GdWhen this sweep signal Scan closes described transistor T, the change in voltage Δ V of this sweep signal Scan _GateThe pixel voltage V of the described pixel R of military order, G, B _r, V _g, V _bDowngrade, the amplitude of downgrading is called feed-trough voltage (fredthroughvoltage) thereupon.As shown in Figure 4, at time point t ₄, described pixel voltage V _r, V _g, V _bCan corresponding above-mentioned change in voltage Δ V _GateA feed-trough voltage V of Chan Shenging respectively _Fr, V _Fg, and V _FbObserve the circuit of Fig. 5, can get described feed-trough voltage value V _Fr, V _Fg, and V _FbFor:

$V_{\mathrm{fr}}=\mathrm{\Δ}{V}_{\mathrm{gate}}\×\frac{C_{\mathrm{gd}}}{C_{\mathrm{str}}+C_{\mathrm{lc}}+C_{\mathrm{gd}}};$ (formula 1)

$V_{\mathrm{fg}}=\mathrm{\Δ}{V}_{\mathrm{gate}}\×\frac{C_{\mathrm{gd}}}{C_{\mathrm{stg}}+C_{\mathrm{lc}}+C_{\mathrm{gd}}};$ And (formula 2)

$V_{\mathrm{fb}}=\mathrm{\Δ}{V}_{\mathrm{gate}}\×\frac{C_{\mathrm{gd}}}{C_{\mathrm{stb}}+C_{\mathrm{lc}}+C_{\mathrm{gd}}}.$ (formula 3)

The present invention will be by the described storage capacitors C of design _Str, C _Stg, and C _StbAdjust described feed-trough voltage V _Fr, V _Fg, and V _Fb, to compensate above-mentioned voltage coupling shifted by delta V _rWith Δ V _g, eliminate the screen color offset phenomenon.

Consult the illustrative examples of Fig. 4, in order to eliminate the screen colour cast, described feed-trough voltage V _Fr, V _FgWith V _FbMust satisfy following equation:

ΔV+ΔV _r-V _fr＝ΔV+ΔV _g-V _fg＝ΔV-V _fb。

So V _Fr=Δ V _r+ V _FbAnd V _Fg=Δ V _g+ V _FbIn conjunction with above-mentioned formula 1 and 2, at the storage capacitors value C of blue pixel B _StbSet and gone out above-mentioned voltage coupling shifted by delta V by Computer Simulation _rWith Δ V _gPrerequisite under, above-mentioned storage capacitors C _Str, and C _StgPrinciple of design as follows:

$C_{\mathrm{str}}=\frac{{\mathrm{\ΔV}}_{\mathrm{gate}}\×C_{\mathrm{gd}}}{{\mathrm{\ΔV}}_r+V_{\mathrm{fb}}}-C_{\mathrm{lc}}-C_{\mathrm{gd}};$ And

$C_{\mathrm{stg}}=\frac{{\mathrm{\ΔV}}_{\mathrm{gate}}\×C_{\mathrm{gd}}}{{\mathrm{\ΔV}}_g+V_{\mathrm{fb}}}-C_{\mathrm{lc}}-C_{\mathrm{gd}};$

V wherein _FbEstimate and get via formula 3.

Yet, if the driving of above-mentioned pixel R → G → B order is different, above-mentioned storage capacitors C _Str, C _Stg, and C _StbPrinciple of design also must adjust thereupon.The driving of the R of pixel described in Fig. 6, G and B is B → G → R in proper order.Signal on the Data of this data voltage source will be in time point t ₁Write this blue pixel B, in time point t ₂Write this green pixel G and at time point t ₃Write this red pixel R.In order to eliminate the screen colour cast, described feed-trough voltage V _Fr, V _FgWith V _FbMust satisfy following equation:

ΔV+ΔV _b-V _fb＝ΔV+ΔV _g-V _fg＝ΔV-V _fr。

So V _Fb=Δ V _r+ V _FrAnd V _Fg=Δ V _g+ V _FrIn conjunction with above-mentioned formula 2 and 3, at the storage capacitors value C of this red pixel R _StrSet and gone out voltage coupling shifted by delta V by Computer Simulation _bWith Δ V _gPrerequisite under, above-mentioned storage capacitors C _Stb, and C _StgPrinciple of design as follows:

$C_{\mathrm{stb}}=\frac{{\mathrm{\ΔV}}_{\mathrm{gate}}\×C_{\mathrm{gd}}}{{\mathrm{\ΔV}}_b+V_{\mathrm{fr}}}-C_{\mathrm{lc}}-C_{\mathrm{gd}};$ And

$C_{\mathrm{stg}}=\frac{{\mathrm{\ΔV}}_{\mathrm{gate}}\×C_{\mathrm{gd}}}{{\mathrm{\ΔV}}_g+V_{\mathrm{fr}}}-C_{\mathrm{lc}}-C_{\mathrm{gd}};$

V wherein _FrGet via formula 1 estimation.

By the cited illustrative examples of Fig. 4 and Fig. 6 with and the storage capacitors design, can observe to draw a conclusion: anyly share same scan signal line Scan and write the pixel of data voltage that (for example R, G, B pixel are respectively at time point t in different time points ₁, t ₂, and t ₃Write data voltage) all can use its voltage of compensating technique of the present invention coupling skew.

Fig. 7 is one embodiment of the present invention, wherein describes an image display system.This image display system comprises one first and one second pixel P ₁With P ₂, one scan signal wire Scan and one first and one second data signal line D ₁With D ₂This first pixel P ₁Comprise a first transistor T ₁And one first storage capacitors C _St1This first storage capacitors C _St1(magnitude of voltage is V through one first pixel electrode ₁) couple this first transistor T ₁Source terminal.This second pixel P ₂Comprise a transistor seconds T ₂And one second storage capacitors C _St2This second storage capacitors C _St2(magnitude of voltage is V through one second pixel electrode ₂) couple this transistor seconds T ₂Source terminal.This scan signal line Scan couples above-mentioned first and transistor seconds T ₁With T ₂Gate terminal, in order to transmit this first and second transistor T of one scan signal conduction ₁With T ₂This first data signal line D ₁Couple this first transistor T ₁Drain electrode end.This second data signal line D ₂Couple this transistor seconds T ₂Drain electrode end.The embodiment military order one data voltage signal Data of Fig. 7 is via a demultiplexer 702 this first data signal line of input D ₁Or the second data signal line D ₂Under the control of a control signal CS, this data voltage signal Data is passed to this first data signal line D in a very first time ₁And be passed to this second data signal line D in one second time ₂This very first time is early than this second time.

When this second time, the voltage level V of this first pixel electrode ₁Can because of the voltage coupling effect along with this second pixel level V ₂Change.This first pixel voltage level V ₁Skew brightly be called voltage coupling skew.At above-mentioned first and second transistor T of stop conducting ₁With T ₂The time, the change in voltage of this scan signal line Scan can produce the feedthrough effect to this first pixel electrode, causes this first pixel level V ₁Displacement one first feed-trough voltage.Because this first feed-trough voltage value can be passed through this first storage capacitors value C _St1Adjust, present embodiment will design this first storage capacitors C according to this voltage coupling side-play amount _St1, make this first feed-trough voltage be compensated this voltage coupling skew.

The change in voltage of this scan signal line Scan also can produce the feedthrough effect to this second pixel electrode, causes this second pixel level V ₂Displacement one second feed-trough voltage.In another embodiment of the present invention, this first storage capacitors C _St1This first feed-trough voltage of design military order equal this second feed-trough voltage and this voltage coupling skew sum.In another embodiment of the present invention, this first storage capacitors C _St1Design will follow following formula:

${\mathrm{<figure-callout\; id="1"\; label="C\; st"\; filenames="A20071010572600131.png,A20071010572600161.png"\; state="\{\{state\}\}">C</figure-callout>}}_{\mathrm{st}}=\frac{{\mathrm{\&Delta;V}}_{\mathrm{gate}}\&times;{\mathrm{<figure-callout\; id="1"\; label="C\; gd"\; filenames="A20071010572600131.png,A20071010572600161.png"\; state="\{\{state\}\}">C</figure-callout>}}_{\mathrm{gd}}}{{\mathrm{\&Delta;<figure-callout\; id="1"\; label="V"\; filenames="A20071010572600131.png,A20071010572600161.png"\; state="\{\{state\}\}">V</figure-callout>}}_1+V_{f2}}-C_{\mathrm{lc}1}-{\mathrm{<figure-callout\; id="1"\; label="C\; gd"\; filenames="A20071010572600131.png,A20071010572600161.png"\; state="\{\{state\}\}">C</figure-callout>}}_{\mathrm{gd}},$

Wherein, C _Gd1Be this first transistor T ₁Gate terminal and the stray capacitance between the drain electrode end, C _Lc1Be this first pixel P ₁Liquid crystal capacitance, Δ V _GateChange in voltage for this sweep signal Scan.Δ V ₁For this voltage coupling skew, can get by Computer Simulation in advance.V _F2Be this second feed-trough voltage, its value can be by this second storage capacitors C _St2, this transistor seconds T ₂Gate terminal and the stray capacitance C between the drain electrode end _Gd2, and this second pixel P ₂Liquid crystal capacitance C _Lc2Calculate and get, for

${\mathrm{\&Delta;V}}_{\mathrm{gate}}\&times;\frac{C_{\mathrm{gd}2}}{{\mathrm{<figure-callout\; id="2"\; label="C\; st"\; filenames="A20071010572600181.png"\; state="\{\{state\}\}">C</figure-callout>}}_{\mathrm{st}}+{\mathrm{<figure-callout\; id="2"\; label="C\; lc"\; filenames="A20071010572600181.png"\; state="\{\{state\}\}">C</figure-callout>}}_{\mathrm{lc}}+{\mathrm{<figure-callout\; id="2"\; label="C\; gd"\; filenames="A20071010572600181.png"\; state="\{\{state\}\}">C</figure-callout>}}_{\mathrm{gd}}}.$

In one embodiment, the liquid crystal capacitance of all pixels is all identical, and transistorized grid leak utmost point stray capacitance is also all identical in all pixels.At this moment, the first designed storage capacitors C of the present invention _St1Less than this second storage capacitors C _St2

Above-mentioned first and second pixel P ₁With P ₂But the partial pixel in the corresponding diagram 3.Under the driving order of R → G → B, this first pixel P ₁Corresponding above-mentioned green pixel G and this second pixel P ₂Corresponding above-mentioned blue pixel B.Under the driving order of B → G → R, this first pixel P ₁Corresponding above-mentioned green pixel G and this second pixel P ₂Corresponding above-mentioned red pixel R.

Fig. 8 is another embodiment of this case.Compare with Fig. 7, the image display system of Fig. 8 also comprises one the 3rd pixel P ₃And one the 3rd data signal line D ₃The 3rd pixel P ₃Comprise one the 3rd transistor T ₃And one the 3rd storage capacitors C _St3The 3rd storage capacitors C _St3(magnitude of voltage is V through one the 3rd pixel electrode ₃) couple the 3rd transistor T ₃Source terminal.The 3rd transistor T ₃Drain electrode couple the 3rd data signal line D ₃, and its gate terminal also couples this scan signal line Scan.Under the control of a control signal CS, a data voltage signal Data is passed to this first data signal line D in a very first time ₁, be passed to this second data signal line D in one second time ₂, and be passed to the 3rd data signal line D in one the 3rd time ₃This very first time is early than this second time, and this second time is early than this very first time.Present embodiment is except this first storage capacitors of the voltage coupling offset design C according to this first pixel electrode _St1(being compensated the voltage coupling skew of this first pixel electrode to make this first feed-trough voltage) also will be according to designed this first storage capacitors C of voltage coupling skew of this second pixel electrode _St2, compensated the voltage coupling skew of this second pixel electrode to make this second feed-trough voltage.

The change in voltage of this scan signal line Scan also can produce the feedthrough effect to the 3rd pixel electrode, causes the 3rd pixel level V ₃Displacement 1 the 3rd feed-trough voltage.In another embodiment of the present invention, this first storage capacitors C _St1This first feed-trough voltage of design military order equal the above-mentioned voltage coupling skew sum of the 3rd feed-trough voltage and this first pixel electrode; And this second storage capacitors C _St2This second feed-trough voltage of design military order equal the above-mentioned voltage coupling skew sum of the 3rd feed-trough voltage and this second pixel electrode.In another embodiment of the present invention, this first and second storage capacitors C _St1With C _St2Design will follow following formula:

${\mathrm{<figure-callout\; id="1"\; label="C\; st"\; filenames="A20071010572600131.png,A20071010572600161.png"\; state="\{\{state\}\}">C</figure-callout>}}_{\mathrm{st}}=\frac{{\mathrm{\&Delta;V}}_{\mathrm{gate}}\&times;{\mathrm{<figure-callout\; id="1"\; label="C\; gd"\; filenames="A20071010572600131.png,A20071010572600161.png"\; state="\{\{state\}\}">C</figure-callout>}}_{\mathrm{gd}}}{{\mathrm{\&Delta;<figure-callout\; id="1"\; label="V"\; filenames="A20071010572600131.png,A20071010572600161.png"\; state="\{\{state\}\}">V</figure-callout>}}_1+V_{f3}}-C_{\mathrm{lc}1}-{\mathrm{<figure-callout\; id="1"\; label="C\; gd"\; filenames="A20071010572600131.png,A20071010572600161.png"\; state="\{\{state\}\}">C</figure-callout>}}_{\mathrm{gd}},$ And

${\mathrm{<figure-callout\; id="2"\; label="C\; st"\; filenames="A20071010572600181.png"\; state="\{\{state\}\}">C</figure-callout>}}_{\mathrm{st}}=\frac{{\mathrm{\&Delta;V}}_{\mathrm{gate}}\&times;{\mathrm{<figure-callout\; id="2"\; label="C\; gd"\; filenames="A20071010572600181.png"\; state="\{\{state\}\}">C</figure-callout>}}_{\mathrm{gd}}}{{\mathrm{\&Delta;<figure-callout\; id="2"\; label="V"\; filenames="A20071010572600181.png"\; state="\{\{state\}\}">V</figure-callout>}}_2+V_{f3}}-C_{\mathrm{lc}2}-{\mathrm{<figure-callout\; id="2"\; label="C\; gd"\; filenames="A20071010572600181.png"\; state="\{\{state\}\}">C</figure-callout>}}_{\mathrm{gd}}$

Wherein, C _Gd1With C _Gd2Be respectively this first with this transistor seconds T ₁With T ₂Gate terminal and the stray capacitance between the drain electrode end, C _Lc1With C _Lc2Be respectively this first with this second pixel P ₁With P ₂Liquid crystal capacitance, Δ V _GateChange in voltage for this sweep signal Scan.Δ V ₁With Δ V ₂Be respectively the voltage coupling skew of this first and second pixel electrode, can get by Computer Simulation in advance.V _F3Be the 3rd feed-trough voltage, its value can be by the 3rd storage capacitors C _St3, the 3rd transistor T ₃Gate terminal and the stray capacitance C between the drain electrode end _Gd3, and the 3rd pixel P ₃Liquid crystal capacitance C _Lc3Calculate and get, for

${\mathrm{<figure-callout\; id="3"\; label="V\; f"\; filenames="A20071010572600161.png"\; state="\{\{state\}\}">V</figure-callout>}}_f={\mathrm{\&Delta;V}}_{\mathrm{gate}}\&times;\frac{C_{\mathrm{gd}3}}{{\mathrm{<figure-callout\; id="3"\; label="C\; st"\; filenames="A20071010572600161.png"\; state="\{\{state\}\}">C</figure-callout>}}_{\mathrm{st}}+{\mathrm{<figure-callout\; id="3"\; label="C\; lc"\; filenames="A20071010572600161.png"\; state="\{\{state\}\}">C</figure-callout>}}_{\mathrm{lc}}+{\mathrm{<figure-callout\; id="3"\; label="C\; gd"\; filenames="A20071010572600161.png"\; state="\{\{state\}\}">C</figure-callout>}}_{\mathrm{gd}}}.$

In one embodiment, the liquid crystal capacitance of all pixels is all identical, and transistorized grid leak utmost point stray capacitance is also all identical in all pixels.At this moment, the first designed storage capacitors C of the present invention _St1Less than this second storage capacitors C _St2, and this second storage capacitors C _St2Less than the 3rd storage capacitors C _St3

Above-mentioned first, second, with the 3rd pixel P ₁, P ₂With P ₃But the pixel in the corresponding diagram 3.Under the driving order of R → G → B, this first pixel P1 corresponding above-mentioned red pixel R, this second pixel P ₂Corresponding above-mentioned green pixel G and the 3rd pixel P ₃Corresponding above-mentioned blue pixel B.Under the driving order of B → G → R, this first pixel P ₁Corresponding above-mentioned blue pixel B, this second pixel P ₂Corresponding above-mentioned green pixel G and the 3rd pixel P ₃Corresponding above-mentioned red pixel R.

Fig. 9 diagram one electronic installation 900 is comprising a picture element matrix 902, a display pannel 904 and an input block 906.This input block 906 couples this display pannel 904, desires the image frame that shows with this display pannel 904 with reception.

Invention which is intended to be protected comprises this display pannel 904, and the mentioned pixel of the present invention can be formed this picture element matrix 902.Scan signal line that the present invention is mentioned and data signal line are the part of this display pannel 904.In addition, the scope of institute of the present invention desire protection also comprises this electronic installation 900.This electronic installation 900 can be a mobile phone, a digital camera, a PDA(Personal Digital Assistant), a mobile computer, a desk-top computer, a televisor, an automobile display or a portable optic disk player.

Though the present invention discloses as above with preferred embodiment; right its is not in order to limiting scope of the present invention, those skilled in the art, without departing from the spirit and scope of the present invention; can do some changes and modification, so protection scope of the present invention is as the criterion with claim of the present invention.

Claims (10)

1. image display system, comprising:

One first pixel comprises a first transistor and one first storage capacitors, and this first storage capacitors couples the source terminal of this first transistor through one first pixel electrode;

One second pixel comprises a transistor seconds and one second storage capacitors, and this second storage capacitors couples the source terminal of this transistor seconds through one second pixel electrode;

The one scan signal wire couples above-mentioned first and the gate terminal of transistor seconds, to transmit this first and second transistor of one scan signal conduction;

One first data signal line couples the drain electrode end of this first transistor, receives a data voltage signal in a very first time; And

One second data signal line couples the drain electrode end of this transistor seconds, receives this data voltage signal in one second time;

Wherein, this very first time is early than this second time,

Wherein, this first storage capacitors is designed according to the voltage coupling skew of this first pixel electrode, and military order one first feed-trough voltage is compensated this voltage coupling skew,

Wherein, this first pixel electrode is with i.e. this first feed-trough voltage of change in voltage that this sweep signal produced.

2. image display system as claimed in claim 1, wherein this second pixel electrode is one second feed-trough voltage with the change in voltage that this sweep signal produced.

3. image display system as claimed in claim 2, wherein this first feed-trough voltage of the design military order of this first storage capacitors equals this second feed-trough voltage and this voltage coupling skew sum.

4. image display system as claimed in claim 3, wherein the design of this first storage capacitors will be followed following formula:

$C_{\mathrm{st}1}=\frac{\mathrm{\&Delta;}{V}_{\mathrm{gate}}\&times;C_{\mathrm{gd}1}}{\mathrm{\&Delta;}{V}_1+V_{f2}}-C_{\mathrm{lc}1}-C_{\mathrm{gd}1},$

Wherein,

C _St1Be the capacitance of this first storage capacitors,

C _Gd1Be the gate terminal of this first transistor and the stray capacitance between the drain electrode end,

C _Lc1Be the liquid crystal capacitance of this first pixel,

Δ V _GateBe the change in voltage of this sweep signal,

Δ V ₁Be this voltage coupling skew, and

V _F2Be this second feed-trough voltage.

5. image display system as claimed in claim 4, wherein this second feed-trough voltage is got by following formula to calculating:

$V_{f2}=\mathrm{\&Delta;}{V}_{\mathrm{gate}}\&times;\frac{C_{\mathrm{gd}2}}{C_{\mathrm{st}2}+C_{\mathrm{lc}2}+C_{\mathrm{gd}2}},$

Wherein,

C _St2Be the capacitance of this second storage capacitors,

C _Gd2Be the gate terminal of this transistor seconds and the stray capacitance between the drain electrode end, and

C _1c2Liquid crystal capacitance for this second pixel.

6. image display system as claimed in claim 4, wherein this voltage coupling skew is got by Computer Simulation.

7. image display system as claimed in claim 1, wherein this first storage capacitors is less than this second storage capacitors.

8. image display system as claimed in claim 1 also comprises a display pannel, comprising above-mentioned first and second pixel, this scan signal line and above-mentioned first and second data signal line.

9. image display system as claimed in claim 8 also comprises an electronic installation, comprising:

The aforementioned display device panel; And

One input block couples this display pannel, desires the image frame that shows with this display pannel with reception.

10. image display system as claimed in claim 9, wherein this electronic installation is a mobile phone, a digital camera, a personal digital assistant, a mobile computer, a desk-top computer, a televisor, an automobile display or a portable optic disk player.

Images