CN101304374B - Sequence matching scheduling algorithm based on Clos network switching structure - Google Patents

Abstract

A sequential match scheduling algorithm based on a Clos network switching structure relates to the field of network crossbar scheduling algorithm, which comprises the following steps: step 1, output ports (the number being m) of an input module send request information to a corresponding output port of each middle module; step 2, the output port of each middle module selects one virtual output group of one sent request information and sends the allowed message to the virtual output group; step 3, the output port of each middle module selects an output port of the middle module and discharges the allowed message sent from the output port; step 4, the establishing process of the channel from a virtual output queue to the output port is finished; step 5, information cells are sent out and a pointer is updated; the fourth step and the fifth step are repeated until all the information cells are sent out or all the allowed message are accepted. The scheduling algorithm of the invention adopts a straight-through type match, the whole match is finished at one time and a many-to-many 'request-allow-accept' mode is adopted, which uses the scheduling opportunity to a maximum extent.

Description

A kind ofly pass through the preface Matching Scheduling based on the Clos network switch fabric

Technical field

The present invention relates to network exchange dispatching algorithm field, a kind ofly specifically pass through the preface Matching Scheduling based on the Clos network switch fabric.

Background technology

Along with the expansion day by day of computer network scale, be mainly reflected in two aspects, one is that the density of switching port increases, another is that the linear speed (Line Speed) of switching fabric (Switch Fabric) input/output port improves constantly.For this reason, the exchange capacity that the packet switching system of core network needs is increasing, the researcher has designed interconnected switching system of multistage satisfying the demand of exchange capacity for this reason, the Clos network switch fabric is exactly wherein a kind of interconnected switching system of typical multistage, the Clos network switch fabric is because it is directly perceived, redundancy is big, and can carry out the expansion of " iterative ", therefore is widely used in commercial product.Fig. 1 has provided existing C los network topology structure schematic diagram, the Clos network switch fabric is general to divide three grades, use crosspoint (the Switch Element of box indicating among Fig. 1, SE) also can be described as module, usually whole three grades of Clos network switch fabrics are described as: have k input module IM (Input module), m intermediate module CM (Center module) and k output module OM (Output module).Each input module is the (scale of n * m), wherein n is an input port quantity, m is output port quantity (identical with the quantity of intermediate module CM), each output module is the (scale of m * n), wherein n is an output port quantity, m is input port quantity (identical with the quantity of intermediate module CM), and therefore the scale of whole switching fabric is N=n * k.The Clos network switch fabric is divided into unblock and two types of rearrangeable unblocks (the n relation that depends on m), when satisfying m 〉=2n-1, Clos network switch fabric network is unblock, if m 〉=n, then Clos network switch fabric network is rearrangeable unblock.

The Clos topological structure has obtained to use widely, and as the ATLANTA switch of University of Washington, the PetaStar of Polytechnic University of New York is the example of successful Application.In industrial circle, DUNE Networks company has released the exchange chip of a series of support Clos network switch fabrics, and promoted in a large number solution based on the extensive switching system of Clos network switch fabric, expandable system structure (Scalable Architecture of NetworkDevices as the network equipment, what SAND), these schemes had is adopted by well-known equipment vendors.Therefore, the dispatching algorithm of Clos network switch fabric becomes the research focus in the switching fabric field always.

Existing C los network switch fabric network scheduling algorithm exists following limitation:

Generally speaking, the scheduling of Clos network switch fabric can be divided into two main problems, and promptly cell is assigned (Cell Dispatching) and route assignment (Route Assignment) problem.Implementation according to the Clos network switch fabric middle crosspoints that use at different levels, Clos network switch fabric network can be divided into S3 type and MSM type, the S3 type represents that three stage switching unit all uses empty (Space Division) structure of dividing, the MSM type represent first and the third level use to share storage organization (with " M " expression), only empty separation structure (with " S " expression) is used in the second level.In these two types, empty separation structure all adopts the Crossbar technology basically.

For S3 type Clos network switch fabric, the key problem of route assignment is how to select the connection from the input port to the output port fast for a given input/output end port coupling matrix.In theory, the route assignment problem can solve by matrix decomposition, but this method lacks practicality, and this shows two aspects: at first, matrix decomposition need be known traffic demand in advance, and this is relatively more difficult in actual applications; Secondly, even obtained the traffic demand matrix, the method computational complexity of matrix decomposition is too high, and when exchange was larger, existing hardware computing capability can't be accomplished real-time calculating.In actual applications, usually use didactic algorithm to solve the route assignment problem, as existing article (H.Jonathan Chao, Zhigang Jing, and Soung Y.Liew, " Matching Algorithms for Three-StageBufferless Clos Network Switches ", IEEE Communications Magazine, pp.46-54, Oct 2003) the PARALLEL MATCHING algorithm introduced.In addition, researchers such as Chao have proposed a series of matching algorithms, as f-MAC, and c-MAC and d-MAC etc., these algorithms all have in various degree improvement to the scheduling of S3 type Clos network switch fabric switching fabric.

The complexity of S3 type Clos network switch fabric on route assignment be not mainly owing to there is buffer memory to cause, because there is not buffer memory, must there be a kind of algorithm can dispatch the cell that enters switching fabric rapidly, otherwise will abandon the cell of in time not dispatched, but because the complexity of Clos network switch fabric self and the limitation of hardware computing capability, the researcher transfers research and development MSM type Clos network switch fabric.

MSM type Clos network switch fabric can be cached in common storage area with the cell that enters, and the pressure that this has alleviated scheduling undoubtedly to a certain extent also makes people can change the mentality of designing of dispatching algorithm.In traditional single phase switching fabric, Cheng Shu dispatching algorithm such as iSlip (N.McKeown, " The iSLIP Scheduling Algorithm forInput-Queues Switches ", IEEE/ACM Trans On Networking, pp.188-200, Apr 1999) that adopt is " request-permission-acceptance " mode (Request-Grant-Accept, be the RGA mode), strictly speaking, the RGA mode also is a kind of didactic algorithm, is a kind of efficient feasible algorithm but the success of iSlip on Cisco 12000 GSR switch router proved the RGA mode.By means of this thought, people such as Chao have proposed the dispatching algorithm CRRD dispatching algorithm and the mutation CMSD (concurrent master-slave round-robin dispatching) thereof of MSM type Clos network switch fabric.

The cell that the CRRD dispatching algorithm will enter input module IM is divided into some VOQ VOQ according to different destination interfaces, and then has adopted two stage dispatching algorithm.Phase I carries out in input module IM, each VOQ VOQ sets up matching relationship in the RGA mode to the output port of the input module IM at place, and second stage mainly is to be mated in the RGA mode by the output port of the input module IM that the match is successful in the phase I and the output port of intermediate module CM.After two stages, all the match is successful, then corresponding VOQ VOQ can send a cell by the circuit that has mated in next time slot.

The major defect of CRRD dispatching algorithm and CMSD dispatching algorithm is aspect following two.At first, twice coupling is to carry out in a kind of mode of relay.The CRRD dispatching algorithm has successively been carried out the coupling of twice RGA mode in input module IM and intermediate module CM, only when all successes of this twice coupling, corresponding VOQ VOQ could send cell in next time slot.Obviously, the success rate of the coupling of such serial mode only is to be matched to the product of power twice, makes overall performance decrease.As shown in Figure 2, the VOQ1 among the input module IM1 is receiving from L in the coupling first _I(1,1) and L _IThe permission message of (1,3), and VOQ1 selects to L _I(1,1) sends and accepts message so L _I(1,1) will be to L in the coupling of second stage _C(1,1) sends a request message.Similarly, the VOQ2 among the input module IM2 receives from L _I(2,1) and L _IThe permission message of (2,2), VOQ2 selects to L _I(2,1) send and accept message, so L _I(2,1) will be also to L in the coupling of second stage _C(1,1) sends a request message.This means at second stage L _I(2,1) will and L _I(1,1) competition L _CThe power of getting permission of (1,1).If in second stage, L _C(1,1) has selected L _I(1,1), interior VOQ2 of input module IM2 and L in the phase I at this moment _IThe coupling that (2,1) have formed will lose efficacy.This also meaned simultaneously in the phase I, L in the input module IM2 _IThe permission message that (2,2) send to VOQ2 has been wasted, and if the VOQ2 among the input module IM2 has selected L _I(2,2) can be set up fully and pass through L _CThe collision-free path of (2,1).Such situation may take place at any time at run duration, and therefore, two stage coupling can potentially reduce the power that is matched to of the overall situation.

Secondly, the CRRD dispatching algorithm is followed the RGA matching way of " many-one ", that is to say in the coupling of phase I, though VOQ may receive a plurality of permission message arbitrarily, can only accept one of them.Though the CRRD dispatching algorithm proposes and can use repeatedly iteration to improve the hit rate of coupling in the phase I, but repeatedly iteration can be brought bigger time overhead to system, therefore in actual applications, usually do not use repeatedly iteration, so the matching efficiency reduction problem that the many-one matching way produces is difficult to effective solution.

Summary of the invention

At the defective that exists in the prior art, the purpose of this invention is to provide and a kind ofly pass through the preface Matching Scheduling based on the Clos network switch fabric, employing through type coupling, whole matching process is once finished, take " request-permission-acceptance " mode of multi-to-multi simultaneously, at utmost utilized the dispatcher meeting.

For reaching above purpose, the technical scheme that the present invention takes is:

A kind ofly pass through the preface Matching Scheduling based on the Clos network switch fabric, said Clos network switch fabric comprises a switch chassis at least and is arranged on ply-yarn drill and backboard on the frame, front-end chip on each ply-yarn drill comprises k input module IM and k output module OM, back-end chip on the backboard comprises m intermediate module CM, each input module IM all has m output port, each intermediate module CM all has k input port and k output port, it is characterized in that: the said preface Matching Scheduling step of passing through is:

Step 1: request stage, each comprises the virtual output group VOG of non-NULL VOQ VOQ, the output module OM that finally will send to according to cell, m the output port of the input module IM by its place sends request message to the corresponding output port of each intermediate module CM

Step 2: in the permission stage, the output port of each intermediate module CM is according to output port pointer Lo _CSelected one of the position of Pointer is sent the virtual output group VOG of request message and is sent permission message to it,

Step 3: filtration stage, judge whether to take place current competition, as the permission message sent of the corresponding output end mouth that not have then directly to let pass, as current the competition taken place, then the input port of each intermediate module CM is according to input port pointer Li _CThe output port of selected this intermediate module CM in the position of Pointer and the permission message that this output port of letting pass sends,

Step 4: accept the stage, each receives the virtual output group VOG that allows message, by the selected non-NULL VOQ VOQ of VOG internal pointer VOGInnerPointer, again according to the selected output port that sends the intermediate module CM that allows message in the position of the outside pointer VOGExternPointer of VOG, virtual output group VOG accepts message to this output port transmission and sets up process with the passage of finishing from VOQ VOQ to this output port

Step 5: pointer update stage, non-NULL VOQ VOQ sends a cell by virtual output group VOG, upgrades the input port pointer Li of the outside pointer VOGExternPointer of VOG internal pointer VOGInnerPointer, VOG, intermediate module CM successively _CThe output port pointer Lo of Pointer and intermediate module CM _CPointer, repeating step 4, step 5 all are sent out or all permission message all is accepted until the cell of all non-NULL VOQ VOQ.

On the basis of technique scheme, the organizational form of VOQ VOQ is that (o), i is the numbering of input module to VOQ for i, p, and p is the input port numbering of input module, and o is the numbering of output module among the input module IM; Among the input module IM organizational form of virtual output group VOG be VOG (i, o), i is the numbering of input module, o is the numbering of output module, and virtual output group VOG is by several member VOQ (i, p, o) form, 1≤p≤n wherein, n is the number of the input port of each input module.

On the basis of technique scheme, the input port pointer Li of the outside pointer VOGExternPointer of VOG internal pointer VOGInnerPointer, VOG, intermediate module CM _CThe output port pointer Lo of Pointer and intermediate module CM _CAfter Pointer upgrades, the next position of the current coupling target of pointed.

The present invention has the following advantages:

1. adopt the through type coupling, whole matching process is once finished,

2. take " request-permission-acceptance " mode of multi-to-multi simultaneously, at utmost utilized the dispatcher meeting.

Description of drawings

The present invention has following accompanying drawing:

Fig. 1 existing C los network topology structure schematic diagram

Twice RGA mode of Fig. 2 CRRD dispatching algorithm mated schematic diagram

Fig. 3 Clos network switch fabric of the present invention schematic diagram

Fig. 4 is divided into the schematic diagram on the plane of k parallel coupling in logic

Fig. 5 VOG obtains the heap spherical model schematic diagram of dispatcher meeting

Fig. 6 is based on the large-scale switching system model schematic diagram of expansion Clos structure

The redundant implementation schematic diagram of N+1 in Fig. 7 Clos switching fabric

The contrast schematic diagram of SMACN and CRRD throughput under Fig. 8 burst mode

The contrast schematic diagram of SMACN and CRRD time delay under the prominent pattern of Fig. 9

Figure 10 VOGInnerPointer (1,1) state

Figure 11 VOGExternPointer (1,1) state

Figure 12 VOGInnerPointer (1,2) state

Figure 13 VOGExternPointer (1,2) state

Figure 14 VOGInnerPointer (3,1) state

Figure 15 VOGExternPointer (3,1) state

Figure 16 Li _CThe pointer Li of (1,3) _CPointer (1,3), Li _CThe pointer Li of (2,1) _CPointer (2,1), Li _CThe pointer Li of (3,1) _CPointer (3,1), Li _CThe pointer Li of (4,3) _CThe state of Pointer (4,3)

The output port pointer Lo of Figure 17 intermediate module _CPointer (1,1), Lo _CPointer (2,1), Lo _CPointer (3,1), Lo _CPointer (4,1) state

The output port pointer Lo of four intermediate modules of Figure 18 _CPointer (1,2), Lo _CPointer (2,2), Lo _CPointer (3,2), Lo _CPointer (4,2) state

Figure 19 VOGInnerPointer (1,1), VOGExternPointer (1,1), Li _CPointer (2,1), Lo _CState after Pointer (2,1) pointer upgrades

Figure 20 VOGInnerPointer (1,1), VOGExternPointer (1,1), Li _CPointer (3,1), Lo _CState after Pointer (3,1) pointer upgrades

Figure 21 VOGInnerPointer (3,1), VOGExternPointer (3,1), Li _CPointer (4,3), Lo _CState after Pointer (4,1) pointer upgrades

Figure 22 VOGInnerPointer (1,2), VOGExternPointer (1,2), Li _CPointer (4,1), Lo _CState after Pointer (4,2) pointer upgrades

Figure 23 VOGInnerPointer (1,2), VOGExternPointer (1,2), Li _CPointer (1,1), Lo _CState after Pointer (1,2) pointer upgrades

Embodiment

Below in conjunction with accompanying drawing the present invention is described in further detail.

Of the present inventionly a kind ofly pass through the preface Matching Scheduling based on the Clos network switch fabric, said Clos network switch fabric comprises a switch chassis at least and is arranged on ply-yarn drill and backboard on the frame, front-end chip on each ply-yarn drill comprises k input module IM and k output module OM, back-end chip on the backboard comprises m intermediate module CM, each input module IM all has m output port, each intermediate module CM all has k input port and k output port, and the said preface Matching Scheduling step of passing through is:

Step 1: request stage, each comprises the virtual output group VOG of non-NULL VOQ VOQ, the output module OM that finally will send to according to cell, m the output port of the input module IM by its place sends request message to the corresponding output port of each intermediate module CM

Step 2: in the permission stage, the output port of each intermediate module CM is according to output port pointer Lo _CSelected one of the position of Pointer is sent the virtual output group VOG of request message and is sent permission message to it,

Step 3: filtration stage, judge whether to take place current competition, as the permission message sent of the corresponding output end mouth that not have then directly to let pass, as current the competition taken place, then the input port of each intermediate module CM is according to input port pointer Li _CThe output port of selected this intermediate module CM in the position of Pointer and the permission message that this output port of letting pass sends,

Step 4: accept the stage, each receives the virtual output group VOG that allows message, by the selected non-NULL VOQ VOQ of VOG internal pointer VOGInnerPointer, again according to the selected output port that sends the intermediate module CM that allows message in the position of the outside pointer VOGExternPointer of VOG, virtual output group VOG accepts message to this output port transmission and sets up process with the passage of finishing from VOQ VOQ to this output port

Step 5: pointer update stage, non-NULL VOQ VOQ sends a cell by virtual output group VOG, upgrades the input port pointer Li of the outside pointer VOGExternPointer of VOG internal pointer VOGInnerPointer, VOG, intermediate module CM successively _CThe output port pointer Lo of Pointer and intermediate module CM _CPointer, repeating step 4, step 5 all are sent out or all permission message all is accepted until the cell of all non-NULL VOQ VOQ.

On the basis of technique scheme, the organizational form of VOQ VOQ is that (o), i is the numbering of input module to VOQ for i, p, and p is the input port numbering of input module, and o is the numbering of output module among the input module IM; Among the input module IM organizational form of virtual output group VOG be VOG (i, o), i is the numbering of input module, o is the numbering of output module, and virtual output group VOG is by several member VOQ (i, p, o) form, 1≤p≤n wherein, n is the number of the input port of each input module.

On the basis of technique scheme, the input port pointer Li of the outside pointer VOGExternPointer of VOG internal pointer VOGInnerPointer, VOG, intermediate module CM _CThe output port pointer Lo of Pointer and intermediate module CM _CAfter Pointer upgrades, the next position of the current coupling target of pointed.Adopt this pointer update mode can improve algorithm efficiency.

Fig. 3 has provided one and has of the present inventionly had 3 input modules, and the Clos network switch fabric schematic diagram of 4 intermediate modules and 3 output modules is as example, and the Reference numeral implication among Fig. 3 is as follows:

(o): enter p the input port of input module IM (i), purpose is the VOQ that forms of the cell of output module OM (o) (1≤i, o≤k, 1≤p≤n) to VOQ VOQ for i, p.Wherein, k is the number of input module IM, and n is the input port quantity of input module IM.For example: VOQ (1,1,1) representative enters the 1st input port of input module IM (1), and purpose is the VOQ that the cell of output module OM (1) forms.

(i, o): purpose is the virtual output group of the VOQ formation of output module OM (o) to virtual output group VOG among the input module IM (i).(i, o) (i, p o) form (1≤p≤n) to virtual output group VOG by n VOQ VOQ.Wherein, n is the input port quantity of input module IM.For example: the virtual output group that the VOQ that it is output module OM (3) that VOG (1,3) represents the middle purpose of input module IM (1) forms.

The output port Lo of input module _I(i, r): the output port that links with intermediate module CM (r) among the input module IM (i), 1≤r≤m.Wherein, m is the number of intermediate module CM.For example: Lo _I(1,2) represents the output port that links with intermediate module CM (2) among the input module IM (1).

The output port Lo of intermediate module _C(r, j): the output port that links with output module OM (j) among the intermediate module CM (r), 1≤j≤k.Wherein, k is the number of input module IM.For example: Lo _C(2,2) represent the output port that links with output module OM (2) among the intermediate module CM (2).

The input port Li of intermediate module _C(r, i): the input port that links with input module IM (i) among the intermediate module CM (r), 1≤i≤k.Wherein, k is the number of input module IM.For example: Li _C(3,3) represent the input port that links with input module IM (3) among the intermediate module CM (3).

Dispatching algorithm of the present invention also relates to following pointer:

(i, o): (i, inner wheel o) is changeed pointer to virtual output group VOG to VOG internal pointer VOGInnerPointer, points to the current member VOQ that can send cell, so the wheel of this pointer commentaries on classics target one total n is individual.

(i, o): (i, outer wheels o) is changeed pointer to each VOG to the outside pointer VOGExternPointer of VOG, points to the Lo of current intermediate module CM (r) _C(r, o), and this VOG will be preferentially to this Lo _C(r, o) message is accepted in transmission.Note Lo _C(r o) is o the output port of each intermediate module CM (r), so the wheel of this pointer changes total m of target.

The output port pointer Lo of intermediate module CM _CPointer (r, j): each Lo _C(r, j) wheel under changes pointer, points to current VOG, this Lo _C(r j) sends permission message with override to this VOG that points to.Therefore total k the wheel of this pointer changes target, represents k to lay respectively at each input module IM respectively, and purpose is the VOG of output module OM (j).(referring to Fig. 4)

The input port pointer Li of intermediate module CM _CPointer (r, i): each Li _C(r, i) wheel under changes pointer, points to the Lo of current intermediate module CM _C(r, j), this Lo _C(r j) will preferentially get permission the permission message that oneself sends is passed through Li _C(r, i).The target of this pointed is each Lo among the identical intermediate module CM _C(r, j), therefore a total k wheel changes target.As Li _CIt is Lo that the wheel of Pointer (1,1) changes target _C(1,1), Lo _C(1,2), Lo _C(1,3) totally 3.

The RGA mode that preface Matching Scheduling SMACN (Sequential Matching Algorithm on Clos Network) has adopted " running through " formula of passing through based on the Clos network switch fabric of the present invention, this mode have been avoided the string type diminishing efficiency of two stages couplings.Further, by this preface coupling of passing through, the SMACN dispatching algorithm can logically be divided into the coupling of the overall situation plane (referring to Fig. 4) of k parallel coupling, and the matching process on these planes can carry out simultaneously.

The RGA matching way that the SMACN dispatching algorithm is used multi-to-multi utilizes the permission message that produces in each time slot more fully.

Remarkable different being of the exchange coupling on exchange on Clos network coupling and the Crossbar, the input port among the Crossbar only sent a request message to the destination interface of piling up message in the incipient stage of mating; And among the SMACN, each VOQ sends a request message to each CM by each output port of IM, therefore, and this " excessively " request mode that is a kind of.For iSlip at Crossbar, article (N.McKeown, " The iSLIP SchedulingAlgorithm for Input-Queues Switches ", IEEE/ACM Trans On Networking, pp.188-200.Apr.1999) research explanation, under uniform traffic pattern, its throughput can approach 100%.But the prerequisite of this conclusion is on Crossbar, and the number of input port and output port is identical.In order to study the throughput of SMACN, be necessary more in depth to study the efficient that the RGA mode is mated.After McKeown, researcher such as Li and Chao has obtained a series of progress in the extensive friendship of research system, their research mainly concentrates on interconnected switching system of Clos type multistage, furthers investigate and done relevant improvement but also the coupling of Crossbar has been done.For example they have proposed improvement algorithm DRRM (the Yihan Li of an iSlip, Shivendra Panwar, H.Jonathan Chao, On thePerformance of a Dual Round-Robin Switch, IEEE INFOCom 2001), Li RGA mode when analyzing the performance comparison of DRRM and iSlip has provided the model that new meaning is arranged very much, and we will adopt this model in ensuing analysis.For this reason, n request initiator of note participation RGA mode is I ₁..., I _n, a m permission side is Q ₁..., Q _m, the requesting party is based on (being iSlip) that wheel changes pointer RGA with the working method of permission side, at first provides as giving a definition:

Definition 1:(hits) if through a RGA operation, certain request initiator Ik (1≤k≤n) can receive successfully that at least one allows message, then claims this I _kRGA operation hits this time.

Definition 2:(S-is hungry to death) a given bigger natural number S, if the request initiator is I _k(1≤k≤n) still can not receive permission message after continuously through RGA operation of S wheel then claims I _kOn that S-has taken place is hungry to death.

We can obtain than one than the work of Li conclusion more generally, promptly following character:

Character 1: carry out 1 based on the iSlip algorithm of RGA at every turn and take turns iteration, when m 〉=n if request initiator's task is saturated, promptly all transmit a request to each permission side at every turn, then pass through the matching operation of limited number of time after, the request initiator can both realize that 100% request hits.

Proof: each request initiator I among the crack i that clocks _kThe permission message number of receiving, promptly those send and allow message to I _kThe number of permission side be v _{K, i}, then according to the iSlip algorithm, then set up: Simultaneously, all v _{K, i}Satisfy

$v_{k,i+1}=\left\{\begin{array}{cc}0& v_{k,i}\≤1,v_{k-1,i}=0\\ v_{k,i}-1& v_{k,i}>1,v_{k-1,i}=0\\ 1& v_{k,i}\≤1,v_{k-1,i}>0\\ v_{k,i}& v_{k,i}>1,v_{k-1,i}>0\end{array}\right.$

By the recurrence relation formula between above time slot, be not difficult to draw, there is a limited T, make when i 〉=T establishment v _{K, i}〉=1.That is to say that through the limited number of time coupling, the later coupling in each input side all can be hit.

Under even saturation volume, the coupling that is arranged in each CM can realize 100% hit rate in limited number of time coupling back when implementing the SMACN algorithm on the character 2:Clos network.

Proof: in the SMACN algorithm, will the be correlated with request message of VOG of each input port among the CM is relayed to the output port of each CM, the moderator P of output port _C(r j) changes pointer according to wheel and returns permission message.Among the given CM, each input port has constituted k requesting party, and each output port has constituted a k permission side.Under even saturation volume, the RGA process among the CM and evenly under the saturation volume RGA process of iSlip be consistent, therefore according to character 1, the coupling among the CM can realize 100% hit rate after passing through the limited number of time step.

When implementing the SMACN algorithm on the character 3:Clos network under even saturation volume, in each time slot each VOG of note at least B (1≤B≤n) probability of individual VOQ non-NULL is P _B, then satisfy:

$P_B\≥{\mathrm{\Σ}}_{i=B}^n{C}_n^B{\left(\frac{1}{k}\right)}^i{(1-\frac{1}{k})}^{n-i}---\left(1\right)$

Proof: consider that arbitrarily (i, v), this VOG is made of n the VOQ of IMi VOG.By hypothesis, the flow of Clos network input is uniformly, so the probability that each VOQ enters a cell in each time slot is 1/k, thereby has B VOQ to receive that separately the probability of a cell is in each time slot just

Therefore set up (1).

Each VOQ transmission cell contention or port can not occur in the character 4:SMACN algorithm.

Proof: in the step 3 (filtration stage) of SMACN algorithm, because each Li _COnly allow a Lo among this CM _CTherefore the permission message of sending is passed through, and is accepting the stage, and LoI at most only has one and accepts message and need pass through.Because each is accepted message and means with there being a cell to lead to OM along the individual message of accepting, so the cell of each transmission the contention phenomenon can not take place on its circuit that passes through and port in the SMACN algorithm.

Character 4 explanations, the degree of concurrence of SMACN algorithm on each CM is very high, and promptly the cell of each VOQ transmission can pass through m CM independently.

Character 5: be located in the Clos network shown in Figure 1 and satisfy m 〉=k.Under uniform saturation volume, the probability that each VOG generation S-scheduling is died of hunger is along with the increase of S is tending towards 0 when implementing the SMACN algorithm.Promptly It is right to make

It is hungry to death that S-takes place Pr{VOG }＜ε.

Proof: consider SMACN algorithm as shown in Figure 4, because each IM has formed k VOG according to the purpose OM that enters cell, the request target of each VOG is to lay respectively at the output port that is connected to corresponding OM among m the CM.

In each coupling k request initiator and m request permission side are arranged on plane, the flow on whole C los network is even when saturated, and each input flow rate that mates the plane also is even saturated.According to character 2,, this means that (j, permission message v) all can arrive certain VOG to each RRP smoothly because each CM can both realize 100% coupling in limited step RGA operation back.

Clocking, (i, the permission message number of v) receiving is crack tVOG

Then each coupling plane v (on 0≤v≤k-1), by above-mentioned analysis, when t is enough big, establishment:

${\mathrm{\Σ}}_{i=0}^{k-1}{g}_{i,v}^t=m---\left(2\right)$

(i v) receives at least one and allows message, if in S operation to mean VOG Then (i v) can not die of hunger by S-VOG.For this reason, we consider that VOG shown in Figure 5 obtains the heap spherical model schematic diagram of dispatcher meeting, and m ball put into k groove position, and the number of ball is represented on each groove position Value, as shown in Figure 5.We will prove, for arbitrarily small ε, if there is t sometime ₀, Then there is M ∈ N, makes

According to SMACN algorithm and formula (1), if

Then must there be certain i _-1, 0≤i _-1≤ k-1 satisfies

And to i arbitrarily _-1＜r≤i ₀,

Be i _-1Be to compare i ₀Little and apart from i ₀Nearest non-vacant slot.Do as one likes matter 3,

VOG (i _-1, v) will be to be not less than P _BProbability comprise B non-empty queue.Therefore

$P\{g_{i_{-1},\mathrm{<figure-callout\; id="0"\; label="v\; t"\; filenames="S2008100842659E00052.png"\; state="\{\{state\}\}">v</figure-callout>}}^{t_{}}=\max (0,g_{i_{-1},v}^{t_0}-B)\}\&GreaterEqual;P_B---\left(3\right)$

By the rotary press system of SMACN, VOG (i _-1, the chance number that has v) obtained to mate will be transferred to VOG (i _-1+ 1, v), so for

Have:

$P\{g_{i_{-1}+1,\mathrm{<figure-callout\; id="0"\; label="v\; t"\; filenames="S2008100842659E00052.png"\; state="\{\{state\}\}">v</figure-callout>}}^{t_{}}=B\}\&GreaterEqual;P_B---\left(4\right)$

Especially, get B=1, use (5-4) formula repeatedly, have

$P\{{\mathrm{<figure-callout\; id="0"\; label="g\; i"\; filenames="S2008100842659E00052.png"\; state="\{\{state\}\}">g</figure-callout>}}_{i_{}}^{{}_0,\mathrm{<figure-callout\; id="0"\; label="v\; t"\; filenames="S2008100842659E00052.png"\; state="\{\{state\}\}">v</figure-callout>}}=1\}\&GreaterEqual;P_1^{i_0-i_{-1}}---\left(5\right)$

Formula (5) illustrates, through i ₀-i _-1Individual time slot, VOG (i ₀, the probability that v) obtains a dispatcher meeting is not less than

That is to say, through i ₀-i _-1Individual time slot, VOG (i _-1, dispatcher v) has one and transfers to VOG (i ₀, the probability of v) going up is not less than

Promptly

Probability be no more than

Therefore using (5) formula repeatedly can also obtain:

$P\{{\mathrm{<figure-callout\; id="0"\; label="g\; i"\; filenames="S2008100842659E00052.png"\; state="\{\{state\}\}">g</figure-callout>}}_{i_{}}^{{}_0,\mathrm{<figure-callout\; id="0"\; label="v\; t"\; filenames="S2008100842659E00052.png"\; state="\{\{state\}\}">v</figure-callout>}}=0\}\&le;{\left(P_1^{i_0-i_{-1}}\right)}^K---\left(6\right)$

For the given ε in front, there is a natural number K ₀, make

So VOG (i ₀, v) at process K ₀(i ₀-i _-1) after the wheel RGA operation, still can not get dispatcher can probability will be less than ε.The conclusion of former proposition is set up.

Below sketch implementation and redundancy protecting:

As previously mentioned, the Clos topology can make up extendible large-scale switching system neatly.The large-scale switching system model schematic diagram based on expansion Clos structure has as shown in Figure 6 shown that use Clos makes up a model of large-scale switching system, switching system among the figure is by a frame (Chassis) and a series of ply-yarn drill (Line Card) and backboard formation, and the back-end chip (CM) on front-end chip on each ply-yarn drill (being IM and OM) and the backboard forms the Clos network.Use the iteration (Iteration) of Clos structure, can also further build ultra-large type switching system (Super Scale Switching System).For example, the topology of several frames according to Clos coupled together, can make up the switching system of 10T level.

Because the large-scale switching system based on the Clos structure is usually operated at the server layer, the stability and the reliability that therefore how to improve system to greatest extent become the problem that another receives publicity.The most frequently used means just are to use the mode of protection, and since the redundancy height of Clos network, realize that thereon redundancy protecting has natural advantage.

With regard to switching system, protection is all carried out in the place that " single point failure " takes place easily usually, for example switching backplane.In traditional switching system Design Mode, the key point of the single point failure really of switching backplane.But in the Clos topology, because that CM has is a plurality of, therefore strictly speaking, CM is not the key point of single point failure in the Clos topology of m＞1.Yet stable for what move, the protection of setting up N+1 remains a kind of important possibility.The scheme of carrying out the 4+1 redundancy protecting in CM can be referring to the redundant implementation schematic diagram of N+1 in the Clos switching fabric shown in Figure 7; owing to carried out the redundancy protecting of 4+1; when the load of system is very high; any one protected CM is if fault; the 5th CM can substitute this inefficacy CM and devote oneself to work at once, and the degree of shake takes place almost is inappreciable to the flow of system like this.Otherwise, if do not protect, allow five CM all devote oneself to work, under high load condition, if certain CM produces fault, the throughput of system will significantly reduce so.In a word, whether take the protection of N+1, depend on planning and the expection of user, but for management plane and control plane, the protection of main control card (normally switching backplane) generally is absolutely necessary network at the datum plane of Clos switching fabric.

Below summary simulation analysis and discussion:

Simulate a k=3, the Clos switching fabric of n=m=4, wherein each crosspoint has equal link rate.Simultaneously, normalized traffic load has been adopted in experiment, promptly uses traffic load ρ ∈ [0,1] to represent the size of flow, represents that when ρ=1 flow imports according to linear speed.In switching fabric shown in Figure 3, have 12 input ports and 12 output ports, use λ _{I, j}The flow intensity of expression from input port i to output port j is so can form the traffic matrix of a 12*12.According to several universal flow scenes of passing judgment on the switching fabric throughput, two kinds of input flow rate patterns are adopted in experiment:

The uniform flux pattern is a kind of relatively more friendly flow rate mode, and under this flow rate mode, the performance of SMACN and CRRD almost overlaps, and all approaches 100%.Under this flow scene, the asymptotic performance of SMACN and CRRD does not have substantial difference, but find in the experiment, SMACN is with the remarkable advantage that CRRD compares, SMACN can be in the forwarding cycle seldom, reduce the conflict that takes place in the matching process rapidly, promptly realize 100% hit rate fast.For this reason, an extreme initial condition is deliberately chosen in experiment, promptly allows all VOGExternPointer pointer and Li _CThe target that the Pointer pointed is identical, thus conflict fully caused at first time slot, the match hit rate of two kinds of algorithms after the observation several slots, as shown in table 1:

	Time Slot 0	Time Slot 10	Time Slot 20	Time Slot 30
					CRRD	8.3％	25％	67％	83％
SMACN	8.3％	33％	83％	100％

The contrast of table 1SMACN and CRRD hit rate under uniform flux

From the result of last table as can be seen, SMACN is better than CRRD to the adaptive capacity of flow rate mode, this mainly is to be to mate in the mode of " one-to-many " because the coupling of SMACN is accepted in the process of message in transmission, this mode can be eliminated matching conflict fast, therefore for the switching of flow scene, the performance of SMACN is better than CRRD, and representative value is 32%, more than 23%, 20%.

Under the scene of burst flow, the flow scene of test remains uniformly according to the distribution of destination interface, but different with the complete uniform flux pattern of front, because flow is sudden, throughput can slightly descend along with the increase of flow input load.In the ON-OFF process, choose (probability that enters ON), be 3 time slots the average time of ON, be that the probability that meter enters the ON state at every turn is p under the such flow scene of 7 time slots the average time of OFF, then allows p change to 1 from 0 and can generate different input flow rate loads.The contrast schematic diagram of SMACN and CRRD throughput has shown CRRD and the throughput of SMACN under the different flow load under the burst mode shown in Figure 8, and the contrast schematic diagram of SMACN and CRRD time delay has shown the average queue length of two kinds of algorithms under different loads under the burst mode shown in Figure 9, has in fact portrayed under two kinds of dispatching algorithms unequally loaded and has transmitted time delay.Therefrom we are not difficult to find out, when input load had surpassed 0.7, throughput and queue length all can produce differentiation.But the differentiation of throughput is smaller, and the queue length of SMACN algorithm is littler than CRRD, and representative value is little by 50%, 40%, 33% and 37%.In general, SMACN will increase than CRRD.

In sum, using the multistage, interconnected to make up extensive switching fabric be to satisfy the switching system robustness, the effective means of extensibility, the switching fabric of Clos network are a kind of multistage interconnecting and switching structures that has application prospect, are used widely in industrial circle.Based on the Clos structure of sharing storage is main one of the scheme of building, and traditional dispatching method is CRRD on the Clos structure, and this is the dispatching method of a kind of iSlip of being similar to, but owing to be operated on the Clos topology, CRRD takes the RGA method of two stages relay.The major defect of CRRD is that matching precision is not high under non-homogeneous flow scene, and this paper has proposed the improvement project of a kind of CRRD, is called and passes through preface formula matching algorithm (SMACN).The improvement of the relative CRRD of SMACN mainly contains 2 points, at first is the RGA mode that adopts " running through " formula, has avoided the poor efficiency of twice use RGA generation; Next is " request-permission-acceptance " mode that has adopted one-to-many, and this mode meets the PARALLEL MATCHING under the Clos network particular topology, can form several parallel coupling planes thus, has improved the success rate of coupling.The deadlock probability that has proved SMACN in theory is infinitely small, though emulation experiment explanation SMACN is very little with the CRRD difference under the uniform flux scene, but under paroxysmal flow scene, SMACN has certain degree to improve than CRRD on throughput and forwarding time delay.

Below in conjunction with Fig. 3, further specify by a concrete coupling example and of the present inventionly to pass through the preface Matching Scheduling based on the Clos network switch fabric:

Suppose VOQ among the input module IM1 (1,1,1), VOQ (1,3,1) non-NULL (promptly having cell in formation, to wait scheduling), these two VOQ are the member VOQ of VOG (1,1); VOQ among the input module IM1 (1,2,2), VOQ (1,3,2) non-NULL (promptly having cell in formation, to wait scheduling), these two VOQ are the member VOQ of VOG (1,2); VOQ among the input module IM3 (3,1,1) non-NULL, this VOQ is the member VOQ of VOG (3,1).

Internal pointer VOGInnerPointer (1, the 1) state of supposing VOG this moment (1,1) as shown in figure 10, current pointer points to VOQ (1,4,1).The outside pointer VOGExternPointer of VOG (1,1) (1,1) state as shown in figure 11, current pointer points to Lo _C(4,1).

Internal pointer VOGInnerPointer (1, the 2) state of supposing VOG this moment (1,2) as shown in figure 12, current pointer points to VOQ (1,4,2).The outside pointer VOGExternPointer of VOG (1,2) (1,2) state as shown in figure 13, current pointer points to Lo _C(4,2).

Internal pointer VOGInnerPointer (3, the 1) state of supposing VOG this moment (3,1) as shown in figure 14, current pointer points to VOQ (3,3,1).Outside pointer VOGExternPointer (3, the 1) state of VOG (3,1) as shown in figure 15, current pointer points to Lo _C(2,1).

Suppose Li this moment _CThe pointer Li of (1,3) _CPointer (1,3), Li _CThe pointer Li of (2,1) _CPointer (2,1), Li _CThe pointer Li of (3,1) _CPointer (3,1), Li _CThe pointer Li of (4,3) _CThe state of Pointer (4,3) as shown in figure 16, Li _CThe pointer Li of (1,3) _CPointer (1,3) points to Lo _C(1,1), Li _CThe pointer Li of (2,1) _CPointer (2,1) points to Lo _C(2,1), Li _CThe pointer Li of (3,1) _CPointer (3,1) points to Lo _C(3,3), Li _CThe pointer Li of (4,3) _CPointer (4,3) points to Lo _C(4,2).

Suppose the output port Lo of four intermediate modules this moment _C(1,1), Lo _C(2,1), Lo _C(3,1), Lo _CThe pointer Lo of (4,1) _CPointer (1,1), Lo _CPointer (2,1), Lo _CPointer (3,1), Lo _CPointer (4,1) state as shown in figure 17, Lo _CPointer (1,1) points to VOG (3,1), Lo _CPointer (2,1) points to VOG (4,1), Lo _CPointer (3,1) points to VOG (1,1), Lo _CPointer (4,1) points to VOG (2,1).

Suppose the output port Lo of four intermediate modules this moment _C(1,2), Lo _C(2,2), Lo _C(3,2), Lo _CThe pointer Lo of (4,2) _CPointer (1,2), Lo _CPointer (2,2), Lo _CPointer (3,2), Lo _CPointer (4,2) state as shown in figure 18, Lo _CPointer (1,2) points to VOG (3,2), Lo _CPointer (2,2) points to VOG (4,2), Lo _CPointer (3,2) points to VOG (1,2), Lo _CPointer (4,2) points to VOG (2,2).

Suppose that above-mentioned pointer all upgrades by clockwise rotation, the then said preface Matching Scheduling step of passing through is:

Step 1:VOG (1,1) and VOG (3,1) send a request message Lo by each output port of the IM at place separately respectively to each CM _C(1,1), Lo _C(2,1), Lo _C(3,1), Lo _CThis two message will be received and handle in (4,1).VOG (1,2) sends a request message Lo by each output port of IM (1) to each CM _C(1,2), Lo _C(2,2), Lo _C(3,2), Lo _CThis message will be received and handle in (4,2).

As previously mentioned, (o): enter p the input port of input module IM (i), purpose is the VOQ that the cell of output module OM (o) forms to VOQ VOQ for i, p.By VOQ (1,1,1), VOQ (1,3,1) non-NULL its cell as can be known will send to OM1, and by VOQ (1,2,2), VOQ (1,3,2) non-NULL its cell as can be known will send to OM2, by VOQ (3,1,1) non-NULL as can be known its cell to send to OM1.So when by the VOG (3,1) at the VOG (1,1) at VOQ (1,1,1) place and VOQ (3,1,1) place after each CM sends a request message, from Fig. 3 we as can be known, have only Lo _C(1,1), Lo _C(2,1), Lo _C(3,1), Lo _C(4,1) link to each other with OM1, therefore have only Lo _C(1,1), Lo _C(2,1), Lo _C(3,1), Lo _CThis two message will be received and handle in (4,1).In like manner, when by the VOG (1,2) at VOQ (1,2,2) place after each CM sends a request message, from Fig. 3 we as can be known, have only Lo _C(1,2), Lo _C(2,2), Lo _C(3,2), Lo _C(4,2) link to each other with OM2, therefore have only Lo _C(1,2), Lo _C(2,2), Lo _C(3,2), Lo _CThis message will be received and handle in (4,2).

Step 2: consider Lo _CThe wheel of (1,1) changes pointer Lo _CPointer (1,1), owing to this pointed VOG (3,1) this moment, so Lo _C(1,1) will send to VOG (3,1) and allow message.Lo _CThe wheel of (2,1) changes pointer Lo _CPointer (2,1) current sensing VOG (4,1), according to the mode of clockwise rotation, VOG (1,1) is nearest apart from current pointer, so Lo _C(2,1) will send to VOG (1,1) and allow message.Same reason, Lo _C(3,1) will send to VOG (1,1) and allow message; Lo _C(4,1) will send to VOG (3,1) and allow message; Lo _C(1,2) will send to VOG (1,2) and allow message; Lo _C(2,2) will send to VOG (1,2) and allow message; Lo _C(3,2) will send to VOG (1,2) and allow message; Lo _C(4,2) will send to VOG (1,2) and allow message.

Step 3:Lo _CThe purpose of the permission message that (1,1) sends is VOG (3,1), and this message must be passed through Li _C(1,3), because Fig. 3 illustrates: CM1 has only Li _CThe IM3 at (1,3) and VOG (3,1) place links to each other; In like manner, Lo _CThe purpose of the permission message that (1,2) sends is VOG (1,2), and this message must be passed through Li _C(1,1), therefore, at filtration stage, CM1 does not compete, and these two allow message all to be let pass.

Lo _CThe purpose of the permission message that (2,1) send is VOG (1,1), and this message must be passed through Li _C(2,1), Lo _CThe purpose of the permission message that (2,2) send is VOG (1,2), and this message must be passed through Li _C(2,1), in the present example, Li _CCurrent competition has taken place here in (2,1), considers Li _CPointer (2,1) is because Li _CPointer (2,1) points to Lo _C(2,1), Lo therefore lets pass _CThe permission message that (2,1) send, and Lo _CThe permission message that (2,2) send is dropped.

Lo _CThe purpose of the permission message that (3,1) send is VOG (1,1), and this message must be passed through Li _C(3,1), Lo _CThe purpose of the permission message that (3,2) send is VOG (1,2), and this message must be passed through Li _C(3,1), in the present example, Li _CCurrent competition has also taken place here in (3,1), according to settling mode recited above, considers Li _CPointer (3,1), current this pointed Lo _C(3,3), Lo _C(3,1) are nearest apart from it, so clearance Lo _CThe permission message that (3,1) send, and Lo _CThe permission message that (3,2) send is dropped.

Lo _CThe purpose of the permission message that (4,1) send is VOG (3,1), and this message must be passed through Li _C(4,3), Lo _CThe purpose of the permission message that (4,2) send is VOG (1,2), and this message must be passed through Li _C(4,1), in the present example, Li _CCurrent competition does not take place here in (4,3), and these two allow message all to be let pass.

Step 4:VOG (1,1) receives from Lo _C(2,1) and Lo _CThe permission message that (3,1) send over is because the current sensing of internal pointer VOGInnerPointer (1, the 1) VOQ (1 of VOG (1,1), 4,1), according to the mode of clockwise rotation, VOQ (1,1,1) nearest apart from current pointer, so VOG (1,1) selects VOQ (1,1,1) to send cell.At this moment, the current sensing of outside pointer VOGExternPointer (1, the 1) Lo of VOG (1,1) _C(4,1) are according to the mode of clockwise rotation, Lo _C(2,1) are the permission senders of the message nearest apart from current pointer, so VOG (1,1) will be at first to Lo _C(2,1) send and accept message.This accepts message along Lo _C(2,1) send and allow the antipodal path of message to arrive Lo _C(2,1) therefore will be through Li _C(2,1).So, VOQ (1,1,1) is to Lo _CPath is set up fully between (2,1),

Step 5:VOQ (1,1,1) sends a cell, through Li _C(2,1) arrive Lo _C(2,1).On this road warp, VOGInnerPointer (1,1), VOGExternPointer (1,1), Li _CPointer (2,1), Lo _CThe pointer of Pointer (2,1) is advanced to the next position of the current target that obtains serving clockwise.Figure 19 has shown the state after these four pointers upgrade.

Owing to also have cell to need to send, below continue repeating step 4, step 5:

The current sensing of internal pointer VOGInnerPointer (1, the 1) VOQ (1,2,1) of step 4:VOG (1,1), according to the mode of clockwise rotation, VOQ (1,3,1) is nearest apart from current pointer, so VOG (1,1) prepares to select VOQ (1,3,1) to send cell.The current sensing of outside pointer VOGExternPointer (1, the 1) Lo of VOG (1,1) _C(3,1) are according to the mode of clockwise rotation, Lo _C(3,1) promptly are the permission senders of the message nearest apart from current pointer, so VOG (1,1) will be again to Lo _C(3,1) send and accept message.This accepts message along Lo _C(3,1) send and allow the antipodal path of message to arrive Lo _C(3,1) therefore will be through Li _C(3,1).Thus, VOQ (1,3,1) is to Lo _CPath is set up fully between (3,1),

Step 5:VOQ (1,3,1) sends a cell, through Li _C(3,1) arrive Lo _C(3,1).On this road warp, VOGInnerPointer (1,1), VOGExternPointer (1,1), Li _CPointer (3,1), Lo _CThe pointer of Pointer (3,1) is advanced to the next position of the current target that obtains serving clockwise.Figure 20 has shown the state after these four pointers upgrade.

Because VOG (1,1) has only two non-NULL VOQ, VOG (1,1) the epicycle coupling that disposed so far.Owing to also have the cell of VOQ (3,1,1) need send to OM1, below continue repeating step 4, step 5:

Step 4:VOG (3,1) receives from Lo _C(1,1) and Lo _CThe permission message of (4,1), the current sensing of internal pointer VOGInnerPointer (3, the 1) VOQ (3 of VOG (3,1), 3,1), nearest apart from current pointer according to the mode VOQ (3,1,1) of clockwise rotation, therefore VOG (3,1) selects VOQ (3,1,1) to send cell.In fact because VOG (3,1) only has a non-NULL VOQ (3,1,1), so VOG (3,1) also inevitable choice VOQ (3,1,1) send cell.The current sensing of outside pointer VOGExternPointer (3, the 1) Lo of VOG (3,1) _C(2,1) are according to the mode of clockwise rotation, Lo _C(4,1) are the permission senders of the message nearest apart from current pointer, so VOG (1,1) will be at first to Lo _C(4,1) send and accept message.This accepts message along Lo _C(4,1) send and allow the antipodal path of message to arrive Lo _C(4,1) therefore will be through Li _C(4,3).Thus, VOQ (3,1,1) is to Lo _CPath is set up fully between (4,1),

Step 5:VOQ (3,1,1) sends a cell, through Li _C(4,3) arrive Lo _C(4,1).On this road warp, VOGInnerPointer (3,1), VOGExternPointer (3,1), Li _CPointer (4,3), Lo _CThe pointer of Pointer (4,1) is advanced to the next position of the current target that obtains serving clockwise.Figure 21 has shown the state after these four pointers upgrade.

Because VOG (3,1) has only a non-NULL VOQ, VOG (3,1) the epicycle coupling that disposed so far.Below just finished the coupling scheduling process of the cell that need send to OM1.Following processes is the coupling scheduling that needs is sent to the cell of OM2.

Step 4:VOG (1,2) receives from Lo _C(1,2) and Lo _CThe permission message of (4,2), the current sensing of internal pointer VOGInnerPointer (1, the 2) VOQ (1 of VOG (1,2), 4,2), nearest apart from current pointer according to the mode VOQ (1,2,2) of clockwise rotation, therefore VOG (1,2) prepares to select VOQ (1,2,2) to send cell.The current sensing of outside pointer VOGExternPointer (1, the 2) Lo of VOG (1,2) _C(4,2) are according to the mode of clockwise rotation, Lo _C(4,2) are the permission senders of the message nearest apart from current pointer, so VOG (1,2) will be at first to Lo _C(4,2) send and accept message.This accepts message along Lo _C(4,2) send and allow the antipodal path of message to arrive Lo _C(4,2) therefore will be through Li _C(4,1).So, VOQ (1,2,2) is to Lo _CPath is set up fully between (4,2),

Step 5:VOQ (1,2,2) sends a cell, through Li _C(4,1) arrive Lo _C(4,2).On this road warp, VOGInnerPointer (1,2), VOGExternPointer (1,2), Li _CPointer (4,1), Lo _CThe pointer of Pointer (4,2) is advanced to the next position of the current target that obtains serving clockwise.Figure 22 has shown the state after these four pointers upgrade.

Owing to also have cell to need to send, below continue repeating step 4, step 5:

The current sensing of internal pointer VOGInnerPointer (1, the 2) VOQ (1,3,2) of step 4:VOG (1,2), according to the mode of clockwise rotation, VOQ (1,3,2) is nearest apart from current pointer, so VOG (1,2) prepares to select VOQ (1,3,2) to send cell.The current sensing of outside pointer VOGExternPointer (1, the 1) Lo of VOG (1,2) _C(1,2) is according to the mode of clockwise rotation, Lo _C(1,2) promptly is the permission sender of the message nearest apart from current pointer, so VOG (1,1) will be again to Lo _C(1,2) sends and accepts message.This accepts message along Lo _C(1,2) sends and allows the antipodal path of message to arrive Lo _C(1,2) therefore will be through Li _C(1,1).Thus, VOQ (1,3,2) is to Lo _CPath is set up fully between (1,2),

Step 5:VOQ (1,3,2) sends a cell, through Li _C(1,1) arrives Lo _C(1,2).On this road warp, VOGInnerPointer (1,2), VOGExternPointer (1,2), Li _CPointer (1,1), Lo _CThe pointer of Pointer (1,2) is advanced to the next position of the current target that obtains serving clockwise.Figure 23 has shown the state after these four pointers upgrade.

So far, just finished the coupling scheduling process of all cells that need send.

Claims (3)

1. one kind passes through the preface Matching Scheduling based on the Clos network switch fabric, said Clos network switch fabric comprises a switch chassis at least and is arranged on ply-yarn drill and backboard on the frame, front-end chip on each ply-yarn drill comprises k input module IM and k output module OM, back-end chip on the backboard comprises m intermediate module CM, each input module IM all has m output port, each intermediate module CM all has k input port and k output port, it is characterized in that: the said preface Matching Scheduling step of passing through is:

Step 1: request stage, each comprises the virtual output group VOG of non-NULL VOQ VOQ, the output module OM that finally will send to according to cell, m the output port of the input module IM by its place sends request message to the corresponding output port of each intermediate module CM

Step 2: in the permission stage, the output port of each intermediate module CM is according to output port pointer Lo _CSelected one of the position of Pointer is sent the virtual output group VOG of request message and is sent permission message to it,

Step 3: filtration stage, judge whether to take place current competition, as the permission message sent of the corresponding output end mouth that not have then directly to let pass, as current the competition taken place, then the input port of each intermediate module CM is according to input port pointer Li _CThe output port of selected this intermediate module CM in the position of Pointer and the permission message that this output port of letting pass sends,

Step 4: accept the stage, each receives the virtual output group VOG that allows message, by the selected non-NULL VOQ VOQ of VOG internal pointer VOGInnerPointer, again according to the selected output port that sends the intermediate module CM that allows message in the position of the outside pointer VOGExternPointer of VOG, virtual output group VOG accepts message to this output port transmission and sets up process with the passage of finishing from VOQ VOQ to this output port

Step 5: pointer update stage, non-NULL VOQ VOQ sends a cell by virtual output group VOG, upgrades the input port pointer Li of the outside pointer VOGExternPointer of VOG internal pointer VOGInnerPointer, VOG, intermediate module CM successively _CThe output port pointer Lo of Pointer and intermediate module CM _CPointer, repeating step 4, step 5 all are sent out or all permission message all is accepted until the cell of all non-NULL VOQ VOQ.

2. as claimed in claim 1ly pass through the preface Matching Scheduling based on the Clos network switch fabric, it is characterized in that: the organizational form of VOQ VOQ is VOQ (i among the input module IM, p, o), i is the numbering of input module, p is the input port numbering of input module, and o is the numbering of output module; Among the input module IM organizational form of virtual output group VOG be VOG (i, o), i is the numbering of input module, o is the numbering of output module, and virtual output group VOG is by several member VOQ (i, p, o) form, 1≤p≤n wherein, n is the number of the input port of each input module.

3. as claimed in claim 1 or 2 based on the Clos network switch fabric pass through the preface Matching Scheduling, it is characterized in that: the input port pointer Li of the outside pointer VOGExternPointer of VOG internal pointer VOGInnerPointer, VOG, intermediate module CM _CThe output port pointer Lo of Pointer and intermediate module CM _CAfter Pointer upgrades, the next position of the current coupling target of pointed.

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