CN101295991A - Receiving circuit - Google Patents
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- CN101295991A CN101295991A CNA2007100979924A CN200710097992A CN101295991A CN 101295991 A CN101295991 A CN 101295991A CN A2007100979924 A CNA2007100979924 A CN A2007100979924A CN 200710097992 A CN200710097992 A CN 200710097992A CN 101295991 A CN101295991 A CN 101295991A
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Abstract
The invention relates to a receiving circuit which is used for receiving a data signal and a clock signal and outputting an output data signal to a data driver. The data signal and the clock signal are low-swing amplitude differential signals and the receiving circuit comprises a data comparator, a data relay circuit, a clock comparator, a clock relay circuit and a flip-flop, wherein, the data comparator is driven by the data bias current and used for receiving the data signal and outputting a comparison data signal; the data relay circuit is used for receiving the comparison data signal; the clock comparator is driven by the clock bias current and used for receiving a clock signal and outputting a comparison clock signal; the clock relay circuit is used for receiving the comparison clock signal and the flip-flop is used for receiving the comparison data signal sent by the data relay circuit and the comparison clock signal sent by the clock relay circuit and outputting the output data signal. By adjusting at least one of the clock bias current and the data bias current, the phase difference of the comparison data signal and the comparison clock signal can be improved.
Description
Technical field
The present invention relates to a kind of receiving circuit of data driver, and particularly relate to a kind of in order to receive low-swing differential signals (Reduced swing differential signal, receiving circuit RSDS).
Background technology
Fig. 1 shows traditional low-swing differential signals (reduced swing differentialsignal, receiving circuit 100 RSDS).Receiving circuit 100 is in order to reception input data signal D1 and P1, and according to input time pulse signal C1, output output document signal S1 to S4.Wherein, input data signal D1, P1 and input time pulse signal C1 are low-swing differential signals.
Please refer to Fig. 1, comparator 131 receives input time pulse signal C1, and output according to this is time pulse signal C2 relatively.Relatively time pulse signal C2 is sent to flip-flop 117,119,128 and 130 through cabling 132 and buffer 133.Relatively time pulse signal C2 passes through cabling 132, buffer 133 and inverter 134 in addition, transfers anti-phase relatively time pulse signal C2 ' to, is sent to flip-flop 118 and 129.Wherein, flip-flop 117,119,128 and 130 is positive edge triggering.Flip- flop 118 and 129 is negative edge triggering.
Flip- flop 117 and 118 according to comparing time pulse signal C2 and anti-phase relatively time pulse signal C2 ', is obtained output document signal S2 and negative edge document signal T1 by comparing document signal D2 respectively.Wherein, the flip-flop 119 that negative edge document signal T1 triggers through positive edge is again adjusted sequential according to comparing time pulse signal C2, obtains exporting document signal S1.
Similarly, comparator 121 receives input data signal P1, and output according to this is document signal P2 relatively.Relatively document signal P2 is sent to flip- flop 128 and 129 respectively through cabling 122 and buffer 123 to 127.Flip- flop 128 and 129 according to comparing time pulse signal C2 and anti-phase relatively time pulse signal C2 ', is obtained output document signal S4 and negative edge document signal T2 by comparing document signal P2 respectively.Wherein, the flip-flop 130 that negative edge document signal T2 triggers through positive edge is again adjusted sequential according to comparing time pulse signal C2, obtains exporting document signal S3.Data comparator 111,121 is identical with the circuit of clock pulse comparator 131.
Because it is excessive that input time pulse signal C1 falls behind the phase difference of input data signal D1, P1, therefore, behind cabling 112 and 122 buffer is set, and comes retardation ratio than document signal D2 and P2.
In addition, because in traditional receiving circuit 100, because the distance of the flip-flop of comparator 111,121 and correspondence is unequal, so the length of cabling 112 and 122 is unequal.Therefore, after relatively document signal P1 and P2 transmitted through cabling 112 and 122 respectively, the time of delay was unequal.Therefore, need to adjust time of delay with the buffer of varying number.For comparing document signal P1, use four buffers 113 to 116.For comparing document signal P2, use five buffers 123 to 127.Thus, relatively document signal P1 is through the time of delay of cabling 112 and buffer 113 to 116, with relatively document signal P2 can be more consistent through the cabling 122 and the time of delay of buffer 123 to 127.
Yet buffer is very responsive to the change of driving voltage, when driving voltage changes, can change the time of delay of buffer.The tradition receiving circuit is should be under different driving voltage, and the time of delay of buffer can be different, so will make the comparison document signal through behind cabling and the buffer, its change time of delay.
Fig. 2 shows traditional receiving circuit under different driving voltage, through behind cabling 112 and the buffer 113 to 116, and received comparison document signal D2 of flip-flop 117 and an example of the graph of a relation of time pulse signal C2 relatively.Please refer to Fig. 2.Curve 201 is for comparing the waveform of time pulse signal.Curve 202 and 203 is respectively that traditional receiving circuit is under 3.3 volts at driving voltage, and relatively document signal D2 is at retention time situation (hold timecondition) and the waveform that time situation (setup time condition) is set.
When time tf, curve 201 forms negative edge.Triggering with negative edge is example, waveform 202,204 and 206 with respect to the 201 formed retention times of curve (hold time) th1, th2, th3 inequality.Formed that time (setup time) ts1, ts2, ts3 are set is inequality with respect to curve 201 for curve 203,205 and 207.As shown in Figure 2, different driving voltage can change the time of delay of buffer, and makes that relatively document signal changes with the phase difference that compares time pulse signal.
Therefore, for comparing document signal D1, after through cabling 112 and buffer 113 to 116, when time that is provided with that time that is provided with that comparison document signal D1 is corresponding with comparing time pulse signal C2 and retention time (hold time) can't meet flip-flop 117 and retention time, flip-flop 117 promptly may be obtained wrong output document signal S2.From the above, when wanting that traditional receiving circuit is applied to different driving voltage, need to consider the influence of driving voltage to buffer, and make use very inconvenient.
In addition, produce anti-phase relatively time pulse signal C2 ' with inverter 134, can make anti-phase comparison time pulse signal C2 ' and comparison time pulse signal C2 produce phase difference, promptly relatively time pulse signal C2 ' makes that with relatively time pulse signal C2 is asynchronous the flip- flop 118 and 129 that negative edge triggers may be by relatively document signal D1 and D2 obtain wrong negative edge document signal T1 and T2.
Summary of the invention
In view of this, purpose of the present invention just provides a kind of receiving circuit.By adjusting the bias current that drives comparator, make comparator comparison document signal of exporting and the phase difference that compares time pulse signal be met the time that is provided with and the retention time of corresponding flip-flop.And work as receiving circuit and be applied under the different driving voltage, bias current can't change and change along with driving voltage.Therefore, the comparison document signal exported of comparator the and relatively phase difference between time pulse signal can be along with driving voltage changes and change.
According to purpose of the present invention, a kind of receiving circuit is proposed, in order to reception document signal and time pulse signal, and the document signal of output output according to this is to the data driver.Document signal and time pulse signal be low-swing differential signals (reduced swing differential signal, RSDS).Receiving circuit comprises data comparator, data repeat circuit, clock pulse comparator, clock pulse repeat circuit and flip-flop.The data comparator drives it with the data bias current, and in order to receive document signal, output according to this is document signal relatively.The data repeat circuit receives relatively document signal.The clock pulse comparator drives it with the clock pulse bias current, and in order to the reception time pulse signal, and time pulse signal is compared in output according to this.The clock pulse repeat circuit is in order to receive relatively time pulse signal.Flip-flop transmits and next comparison document signal in order to receive by the data repeat circuit, the comparison time pulse signal that comes with being transmitted by the clock pulse repeat circuit, and the document signal of output output according to this.Wherein, the one at least of clock pulse bias current and data bias current is adjusted to and makes that document signal relatively and time pulse signal relatively are formed the time that is provided with and the retention time that time (setup time) and retention time (hold time) are met flip-flop be set.
According to purpose of the present invention, a kind of low-swing differential signals method of reseptance is proposed, be used for receiving circuit.Receiving circuit comprises data comparator, clock pulse comparator and flip-flop.This method comprises: at first, drive the data comparator with the data bias current, make the data comparator receive document signal, and output is according to this compared document signal to flip-flop.Then, drive the clock pulse comparator, make the clock pulse comparator receive time pulse signal, and output is according to this compared time pulse signal to flip-flop with the clock pulse bias current.Afterwards, adjust the one at least of clock pulse bias current and data bias current, making that document signal relatively and time pulse signal relatively are formed is provided with the time that is provided with and the retention time that time and retention time are met flip-flop, flip-flop is able to according to relatively document signal and relatively time pulse signal, output output document signal.
The invention provides a kind of receiving circuit, in order to receive first document signal and time pulse signal, and export the first output document signal according to this to the data driver, described first document signal and described time pulse signal are low-swing differential signals, described receiving circuit comprises: the first data comparator, drive it with the data bias current,, export first according to this and compare document signal in order to receive described first document signal; The first data repeat circuit compares document signal in order to receive described first; The clock pulse comparator drives it with the clock pulse bias current, in order to receiving described time pulse signal, and exports first time pulse signal relatively according to this; The first clock pulse repeat circuit compares time pulse signal in order to receive described first; And first flip-flop, transmit and described first document signal relatively that comes in order to receive by the described first data repeat circuit, first time pulse signal relatively that comes with transmitting by the described first clock pulse repeat circuit, and export the described first output document signal according to this; Wherein, the one at least of described clock pulse bias current and described data bias current is adjusted to and makes described first relatively document signal and the described first comparison time pulse signal are formed the time that is provided with and the retention time that time and retention time are met described first flip-flop be set.
Wherein, described receiving circuit is also in order to export the second output document signal, described clock pulse comparator also compares time pulse signal according to described time pulse signal output second, described first relatively time pulse signal relatively the polarity of time pulse signal is opposite with described second, and described first relatively time pulse signal and described second relatively time pulse signal is synchronous;
Wherein, described receiving circuit also comprises: the second clock pulse repeat circuit, compare time pulse signal in order to receive described second; And second flip-flop, in order to receive the described first comparison document signal by described first data repeat circuit transmission, the described second comparison time pulse signal with transmitting by the described second clock pulse repeat circuit, and export the described second output document signal according to this;
Wherein, described first flip-flop and described second flip-flop are respectively positive edge and trigger and bear the edge triggering; Wherein, the one at least of described clock pulse bias current and described data bias current is adjusted to and makes described first relatively document signal and the described second comparison time pulse signal are formed the time that is provided with and the retention time that time and retention time are met described second flip-flop be set.
Wherein, described receiving circuit also comprises the 3rd flip-flop, transmit and the next described second output document signal in order to receive described second flip-flop, the first comparison time pulse signal with transmitting by the described first clock pulse repeat circuit, and export the 3rd according to this and export document signal, wherein, described the 3rd flip-flop is that positive edge triggers.
Wherein, the described first clock pulse repeat circuit also comprises: the first clock pulse cabling receives the described first comparison time pulse signal by described clock pulse comparator transmission; At least one first buffer compares time pulse signal in order to receive and to cushion described first, and the described first comparison time pulse signal is sent to described first flip-flop.
Wherein, the described second clock pulse repeat circuit also comprises: the second clock pulse cabling receives the described second comparison time pulse signal by described clock pulse comparator transmission; At least one second buffer compares time pulse signal in order to receive and to cushion described second, and the described second comparison time pulse signal is sent to described second flip-flop.
Wherein, the equal in length of described first clock pulse cabling and the described second clock pulse cabling.
Wherein, the described first data repeat circuit also comprises: the first data cabling receives by the described first data comparator and transmits and next described relatively document signal; At least one buffer in order to receiving and to cushion described relatively document signal, and is sent to described first flip-flop with described relatively document signal.
Wherein, described receiving circuit also comprises: the second data comparator, receive second document signal, and output second is document signal relatively; The second data repeat circuit compares document signal in order to receive described second; The 4th flip-flop transmits and described second document signal relatively that comes in order to receive by the described second data repeat circuit, first time pulse signal relatively that comes with transmitting by the described first clock pulse repeat circuit, and export the 4th output document signal according to this.
Wherein, the described second data repeat circuit also comprises: the second data cabling receives the described second comparison document signal by described second data comparator transmission; And at least one second buffer, receive and cushion the described second comparison document signal, and the described second comparison document signal is sent to described the 4th flip-flop; Wherein, the equal in length walked of the length of the described first data cabling and described second data.
Wherein, the described first clock pulse repeat circuit also comprises: the first clock pulse cabling receives the described first comparison time pulse signal by described clock pulse comparator transmission; At least one buffer compares time pulse signal in order to receive and to cushion described first, and the described first comparison time pulse signal is sent to described first flip-flop.
Wherein, the length of the described first clock pulse cabling is less than the length of the described first data cabling.
The present invention also provides a kind of low-swing differential signals method of reseptance, be used for receiving circuit, described receiving circuit comprises the first data comparator, clock pulse comparator and first flip-flop, described method comprises: drive the described first data comparator with the data bias current, make the described first data comparator receive described first document signal, and export first according to this and compare document signal to described first flip-flop; Drive described clock pulse comparator with the clock pulse bias current, make described clock pulse comparator receive described time pulse signal, and export first according to this and compare time pulse signal to described first flip-flop; Adjust the one at least of described clock pulse bias current and described data bias current, make described first relatively document signal and the described first comparison time pulse signal are formed the time that is provided with and the retention time that time and retention time are met described first flip-flop be set, make described first flip-flop be able to compare relatively time pulse signal of document signal and described first, the output first output document signal according to described first.
Wherein, described receiving circuit also comprises second flip-flop, in the step of described driving clock pulse comparator, drive described clock pulse comparator with described clock pulse bias current, make described clock pulse comparator receive described time pulse signal, and export respectively according to this described first relatively time pulse signal with second relatively time pulse signal to described first and described second flip-flop; Wherein, described first and described second relatively time pulse signal be that polarity is opposite, described first with one of described second flip-flop be that positive edge triggers, another is negative edge triggering.
Wherein, in the step of adjusting described clock pulse bias current and described data bias current, adjust the one at least of described clock pulse bias current and described data bias current, make described first relatively document signal and the described second comparison time pulse signal are formed the time that is provided with and the retention time that time and retention time are met described second flip-flop be set, make that described second flip-flop is able to compare relatively time pulse signal of document signal and described second, the output second output document signal according to described first.
For above-mentioned purpose of the present invention, feature and advantage can be become apparent, preferred embodiment cited below particularly, and conjunction with figs. are described in detail below:
Description of drawings
Fig. 1 shows traditional low-swing differential signals (reduced swing differentialsignal, receiving circuit RSDS).
Fig. 2 shows traditional receiving circuit under different driving voltage, an example of the graph of a relation of comparison document signal that flip-flop is received and comparison time pulse signal.
Fig. 3 shows the circuit diagram according to the receiving circuit of first embodiment.
Fig. 4 shows the circuit diagram according to the receiving circuit of second embodiment.
Fig. 5 shows the receiving circuit of second embodiment under different driving voltage, and the comparison document signal that flip-flop is received and first is an example of the graph of a relation of time pulse signal relatively.
Fig. 6 shows the example of circuit diagram of comparator of the receiving circuit of second embodiment.
Fig. 7 shows the flow chart according to the method for reseptance of the embodiment of the invention.
Embodiment
First embodiment
Please refer to Fig. 3, it shows the circuit diagram according to the receiving circuit of first embodiment.The receiving circuit 300 of first embodiment is in order to reception input data signal A1, and according to input time pulse signal CK1, output output signal Q1.Wherein input data signal A1 and input time pulse signal CK1 be low-swing differential signals (reduced swing differentialsignal, RSDS).Receiving circuit 300 comprises comparator 311 and 321, repeat circuit 312 and 322, with flip-flop 313.In first embodiment, flip-flop 313 is an example with the D type flip-flop (D-flip flop) that positive edge triggers.
Please refer to Fig. 3, comparator 311 is to drive with bias current B1, receives input data signal A1, and output is compared document signal A2 to repeat circuit 312.Relatively document signal A2 inputs to flip-flop 313 by repeat circuit 312.
The one at least of bias current B1 and B2 is adjusted to and makes the comparison document signal A2 of comparator 311 and 321 outputs and relatively time pulse signal CK2 is formed that the time that is provided with and the retention time that time (setup time) and retention time (hold time) are met flip-flop 313 be set.
Because it is excessive that input time pulse signal CK1 falls behind the phase difference of input data signal A1, so need to adjust relatively time pulse signal CK2 and the phase difference that compares document signal A2.Change the time of delay of comparator output because different bias plasma fails to be convened for lack of a quorum, so can adjust comparison time pulse signal and the phase difference that compares document signal by adjusting the bias current that drives comparator.
Therefore, be with different bias current B1 and B2 at the receiving circuit 300 of first embodiment, drive comparator 311 and 321, wherein B2 is greater than B1.After comparator 321 drove with bigger bias current B2, the past reach of the phase place of the comparison time pulse signal A2 of feasible output improved and compares document signal A2 and the phase difference that compares time pulse signal CK2.So, make that the comparison document signal A2 of output respectively and time pulse signal CK2 relatively are formed the time that is provided with and the retention time that time and retention time are met flip-flop 313 be set, flip-flop 313 is correctly obtained exported document signal Q1.
Because the bias current and the applied driving voltage of receiving circuit of driving comparator are irrelevant, when receiving circuit is applied to different driving voltage, can not influence comparator output relatively document signal and the time of delay of comparing time pulse signal.Thus, relatively document signal and the phase difference of comparison time pulse signal are met the time that is provided with and the retention time of corresponding flip-flop.Therefore, the receiving circuit of first embodiment can directly apply to different driving voltage.
Second embodiment
Fig. 4 shows the circuit diagram of the receiving circuit of second embodiment.The receiving circuit 400 of second embodiment is in order to reception input data signal M1 and N1, and according to input time pulse signal K1, obtains output document signal VP1 to VP4 by input data signal M1 and N1.Wherein, input data signal M1, N1 and input time pulse signal K1 are low-swing differential signals.Receiving circuit 400 comprises data comparator 411 and 421, clock pulse comparator 431, repeat circuit 410,420 and 430, buffer 413,414,423,424,433 and 443, flip-flop 415,416,417,425,426 and 427.Wherein, flip-flop 415,417,425 and 427 is that the D type flip-flop that triggers with positive edge is an example.Flip- flop 416 and 426 is that the D type flip-flop that triggers with negative edge is an example.
Because it is excessive that input time pulse signal K1 falls behind the phase difference of input data signal M1, N1, therefore adjust the time of delay of the output of comparator 411,421 and 431 with bias current BA1, BA2 and BA3, make comparison document signal M2, N2 that comparator 411,421 and 431 is exported and the phase difference of the first comparison time pulse signal K2, the second comparison time pulse signal K3 be met the time that is provided with and the retention time of pairing flip-flop.
For comparing document signal M2, by adjusting the one at least of bias current BA1 and BA3, adjust the time of delay of the output of comparator 411 and 431, making relatively that document signal M2 and the first comparison time pulse signal K2 are formed is provided with time and retention time, is met the time that is provided with and the retention time of flip-flop 415; And relatively document signal M2 and the second comparison time pulse signal K3 are formed time and retention time be set, met the time that is provided with and the retention time of flip-flop 416.
For example, if the time that is provided with of the employed flip-flop of receiving circuit equated with the retention time, then can adjust bias current BA3, make relatively document signal M2 respectively with first relatively time pulse signal K2, second relatively time pulse signal K3 is formed the time is set equates preferably with the retention time.
Similarly, for comparing document signal N2, adjust the time of delay of the output of comparator 421 and 431 by bias current BA2 and BA3, making relatively that document signal N2 and the first comparison time pulse signal K2 are formed is provided with time and retention time, is met the time that is provided with and the retention time of flip-flop 425; And relatively document signal N2 and the second comparison time pulse signal K3 are formed time and retention time be set, met the time that is provided with and the retention time of flip-flop 426.
From the above, by adjusting the bias current that drives comparator, change the time of delay of the output of comparator, can significantly improve relatively phase difference of time pulse signal of comparison document signal that comparator exports and first, second, to meet the time that is provided with and the retention time of the pairing flip-flop of comparison document signal.
Detailed circuit in this explanation repeat circuit 410,420,430 and 440.Repeat circuit 410 comprises cabling 412, buffer 413 and 414.Relatively document signal M2 is sent to flip- flop 415 and 416 respectively through cabling 412, buffer 413 and 414.
In Fig. 4, cabling 412 is adjusted into equal in length with cabling 422.In addition, the quantity of the buffer that is connected also equates, in a second embodiment, is that to be connected two buffers respectively with cabling 412 and 422 be example.
When the distance of comparator 411 with flip-flop 415,416, be longer than the distance of comparator 421 and flip-flop 425,426, expression relatively document signal M2 is sent to time of flip- flop 415 and 416 by comparator 411, and it is long by the time that comparator 421 is sent to flip- flop 425 and 426 to compare document signal N2.Therefore, cabling 422 is extended to the equal in length of its length and cabling 412.Otherwise, then cabling 412 is extended to the equal in length of its length and cabling 422.
And, therefore, can suitably adjust the length of cabling 412,422 and 432,442 because the phase place of input time pulse signal K1 lags behind the phase place of input data signal M1, N1.Adjust first relatively time pulse signal K2 with second relatively time pulse signal K3 the cabling 432 and 442 length of process, making its length than cabling 412,422 is weak point.In addition, also can suitably adjust the quantity of cabling 433 and 443 buffers that are connected.In a second embodiment, be that to be connected a buffer respectively with cabling 433 and 443 be example.
From the above, by the quantity of adjustment track lengths with the buffer that is coupled, also can improve first relatively the time pulse signal K2 and second relatively the time pulse signal K3 and the phase difference of document signal M2, N2 relatively better, make relatively document signal M2, N2 and first compare the time that is provided with and retention time that time pulse signal K2, second phase difference that compares time pulse signal K3 are met pairing flip-flop.
At this effect of second embodiment is described.In a second embodiment, by adjusting the bias current that drives comparator, adjust comparison document signal and first and compare the relatively phase difference of time pulse signal of time pulse signal, second, to meet the time that is provided with and the retention time of corresponding flip-flop, make flip-flop correctly be obtained the output document signal.Because bias current is not subjected to the influence of driving voltage, therefore, when receiving circuit is applied to different driving voltage, can not change bias current.So feasible relatively document signal and first compares time pulse signal, second, and relatively the phase difference of time pulse signal can be along with driving voltage changes and changes.
In addition, document signal and first compares the relatively phase difference of time pulse signal of time pulse signal, second owing to adjusted relatively in comparator, and therefore, the repeat circuit between comparator and flip-flop need not use too much buffer.Because it is bigger that influenced by driving voltage the time of delay of the output of buffer, therefore, the traditional receiving circuit 100 in Fig. 1 uses too much buffer, and the receiving circuit 200 of second embodiment more is not subjected to the influence of driving voltage.
Fig. 5 shows receiving circuit 400 after adjusting bias current BA1 and BA3, under different driving voltage, behind cabling 412, buffer 413 and 414, flip-flop 415 received comparison document signal M2 and first compare an example of the graph of a relation of time pulse signal K2.The retention time of flip-flop 415 and the time that is provided with are for example for equating.
Please refer to Fig. 5.Curve 501 is for comparing the waveform of time pulse signal.Curve 502 and 503 is respectively that receiving circuit 400 is under 3.3 volts at driving voltage, and relatively document signal M2 is at retention time situation (hold time condition) and the waveform that time situation (setup timecondition) is set.
When time T f ', the time pulse signal of curve 501 forms negative edge.If triggering with negative edge is example, formed that time (setup time) ts1 ', ts2 ', ts3 ' are set is all identical with respect to waveform 501 with 507 for curve 503,505, and curve 502,504 with 506 with respect to the 501 formed retention times of waveform (setup time) th1 ', th2 ', th3 ' all identical, meet flip-flop 415 for the requirement that time and retention time are set.
As shown in Figure 5, as the bias current BA1 and the BA3 that adjust comparator 411 and 431, making relatively that document signal M2 and time pulse signal K2 relatively are formed is provided with after time and retention time meet the time that is provided with and retention time of flip-flop 415, different driving voltage can't change the time of delay of comparison document signal M2, and the relatively phase difference change of time pulse signal K2 of feasible relatively document signal M2 and first.
Above-mentioned is that down relatively document signal M2 and time pulse signal K2 relatively are formed is set and the retention time is an example time with different driving voltage, illustrates that the receiving circuit 400 of second embodiment is not influenced by driving voltage.Similarly, after adjusting comparator 421 and 431 bias current BA2 and BA3, even under different driving voltage, relatively document signal N2 and comparison time pulse signal K2 are formed is provided with time and retention time, not influenced by driving voltage.
In addition, in a second embodiment, though the distance of comparator 411 and flip-flop 415,416 is not equal to the distance of comparator 421 and flip-flop 425,426.But by being identical with 422 length adjustment, make that relatively document signal M2 is equal with the time of delay that N2 is sent to corresponding flip-flop, reach the synchronous effect of comparison document signal M2 and N2 cabling 412.
In addition, in a second embodiment, comparator 431 is that output phase identical, opposite polarity first compares relatively time pulse signal K3 of time pulse signal K2 and second.Therefore, before second flip- flop 416 and 426 that relatively the negative edge of time pulse signal K3 output triggers, need pass through inverter, so can not make second to compare time pulse signal K3 and postpone.And traditional receiving circuit 100 of Fig. 1, before relatively time pulse signal inputed to the flip-flop of negative edge triggering, it was anti-phase to need will to compare time pulse signal through inverter earlier, and caused time delay.Therefore, in comparison, the received time pulse signal of all flip-flops of the receiving circuit of second embodiment is synchronously.
Fig. 6 shows the example of circuit diagram of the comparator 431 of receiving circuit 400.Comparator receives input time pulse signal K1 with positive input terminal INP and negative input end INN, and compares relatively time pulse signal K3 of time pulse signal K2 and second by positive output end OUP and negative output terminal OUN output first respectively.
In a second embodiment, receiving circuit 400 is to be example to receive two input data signal M1 and N1, and in the practical application, receiving circuit can receive the low-swing differential document signal of greater number.
Fig. 7 shows the flow chart according to the method for reseptance of the embodiment of the invention, is used for the receiving circuit 300 of the embodiment of the invention.At first, in step 710, drive data comparator 311, make data comparator 311 receive document signal A1, and output is according to this compared document signal A2 to flip-flop 313 with data bias current B1.In step 720, drive clock pulse comparator 321 with clock pulse bias current B2, make clock pulse comparator 321 receive time pulse signal CK1, and output is according to this compared time pulse signal CK2 to flip-flop 313.In step 730, the one at least of adjustment data bias current B1 and clock pulse bias current B2, making that document signal A2 relatively and time pulse signal CK2 relatively are formed is provided with the time that is provided with and the retention time that time and retention time are met flip-flop 313, flip-flop 313 is able to according to relatively document signal A2 and relatively time pulse signal CK2, output output document signal Q1.
Because the input data signal is excessive with the phase difference of input time pulse signal, therefore, the receiving circuit of the first embodiment of the present invention and second embodiment, by adjusting the bias current that drives comparator, make comparator comparison document signal of exporting and the phase difference that compares time pulse signal be met the time that is provided with and the retention time of corresponding flip-flop.And be applied under the different driving voltage when receiving circuit, bias current can't change and change along with driving voltage, makes change time of delay of output of comparator.Therefore, the comparison document signal exported of comparator the and relatively phase difference between time pulse signal can be along with driving voltage changes and change.So receiving circuit of the present invention is applicable to different driving voltage.
In addition, the comparator output phase is identical, and opposite polarity two compare time pulse signal to positive edge triggers and the flip-flop of bearing the edge triggering.With traditional receiving circuit in comparison, do not need before time pulse signal relatively is sent to the flip-flop that negative edge triggers, inverter to be set, and cause positive edge to trigger with to bear the comparison time pulse signal that flip-flop received that edge triggers asynchronous.Therefore, receiving circuit of the present invention compared to traditional receiving circuit, more can correctly be obtained the output document signal according to comparing time pulse signal.
In sum, though the present invention discloses as above with preferred embodiment, so it is not in order to limit the present invention.The ordinary technical staff in the technical field of the invention, without departing from the spirit and scope of the present invention, when being used for a variety of modifications and variations.Therefore, protection scope of the present invention is as the criterion when looking the claims person of defining.
The main element symbol description
111,121,131,311,321,411,421,431: comparator
112,122,132,412,422,432,442: cabling
113～116,123～127,133,413,414,423,424,433,443: buffer
312,322: repeat circuit
117,118,119,128,129,130,313,411,421,431: flip-flop
Claims (10)
1. receiving circuit in order to receiving first document signal and time pulse signal, and is exported the first output document signal according to this to the data driver, and described first document signal and described time pulse signal are low-swing differential signals, and described receiving circuit comprises:
The first data comparator drives it with the data bias current, in order to receive described first document signal, exports first according to this and compares document signal;
The first data repeat circuit compares document signal in order to receive described first; The clock pulse comparator drives it with the clock pulse bias current, in order to receiving described time pulse signal, and exports first time pulse signal relatively according to this;
The first clock pulse repeat circuit compares time pulse signal in order to receive described first; And
First flip-flop transmits and described first document signal relatively that comes in order to receive by the described first data repeat circuit, first time pulse signal relatively that comes with transmitting by the described first clock pulse repeat circuit, and export the described first output document signal according to this;
Wherein, the one at least of described clock pulse bias current and described data bias current is adjusted to and makes described first relatively document signal and the described first comparison time pulse signal are formed the time that is provided with and the retention time that time and retention time are met described first flip-flop be set.
2. receiving circuit according to claim 1, wherein, described receiving circuit is also in order to export the second output document signal, described clock pulse comparator also compares time pulse signal according to described time pulse signal output second, described first relatively time pulse signal relatively the polarity of time pulse signal is opposite with described second, and described first relatively time pulse signal and described second relatively time pulse signal is synchronous;
Wherein, described receiving circuit also comprises:
The second clock pulse repeat circuit compares time pulse signal in order to receive described second; And
Second flip-flop transmits and described first document signal relatively that comes in order to receive by the described first data repeat circuit, described second time pulse signal relatively that comes with transmitting by the described second clock pulse repeat circuit, and export the described second output document signal according to this;
Wherein, described first flip-flop and described second flip-flop are respectively positive edge and trigger and bear the edge triggering;
Wherein, the one at least of described clock pulse bias current and described data bias current is adjusted to and makes described first relatively document signal and the described second comparison time pulse signal are formed the time that is provided with and the retention time that time and retention time are met described second flip-flop be set.
3. receiving circuit according to claim 2, wherein, described receiving circuit also comprises the 3rd flip-flop, transmit and the next described second output document signal in order to receive described second flip-flop, the first comparison time pulse signal with transmitting by the described first clock pulse repeat circuit, and export the 3rd output document signal according to this, wherein, described the 3rd flip-flop is that positive edge triggers.
4. receiving circuit according to claim 2, wherein, the described first clock pulse repeat circuit also comprises:
The first clock pulse cabling receives the described first comparison time pulse signal by described clock pulse comparator transmission;
At least one first buffer compares time pulse signal in order to receive and to cushion described first, and the described first comparison time pulse signal is sent to described first flip-flop.
5. receiving circuit according to claim 4, wherein, the described second clock pulse repeat circuit also comprises:
The second clock pulse cabling receives the described second comparison time pulse signal by described clock pulse comparator transmission;
At least one second buffer compares time pulse signal in order to receive and to cushion described second, and the described second comparison time pulse signal is sent to described second flip-flop.
6. receiving circuit according to claim 5, wherein, the equal in length of described first clock pulse cabling and the described second clock pulse cabling.
7. receiving circuit according to claim 2, wherein, the described first data repeat circuit also comprises:
The first data cabling receives by the described first data comparator and transmits and next described relatively document signal;
At least one buffer in order to receiving and to cushion described relatively document signal, and is sent to described first flip-flop with described relatively document signal.
8. receiving circuit according to claim 7, wherein, described receiving circuit also comprises:
The second data comparator receives second document signal, and output second is document signal relatively;
The second data repeat circuit compares document signal in order to receive described second;
The 4th flip-flop transmits and described second document signal relatively that comes in order to receive by the described second data repeat circuit, first time pulse signal relatively that comes with transmitting by the described first clock pulse repeat circuit, and export the 4th output document signal according to this.
9. receiving circuit according to claim 8, wherein, the described second data repeat circuit also comprises:
The second data cabling receives the described second comparison document signal by described second data comparator transmission; And
At least one second buffer receives and cushions the described second comparison document signal, and the described second comparison document signal is sent to described the 4th flip-flop;
Wherein, the equal in length walked of the length of the described first data cabling and described second data.
10. a low-swing differential signals method of reseptance is used for receiving circuit, and described receiving circuit comprises the first data comparator, clock pulse comparator and first flip-flop, and described method comprises:
Drive the described first data comparator with the data bias current, make the described first data comparator receive described first document signal, and export first according to this and compare document signal to described first flip-flop;
Drive described clock pulse comparator with the clock pulse bias current, make described clock pulse comparator receive described time pulse signal, and export first according to this and compare time pulse signal to described first flip-flop;
Adjust the one at least of described clock pulse bias current and described data bias current, make described first relatively document signal and the described first comparison time pulse signal are formed the time that is provided with and the retention time that time and retention time are met described first flip-flop be set, make described first flip-flop be able to compare relatively time pulse signal of document signal and described first, the output first output document signal according to described first.
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| CN2007100979924A CN101295991B (en) | 2007-04-25 | 2007-04-25 | Receiving circuit and signal receiving method |
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| CN2007100979924A CN101295991B (en) | 2007-04-25 | 2007-04-25 | Receiving circuit and signal receiving method |
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| CN101295991B CN101295991B (en) | 2011-08-17 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105099410A (en) * | 2014-05-16 | 2015-11-25 | 瑞昱半导体股份有限公司 | Clock data recovery circuit and method, and equalized signal analysis circuit and method |
| CN113936620A (en) * | 2021-12-15 | 2022-01-14 | 常州欣盛半导体技术股份有限公司 | Source driver and control method of input stage comparator thereof |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001053598A (en) * | 1999-08-16 | 2001-02-23 | Nec Corp | Interface circuit, electronic equipment provided with the interface circuit and communication system |
| CN100338567C (en) * | 2004-05-10 | 2007-09-19 | 联咏科技股份有限公司 | Method for data transmission interface |
| JP4682567B2 (en) * | 2004-09-13 | 2011-05-11 | パナソニック株式会社 | Display element driving device and image display device |
-
2007
- 2007-04-25 CN CN2007100979924A patent/CN101295991B/en active Active
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105099410A (en) * | 2014-05-16 | 2015-11-25 | 瑞昱半导体股份有限公司 | Clock data recovery circuit and method, and equalized signal analysis circuit and method |
| CN105099410B (en) * | 2014-05-16 | 2018-08-28 | 瑞昱半导体股份有限公司 | Clock pulse data reflex circuit and method and grade signal analysis circuit and method |
| CN113936620A (en) * | 2021-12-15 | 2022-01-14 | 常州欣盛半导体技术股份有限公司 | Source driver and control method of input stage comparator thereof |
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| CN101295991B (en) | 2011-08-17 |
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Effective date of registration: 20191011 Address after: Room 1501, No. 1168, South Renmin Road, Kunshan Development Zone, Jiangsu Province Patentee after: Kunshan ruichuangsin Electronics Co., Ltd. Address before: Taipei City, Taiwan, China Patentee before: Ruiding Technology Co., Ltd. |