CN101295645A - Metal-oxide-semiconductor transistor with Y type metal grid and technique thereof - Google Patents
Metal-oxide-semiconductor transistor with Y type metal grid and technique thereof Download PDFInfo
- Publication number
- CN101295645A CN101295645A CNA2007101021325A CN200710102132A CN101295645A CN 101295645 A CN101295645 A CN 101295645A CN A2007101021325 A CNA2007101021325 A CN A2007101021325A CN 200710102132 A CN200710102132 A CN 200710102132A CN 101295645 A CN101295645 A CN 101295645A
- Authority
- CN
- China
- Prior art keywords
- layer
- groove
- sloping edge
- insulating barrier
- oxide semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Landscapes
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention discloses a method for manufacturing an MOS transistor with a metal grid, which comprises the following steps of: providing a floor; a grid sacrificial layer is arranged over the floor; a clearance wall circles the grid sacrificial layer; the floors in the two opposite sides of the grid sacrificial layer are respectively provided with a doping area; an incline edge is formed on the clearance wall and a groove is formed in the clearance wall; an obstructing layer and a metal grid are formed in the grove and the incline edge and the problem of bad step coverage of the obstructing layer can not happen. The invention also discloses an MOS transistor with a Y type metal grid.
Description
Technical field
The present invention relates to the method that a kind of making has the metal oxide semiconductor transistor of metal gates, refer to a kind of method of producing metal oxide semiconductor transistor especially with Y type metal gates.
Background technology
Along with semiconductor technology is constantly progressive, industry can produce the semiconductor device of 45 nanometers (nm) at present.And (the Metal-Oxide-Semiconductor Field-Effect Transistors of metal oxide semiconductcor field effect transistor now; MOSFET) majority is to utilize polysilicon (Poly-silicon) material to make grid (Gate).But existing doped polycrystalline silicon materials remain depletion effect (Depletion Effect) at polysilicon gate and boron penetration (Boron Penetration) to problems such as channel regions as the method for grid structure.
Depletion effect with polysilicon gate is an example, and polysilicon gate can produce the phenomenon that charge carrier (Carrier) exhausts in the zone of polysilicon adjacent gate dielectric medium (Gate Dielectric) in the counter-rotating stage (Inversion).If the depletion effect of this polysilicon gate generation polysilicon gate, then its effective grid capacitance (EffectGate Capacitance) can reduce.But the metal oxide semiconductor transistor of good electron product but should have the grid capacitance of high unit.Because, when grid capacitance was high more, many more electric charges can be accumulated in the grid capacitance both sides, so more electric charge accumulation just can be arranged in the raceway groove, so when metal oxide semiconductor transistor was electrically connected to bias voltage, the electric current turnover rate between the source/drain (Source/Drain) can be better.
Please refer to Fig. 1 (a), Fig. 1 (a) is the schematic diagram of known metal oxides semiconductor transistor.In Fig. 1, have grid structure 12 above the substrate 10, have gate dielectric 15 between grid structure 12 and the substrate 10, and in the grid structure 12 corresponding substrate on two sides 10, have source/drain 14, and grid structure 12 is on every side around clearance wall 16.Wherein, grid structure 12 constitutes metal oxide semiconductor transistor 18 with source/drain 14, and grid structure 12 is made by polysilicon.When the depletion effect of polysilicon gate took place metal oxide semiconductor transistor 18, charged charge carrier can be accumulated between grid structure 12 and the gate dielectric 15, made the thickness of equivalent gate dielectric layer increase.Therefore, the grid capacitance value can with decline, and then reduce the total value of grid capacitance, and cause the decline of metal oxide semiconductor transistor driving force.
For avoiding the depletion effect of above-mentioned polysilicon gate, industry utilizes metal gates to replace polysilicon gate more at present, and its related process can utilize " replacing grid (replacement gate) " technology to finish.Just form counterfeit polysilicon gate (dummy poly-silicon gate) earlier, then, remove this counterfeit polysilicon gate again with the formation groove, and in its groove, form metal gates.In addition, often has barrier layer and high dielectric constant material (high-k) dielectric layer between metal gates and the substrate again, to prevent the elasticity of grid structure electric leakage and increase technology.And this structure often is used in 45nm and the following element, exhausts effect to reduce polysilicon, lower heat budget is provided, and then improves element efficiency.
In aforementioned replacement grid technology, must be earlier with barrier layer deposition on groove walls, again metal insert groove in.Yet, because groove can have very big depth/width ratio usually, the barrier layer ladder takes place when making deposit barrier layers easily covers (step coverage) condition of poor.Please refer to Fig. 1 (b) and Fig. 1 (c), Fig. 1 (b) and Fig. 1 (c) are the manufacture method schematic diagram of conventional metals oxide semi conductor transistor.Shown in Fig. 1 (b), remove after the counterfeit polysilicon gate, have groove 22 in the substrate 10, and groove 22 itself has certain degree of depth L and width W.The barrier layer 24 that is deposited in the substrate 10 causes groove 22 openings to dwindle (overhang) phenomenon, and causes the follow-up technology of inserting metal formation metal gates 26 to be easy to generate hole (void) phenomenon, shown in Fig. 1 (c).Metal gates was vulnerable to chemical damage (chemical attack) and influences element characteristic when this made subsequent technique.In view of this, how to produce the metal oxide semiconductor transistor that no ladder covers the barrier layer of bad problem, be important topic of semiconductor industry.
Summary of the invention
The main purpose of the present invention is to be to provide a kind of metal oxide semiconductor transistor of the Y of having type metal gates and technology thereof to address the above problem.
According to claim of the present invention, the invention provides the method that a kind of making has the metal oxide semiconductor transistor of metal gates, comprising provides substrate, and the substrate top has the grid sacrifice layer, clearance wall respectively has doped region around the grid sacrifice layer in the relative substrate on two sides of grid sacrifice layer.Then, above grid sacrifice layer, clearance wall and substrate, form insulating barrier and dielectric layer in regular turn.Afterwards, remove the part dielectric layer to exposing insulating barrier, and remove the insulating barrier and the grid sacrifice layer of grid sacrifice layer top, on remaining clearance wall, to form sloping edge.Clearance wall in form groove thereafter.Form barrier layer on groove inwall, sloping edge and remaining dielectric layer, and form conductive layer in groove, on sloping edge and the remaining dielectric layer, and barrier layer and the conductive layer of removing remaining dielectric layer top, make remaining barrier layer and conductive layer be formed metal gates.
According to claim of the present invention, the invention provides a kind of metal oxide semiconductor transistor of the Y of having type metal gates, comprise substrate, Y type metal gates is positioned at the substrate top, and two doped regions are positioned at the relative substrate on two sides of Y type metal gates.
Because when barrier layer of the present invention was inserted groove, because there is sloping edge at the slot opening place, so relatively prior art is little for effective depth/width, therefore, the bad problem of barrier layer ladder covering in the prior art can not take place in the present invention.Because the present invention does not have the barrier layer ladder to cover bad problem,, produce the good metal oxide semiconductor transistor of quality again with metal gates so metal gates can completely be inserted in the groove.
Description of drawings
Fig. 1 (a) is the schematic diagram of known metal oxides semiconductor transistor.
What Fig. 1 (b) and Fig. 1 (c) illustrated is that the metal oxide semiconductor transistor generation opening that generally has metal gates dwindles the schematic diagram of phenomenon and hole phenomenon.
Fig. 2 to 6 is the replacement grid making method schematic diagram of first embodiment of the invention.
Fig. 7 to 10 is the replacement grid making method schematic diagram of second embodiment of the invention.
Description of reference numerals
10,50,100 substrates, 12,57 grid structures
14,62,112 source/drains, 15,132 gate dielectrics
16,60,110 clearance walls, 18 metal oxide semiconductor transistors
52,102 gate insulators, 84 barrier layers
84 ', 136 ' residue barrier layer, 72,118 grooves
90 residue conductive layers, 92,140 metal gates
54,104 grid sacrifice layers, 56,63,113 metal silicide layers
58,108 lightly doped drains, 64,114 contact etch stop layers
66,116 inner layer dielectric layers, 68,120 sloping edges
82 high dielectric constant material layers 82 ', 134 ' residue high dielectric constant material layer
138 residual metallic material L, the L ' degree of depth
The W width
Embodiment
Please refer to Fig. 2 to 6, Fig. 2 to 6 is the schematic diagram of the replacement grid making method of first embodiment of the invention.As shown in Figure 2, have grid structure 57 in the substrate 50, grid structure 57 includes gate insulator 52, grid sacrifice layer 54 and grid cover layer (cap layer) 56.Wherein, substrate 50 can be by silicon base, (Silicon-on-Insulator SOI) waits semi-conducting material to constitute to contain silicon base or silicon-on-insulator.Gate insulator 52 can be then that oxide layer (oxide), nitrogen oxide (Oxy-Nitride) layer etc. has the dielectric medium of oxygen atom or nitrogen-atoms and the dielectric material of oxygen atom and nitrogen-atoms composition constitutes.In addition, in first embodiment, grid sacrifice layer 54 utilizes the polysilicon material to constitute, and 56 of grid cover layers can include oxide skin(coating), oxynitride layer or nitride layer.
In grid structure 57 substrate on two sides 50, form lightly doped drain (Lightly Doped Drain, LDD also can be described as the light dope source electrode) 58 and source/drain 62.In addition, visual again arts demand in the surface of source/drain 62 and element characteristic etc. are considered, and form metal silicide (silicide) layer 63.Moreover, then center on the clearance wall (spacer) 60 that forms with silicon nitride, silica or nitrogenize silicon/oxidative silicon composite around the grid structure 57.And the insulation material contact etch stop layer (Contact etch stop layer CESL) 64 covers grid structure 57, clearance wall 60 and substrate 50 tops.Wherein, form the purpose of contact etch stop layer 64, except making follow-up contact hole etching etching end point can be arranged as the etching stopping layer usefulness, it can produce the function of compression or tensile stress in addition, make the channel region of 62 of grid structure 57 belows and source/drains form strain structure, to promote the charge mobility or the hole mobility of raceway groove.Moreover, above contact etch stop layer 64, have inner layer dielectric layer (Inter-Level Dielectric, ILD) 66 again.Wherein, contact etch stop layer 64 can be silicon nitride layer or comprises the insulating barriers such as silicon nitride layer of carbon, fluorine, and inner layer dielectric layer 66 then can be made of oxide or the materials such as silica that are mixed with boron, phosphorus.
Please refer to Fig. 3, subsequently, (chemical mechanical polishing, flatening process CMP) and etch process expose grid sacrifice layer 54 to the open air to utilize chemico-mechanical polishing.For example, carry out CMP (Chemical Mechanical Polishing) process earlier,, just grind inner layer dielectric layer 66 to contact etch stop layer 64 with the grinding stop layer of contact etch stop layer 64 as CMP (Chemical Mechanical Polishing) process.Perhaps, this stage also can be ground earlier by CMP technology and be removed a part of inner layer dielectric layer 66, and reserve part is positioned at the inner layer dielectric layer 66 on the contact etch stop layer 64.Then, carry out etch process, remove and to be positioned at the contact etch stop layer 64 of grid sacrifice layer 54 tops, and make and form sloping edge 68 on remaining inner layer dielectric layer 66, contact etch stop layer 64 and the clearance wall 60.In the present embodiment, sloping edge 68 mainly be positioned at clearance wall 60 around the grid sacrifice layer 54, contact etch stop layer 64, with inner layer dielectric layer 66 on.Yet the size of sloping edge 68, position and angle of inclination need not be confined to this.In other embodiments of the invention, sloping edge 68 also can only be positioned on grid sacrifice layer 54 clearance wall 60 and contact etch stop layer 64 on every side, and does not cover inner layer dielectric layer 66.
In the above-described embodiment, the etch process that forms sloping edge 68 can utilize wet etching or dry etching to finish.With the wet etching is example, can utilize the wet etching solution that silicon nitride and oxide layer is had height etching selectivity (selectivity), phosphoric acid class solution for example, and it is the contact etch stop layer 64 of material that etching is removed with the silicon nitride.Because wet etching is a kind of isotropic etching (isotropicetching), so wet etching not only can vertically carry out etching, and has horizontal etch effect.Moreover, because the contact etch stop layer 64 of the purer silicon nitride material of the etched speed of part of inner layer dielectric layer 66 is slow, so the contact etch stop layer 64 of the purer silicon nitride material of contact etch stop layer 64 etched thickness of close inner layer dielectric layer 66 is few, so can form sloping edge 68 by nature.
Or with the etch process of dry etching as formation sloping edge 68, can utilize silicon nitride and oxide layer are had the highly dry etching gas of etching selectivity, for example chlorine, perfluoroethane and hydrogen bromide mist, carry out etching at contact etch stop layer 64 and part inner layer dielectric layer 66, to etch sloping edge 68.In addition, no matter be to utilize dry etching or wet etching to form sloping edge, all can adjust etching composition to remove grid cover layer 56.
Treat that sloping edge 68 finishes and remove after the grid cover layer 56, please refer to Fig. 4, utilize etch process to remove grid sacrifice layer 54 and gate insulator 52, to form groove 72.Wherein, be the vertical sidewall (vertical sidewall) of clearance wall 60 around the groove 72, the bottom then has substrate 50.Etching is removed the etch process of grid sacrifice layer 54 and also can be selected with wet etching or dry etching.If with the grid sacrifice layer 54 of wet etching removal polysilicon material, then can select to use the chemical etching liquor of nitric acid/hydrogen fluoride composition as etching solution.If remove, then can utilize chlorine or hydrogen bromide to be main gas, to remove grid sacrifice layer 54 with dry etching.Be not limited in polysilicon at this material that note that grid sacrifice layer 54, so long as compare all optional material of the material with suitable etching selectivity as grid sacrifice layer 54 with gate insulator 52.
Etching is removed the etch process of gate insulator 52 and also can be selected with wet etching or dry etching, as if the gate insulator 52 of removing the polysilicon material with wet etching, then can select to use the chemical etching liquor of hydrogen fluoride composition as etching solution.If remove, then can use ion bombardment (ion bombardment) mode of inert gas such as argon gas, to remove gate insulator 52 with dry etching.Removal opportunity can be at the preposition cleaning procedure of removing before grid sacrifice layer 54 backs or subsequent gate dielectric layer form.
Please refer to Fig. 5, then, utilize chemical gaseous phase depositing process or other deposition processs, form high-k (High K) material layer 82 in these groove 72 inwalls, and on the sloping edge 68, residue inner layer dielectric layer 66.Generally as the material of high dielectric constant material layer 82 include elements such as high temperature transition metal, precious metal, rare earth metal with and aluminide, silicide such as the nitrogen-oxygen-silicon hafnium (HfSiON) of aluminide, silicide or nitrogenous oxygen, gadolinium oxide (Gd2O3), dysprosia (Dy2O3) etc.And generally before forming high dielectric constant material layer 82, can earlier form individual interface layer (not shown)s 50 of high dielectric constant material layer 82 and substrates, this interface layer (not shown) comprises the silicon oxide layer, silicon oxynitride layer or the silicon nitride layer that are formed by heating or chemical bonded refractory.And finish after the deposition of high dielectric constant material layer 82, form barrier layer (barrier layer) 84 on high dielectric constant material layer 82 surface again, its formation method includes atomic layer deposition method (ALD), chemical vapour deposition technique (Chemical Vapor Deposition, CVD) or physical vaporous deposition (Physical vapor deposition, PVD), and its material includes the high temperature transition metal, precious metal, elements such as rare earth metal with and carbide, nitride, silicide, aln precipitation or nitrogen silicide, titanium nitride (titanium nitride for example, TiN), tantalum nitride (tantalumnitride, TaN), ramet (tantalum carbide, TaC), the nitrogen tantalum silicide (tantalum silica-nitride, TaSiN), aluminium molybdenum nitride materials such as (MoAlN).Part barrier layer 84 can be with work function regulatory function such as TaC etc.In first embodiment, above part has work function regulatory function barrier layer 84, can not form work function (work function) again again and adjust layer, its material can be ruthenium (ruthenium, Ru) material of element such as containing metal such as grade.
Because groove 72 tops in the first embodiment of the present invention have sloping edge 68, so the opening of the first embodiment further groove 72 is bigger, make the effective depth L ' of groove 72 and the ratio of width W (L '/W) descend, when so high dielectric constant material layer 82 and barrier layer 84 are inserted, ladder can not take place cover condition of poor, and can avoid the opening generation of groove 72 to dwindle phenomenon.
Afterwards, please refer to Fig. 6, after barrier layer 84 is finished, form the conductive layer (not shown) on inner layer dielectric layer 66 and fill up groove 72 and sloping edge 68.Wherein, conductive layer can utilize tungsten (W), titanium nitride (TiN), tungsten titanium metal materials such as (TiN) or mixture to constitute.Then conductive layer (not shown), barrier layer 84 are carried out smooth technology with high dielectric constant material layer 82, utilize CMP (Chemical Mechanical Polishing) process to expose remaining inner layer dielectric layer 66.And the residue high dielectric constant material layer 82 ', the residue barrier layer 84 ' that are positioned at groove 72 and sloping edge 68 at last are metal gates 92 with residue conductive layer 90.Because among first embodiment, metal gates 92 fills up groove 72 and sloping edge 68, so the cross-section structure of metal gates 92 can roughly have y-type structure.And metal gates 92 and source/drain 62 promptly constitute the metal oxide semiconductor transistor of first embodiment.Afterwards, the dielectric layer that can continue, and form required metal interconnecting in regular turn, to finish the making of semiconductor element.
In addition, in the change type of first embodiment, when the inner layer dielectric layer among Fig. 2 66 is removed to when exposing contact etch stop layer 64, also can utilize ion bombardment (ion bombardment) technology to remove the contact etch stop layer 64 of grid sacrifice layer 54 tops, and then make and form sloping edge 68 on remaining inner layer dielectric layer 66, contact etch stop layer 64 and the grid sacrifice layer 54.And in the process of carrying out ion bombardment technology, also can in same equipment, carry out dry method etch technology simultaneously, with removal grid cover layer 56, and the composition removal grid sacrifice layer 54 of adjustment dry etching, and then form groove 72.In other words, first embodiment can carry out ion(ic) etching, dry method etch technology simultaneously in same equipment, and forms sloping edge 68 and groove 72 respectively.Afterwards, only need form high dielectric constant material layer, barrier layer in regular turn, and get final product as the description making metal gates of first embodiment, its detailed process is not given unnecessary details separately at this.
Please refer to Fig. 7 to 10, Fig. 7 to 10 is the replacement grid making method schematic diagram of second embodiment of the invention.As shown in Figure 7, have gate insulator 102, grid sacrifice layer 104 and grid cover layer (not shown) in the substrate 100.Wherein, substrate 100 can be made of silicon base or semi-conducting material such as silicon-coated insulated.Gate insulator 102 can be then that oxide layer, oxynitride layer etc. have the dielectric medium of oxygen atom or nitrogen-atoms and the dielectric material of oxygen atom and nitrogen-atoms composition constitutes.In addition, in a second embodiment, grid sacrifice layer 104 utilizes the polysilicon material to constitute.
In gate insulator 102 and grid sacrifice layer 104 substrate on two sides 100, have lightly doped drain 108 and source/drain 112, in addition, have metal silicide layer 113 on the source/drain 112 again.Moreover then centering on the silicon nitride around gate insulator 102 and the grid sacrifice layer 104 is the clearance wall 110 of material.
Then, deposition contact etch stop layer 114 covers grid sacrifice layer 104, clearance wall 110 and substrate 100 tops.In addition, deposit inner layer dielectric layer 116 again above contact etch stop layer 114.Wherein, contact etch stop layer 114 is for the silicon nitride layer of insulation material or comprise the silicon nitride layer of carbon, fluorine, and inner layer dielectric layer 116 is made of oxide layer or the silica that is mixed with boron, phosphorus.Afterwards, utilize CMP (Chemical Mechanical Polishing) process and etch process to expose grid sacrifice layer 104 to the open air, for example grind the inner layer dielectric layer 116 of removing part by CMP (Chemical Mechanical Polishing) process earlier.Then, carry out the inner layer dielectric layer 116 of etch-back (etchback) process portion up to exposing contact etch stop layer 114.Afterwards, by adjusting different etching compositions, with the contact etch stop layer 114 of removal grid sacrifice layer 104 tops, and grid cover layer (not shown), up to the grid sacrifice layer 104 that exposes the polysilicon material.
Then, please refer to Fig. 8, grid sacrifice layer 104 and gate insulator 102 are removed in etching, form groove 118.Wherein, groove 118 is centered on by the vertical sidewall of clearance wall 110 to form, and the bottom then is substrate 100.Wherein removing the etch process of grid sacrifice layer 104 also can select with wet etching or dry etching.If with the grid sacrifice layer 104 of wet etching removal polysilicon material, then can select to use the chemical etching liquor of nitric acid/hydrogen fluoride composition as etching solution.If remove, then can utilize chlorine or hydrogen bromide to be main gas, to remove grid sacrifice layer 104 with dry etching.Be not limited in polysilicon at this material that note that grid sacrifice layer 104, so long as compare all optional material of the material with suitable etching selectivity as grid sacrifice layer 104 with gate insulator 102.Etching is removed the etch process of gate insulator 102 and also can be selected with wet etching or dry etching, as if the gate insulator 102 of removing the polysilicon material with wet etching, then can select to use the chemical etching liquor of hydrogen fluoride composition as etching solution.If remove, then can use the ion bombardment mode of inert gas such as argon gas, to remove gate insulator 102 with dry etching.Removal opportunity can be at the preposition cleaning procedure of removing before grid sacrifice layer 104 backs or subsequent gate dielectric layer form.
Please continue with reference to figure 9, carry out ion bombardment technology or etch process, make the clearance wall 110 of groove 118 opening parts and part contact etch stop layer 114 be removed, and then form sloping edge 120 at groove 118 opening parts.Owing to have sloping edge 120 around the groove 118, so can be so that the ratio of the effective depth L ' of groove 120 and width W (L '/W) descend.
Then, please refer to Figure 10, above the substrate 100 of groove 118 bottoms, form gate dielectric 132.Wherein, gate dielectric 132 can comprise heat and chemical mode formation by oxidation technology, promptly oxidation is carried out in the substrate 100 of siliceous composition and is made part of grid pole dielectric layer 132 be formed at groove 118 bottoms.Then, utilize chemical gaseous phase depositing process or other deposition processs, form high dielectric constant material layer (not shown) comprehensively in this groove 118, and on the sloping edge 120, inner layer dielectric layer 116.Finish after the deposition of high dielectric constant material layer (not shown), form the barrier layer (not shown) on high dielectric constant material layer (not shown) surface again.Form conductive layer (not shown) in inner layer dielectric layer 116 on and fill up groove 118 and sloping edge 120 thereafter.Then, utilize CMP (Chemical Mechanical Polishing) process that the conductive layer (not shown) is ground to and expose residue inner layer dielectric layer 116, residue high dielectric constant material layer 134 ' and residue barrier layer 136 '.The residue high dielectric constant material layer 134 ', residue barrier layer 136 ' and the residual metallic material 138 that are positioned at groove 118 and sloping edge 120 at last are metal gates 140.Afterwards, the dielectric layer that can continue again, and form required metal interconnecting in regular turn, to finish the semiconductor element of telotism.
Generally as the material of high dielectric constant material layer (not shown) comprise elements such as high temperature transition metal, precious metal, rare earth metal with and aluminide, silicide such as nitrogen-oxygen-silicon hafnium, gadolinium oxide, the dysprosia of aluminide, silicide or nitrogenous oxygen.Barrier layer formation method includes atomic layer deposition method, chemical vapour deposition technique or physical vaporous deposition, and its material include elements such as high temperature transition metal, precious metal, rare earth metal with and material such as carbide, aluminide, nitride, silicide, aln precipitation or nitrogen silicide such as titanium nitride, tantalum nitride, ramet, aluminium molybdenum nitride, nitrogen tantalum silicide.Part barrier layer (not shown) can be with work function regulatory function such as TaC etc.In a second embodiment, have in part and can not form work function above the work function regulatory function barrier layer (not shown) again again and adjust layer, its material can be the material of containing metal element such as ruthenium.
Advantage as first embodiment of the invention, owing to have sloping edge 120 around the groove 118 in the second embodiment of the present invention, so the effective depth/width of groove 118 than (L '/W) less, therefore, when high dielectric constant material layer (not shown) and barrier layer (not shown) are inserted, ladder can not take place cover condition of poor.Wherein, conductive layer can utilize metal materials such as tungsten, titanium nitride, tungsten titanium to constitute.Because among second embodiment, metal gates 140 fills up groove 118 and sloping edge 120, so metal gates 140 has y-type structure.And the metal oxide semiconductor transistor among second embodiment is made of metal gates 140 and source/drain 112.Since when barrier layer of the present invention is inserted groove, because there is sloping edge at the slot opening place, so effective depth/width (L '/W) little than prior art, therefore, the bad problem of barrier layer ladder covering in the prior art can not take place in the present invention.Again because the present invention does not have the barrier layer ladder to cover bad problem, so metal gates can completely be inserted in the groove, to produce the good metal oxide semiconductor transistor of quality with metal gates.
The above only is the preferred embodiments of the present invention, and all equalizations of doing according to claim of the present invention change and modify, and all should belong to covering scope of the present invention.
Claims (27)
1. a making has the method for the metal oxide semiconductor transistor of metal gates, comprises:
Substrate is provided, and this substrate top has the grid sacrifice layer, and clearance wall respectively has doped region around this grid sacrifice layer in this substrate of these relative both sides of grid sacrifice layer;
Above this grid sacrifice layer, this clearance wall and this substrate, form insulating barrier
Above this insulating barrier, form dielectric layer;
Remove this dielectric layer of part to exposing this insulating barrier;
Remove this insulating barrier and this grid sacrifice layer of this grid sacrifice layer top, above this clearance wall, forming sloping edge, and in this clearance wall, form groove;
Form barrier layer on this groove inwall, this sloping edge and remaining this dielectric layer;
Form conductive layer in this groove, on this sloping edge and remaining this dielectric layer; And
Remove this barrier layer and this conductive layer of remaining this dielectric layer top, to form metal gates.
2. as claim the 1 described method, wherein remove part this dielectric layer to the method that exposes this insulating barrier be selected from CMP (Chemical Mechanical Polishing) process, etch process one of them with and combination.
3. as claim the 1 described method, wherein has etching selectivity between this insulating barrier, this dielectric layer and between this grid sacrifice layer and this clearance wall.
4. as claim the 1 described method, the technology that wherein forms this sloping edge is ion bombardment technology, and the technology that forms this groove is dry method etch technology, and two technologies are carried out simultaneously.
5. as claim the 1 described method, wherein form the technology of this sloping edge and the technology of this groove of formation and in same equipment, carry out.
6. as claim the 1 described method, after wherein this sloping edge is finished, just form this groove.
7. as claim the 6 described methods, the technology that wherein forms this sloping edge be selected from dry method etch technology, wet etching process one of them.
8. as claim the 6 described methods, the technology that wherein forms this groove be selected from dry method etch technology, wet etching process one of them.
9. as claim the 1 described method, after wherein this groove is finished, just form the step of this sloping edge.
10. as claim the 9 described methods, the technology that wherein forms this groove be selected from dry method etch technology, wet etching process one of them.
11. as claim the 9 described methods, the technology that wherein forms this sloping edge is ion bombardment technology.
12. as claim the 1 described method, wherein this insulating barrier comprises silicon nitride layer, this dielectric layer comprises oxide layer, this grid sacrifice layer comprises the polysilicon material and constitutes.
13. as claim the 1 described method, wherein this insulating barrier comprises the silicon nitride layer of carbon, fluorine.
14. as claim the 1 described method, wherein form before this barrier layer, form earlier on this groove inwall of high dielectric constant material layer, this sloping edge and remaining this dielectric layer.
15. as claim the 1 described method, wherein form after this barrier layer, form work function again and adjust layer on this barrier layer.
16. as claim the 1 described method, wherein removing this barrier layer of remaining this dielectric layer top and the method for this conductive layer is CMP (Chemical Mechanical Polishing) process.
17. the metal oxide semiconductor transistor with Y type metal gates comprises:
Substrate;
Y type metal gates is positioned at this substrate top;
Doped region is positioned at this substrate of these relative both sides of Y type metal gates;
Clearance wall, this clearance wall has vertical sidewall, and this vertical sidewall of this clearance wall surrounds into groove, and this Y type metal gates of part is positioned at this groove;
Insulating barrier is positioned at this clearance wall periphery;
Dielectric layer is positioned at this insulating barrier periphery; And
Sloping edge is covered on this clearance wall, and this Y type metal gates of part is positioned on this sloping edge.
18. as claim the 16 described metal oxide semiconductor transistors, wherein this sloping edge is covered on this clearance wall and this insulating barrier.
19. as claim the 16 described metal oxide semiconductor transistors, wherein this sloping edge is covered on this clearance wall, this insulating barrier and this dielectric layer.
20. as claim the 17 described metal oxide semiconductor transistors, wherein this substrate is silicon or silicon-coated insulated material.
21. as claim the 17 described metal oxide semiconductor transistors, this two doped region source/drain that is this metal oxide semiconductor transistor wherein.
22., wherein have etching selectivity between this insulating barrier, this dielectric layer as claim the 17 described metal oxide semiconductor transistors.
23. as claim the 17 described metal oxide semiconductor transistors, wherein this insulating barrier is that silicon nitride layer, this dielectric layer are constituted by oxide layer.
24. as claim the 17 described metal oxide semiconductor transistors, wherein this insulating barrier is the silicon nitride layer that comprises carbon, fluorine.
25., wherein have the high dielectric constant material layer again between this Y type metal gates and this clearance wall and this insulating barrier as claim the 17 described metal oxide semiconductor transistors.
26., wherein have barrier layer again between this Y type metal gates and this high dielectric constant material layer as claim the 25 described metal oxide semiconductor transistors.
27., wherein have work function between this Y type metal gates and this barrier layer again and adjust layer as claim the 26 described metal oxide semiconductor transistors.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200710102132A CN100580892C (en) | 2007-04-29 | 2007-04-29 | Metal-oxide-semiconductor transistor with Y type metal grid and technique thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200710102132A CN100580892C (en) | 2007-04-29 | 2007-04-29 | Metal-oxide-semiconductor transistor with Y type metal grid and technique thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101295645A true CN101295645A (en) | 2008-10-29 |
| CN100580892C CN100580892C (en) | 2010-01-13 |
Family
ID=40065817
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN200710102132A Active CN100580892C (en) | 2007-04-29 | 2007-04-29 | Metal-oxide-semiconductor transistor with Y type metal grid and technique thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN100580892C (en) |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102210035A (en) * | 2008-12-30 | 2011-10-05 | 三星移动显示器株式会社 | Method for encapsulating environmentally sensitive devices |
| CN102779843A (en) * | 2012-07-23 | 2012-11-14 | 上海宏力半导体制造有限公司 | Transistor and forming method thereof |
| CN103681273A (en) * | 2012-09-06 | 2014-03-26 | 中芯国际集成电路制造(上海)有限公司 | Metal gate manufacturing method |
| WO2015021670A1 (en) * | 2013-08-13 | 2015-02-19 | 中国科学院微电子研究所 | Semiconductor device and manufacturing method therefor |
| CN110571144A (en) * | 2019-07-25 | 2019-12-13 | 西安电子科技大学 | manufacturing method of novel semiconductor grid |
| WO2020021400A1 (en) * | 2018-07-24 | 2020-01-30 | International Business Machines Corporation | Oxide resistive random access memory |
| CN111627993A (en) * | 2020-06-05 | 2020-09-04 | 福建省晋华集成电路有限公司 | Grid structure and manufacturing method thereof |
| CN112420821A (en) * | 2020-10-29 | 2021-02-26 | 北京元芯碳基集成电路研究院 | Y-shaped gate structure based on carbon-based material and preparation method thereof |
-
2007
- 2007-04-29 CN CN200710102132A patent/CN100580892C/en active Active
Cited By (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102210035A (en) * | 2008-12-30 | 2011-10-05 | 三星移动显示器株式会社 | Method for encapsulating environmentally sensitive devices |
| CN102779843A (en) * | 2012-07-23 | 2012-11-14 | 上海宏力半导体制造有限公司 | Transistor and forming method thereof |
| CN103681273A (en) * | 2012-09-06 | 2014-03-26 | 中芯国际集成电路制造(上海)有限公司 | Metal gate manufacturing method |
| CN103681273B (en) * | 2012-09-06 | 2018-04-27 | 中芯国际集成电路制造(上海)有限公司 | Metal gates production method |
| WO2015021670A1 (en) * | 2013-08-13 | 2015-02-19 | 中国科学院微电子研究所 | Semiconductor device and manufacturing method therefor |
| US9825135B2 (en) | 2013-08-13 | 2017-11-21 | Institute of Microelectronics, Chinese Academy of Sciences | Semiconductor devices and methods for manufacturing the same |
| US10580977B2 (en) | 2018-07-24 | 2020-03-03 | International Business Machines Corporation | Tightly integrated 1T1R ReRAM for planar technology |
| WO2020021400A1 (en) * | 2018-07-24 | 2020-01-30 | International Business Machines Corporation | Oxide resistive random access memory |
| US11038103B2 (en) | 2018-07-24 | 2021-06-15 | International Business Machines Corporation | Tightly integrated 1T1R ReRAM for planar technology |
| GB2591186A (en) * | 2018-07-24 | 2021-07-21 | Ibm | Oxide resistive random access memory |
| GB2591186B (en) * | 2018-07-24 | 2022-01-05 | Ibm | Oxide resistive random access memory |
| CN110571144A (en) * | 2019-07-25 | 2019-12-13 | 西安电子科技大学 | manufacturing method of novel semiconductor grid |
| CN111627993A (en) * | 2020-06-05 | 2020-09-04 | 福建省晋华集成电路有限公司 | Grid structure and manufacturing method thereof |
| CN111627993B (en) * | 2020-06-05 | 2023-01-06 | 福建省晋华集成电路有限公司 | Grid structure and manufacturing method thereof |
| CN112420821A (en) * | 2020-10-29 | 2021-02-26 | 北京元芯碳基集成电路研究院 | Y-shaped gate structure based on carbon-based material and preparation method thereof |
| CN112420821B (en) * | 2020-10-29 | 2021-11-19 | 北京元芯碳基集成电路研究院 | Y-shaped gate structure based on carbon-based material and preparation method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN100580892C (en) | 2010-01-13 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7745889B2 (en) | Metal oxide semiconductor transistor with Y shape metal gate | |
| US11887891B2 (en) | Self-aligned contacts | |
| US10825915B2 (en) | Spacers for nanowire-based integrated circuit device and method of fabricating same | |
| CN100580892C (en) | Metal-oxide-semiconductor transistor with Y type metal grid and technique thereof | |
| US9455344B2 (en) | Integrated circuit metal gate structure having tapered profile | |
| US7723192B2 (en) | Integrated circuit long and short channel metal gate devices and method of manufacture | |
| US8193641B2 (en) | Recessed workfunction metal in CMOS transistor gates | |
| CN100399580C (en) | Semiconductor element and method for producing the same | |
| CN105428304B (en) | Semiconductor structure and method of forming isolation between fin structures of fin device | |
| US7422936B2 (en) | Facilitating removal of sacrificial layers via implantation to form replacement metal gates | |
| US8735272B2 (en) | Integrated circuit having a replacement gate structure and method for fabricating the same | |
| US7709910B2 (en) | Semiconductor structure for low parasitic gate capacitance | |
| TW201137985A (en) | Multi-gate semiconductor device with self-aligned epitaxial source and drain | |
| US20120319205A1 (en) | High-k metal gate electrode structures formed by reducing a gate fill aspect ratio in replacement gate technology | |
| CN102437118B (en) | Making method of transistor with metal grid | |
| US7326617B2 (en) | Method of fabricating a three-dimensional multi-gate device | |
| KR20080076832A (en) | Method for manufacturing insulated gate field effect transistor | |
| CN102222694A (en) | semiconductor device having a strained channel and method of manufacture thereof | |
| CN101527316A (en) | Semiconductor device and method of manufacturing the same | |
| US10128112B2 (en) | Method of fabricating semiconductor device | |
| US9761691B2 (en) | Integrated circuits including replacement gate structures and methods for fabricating the same | |
| US20220093468A1 (en) | Semiconductor device and forming method thereof | |
| JP2006302959A (en) | Semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |