CN101295537B - Reading operation control method of memory body - Google Patents
Reading operation control method of memory body Download PDFInfo
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- CN101295537B CN101295537B CN2007101017211A CN200710101721A CN101295537B CN 101295537 B CN101295537 B CN 101295537B CN 2007101017211 A CN2007101017211 A CN 2007101017211A CN 200710101721 A CN200710101721 A CN 200710101721A CN 101295537 B CN101295537 B CN 101295537B
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Abstract
The invention relates to a memory reading-operation control method which respectively decodes received reading instructions and address signals into internal address reading signals and internal address signals so as to read data from the data storage part of the memory. Then, the read date is simulated into the time or a transmission path required by a ready state. When the simulated result indicates that the data is ready, the read data is inspected for mistakes, and the time spent on mistake inspection is simulated and when the simulated result indicates that the mistake inspection is completed, and the mistake inspection result is sent out to the external part of the memory.
Description
Technical field
The present invention relates to a kind of memory body read operation control method of (storer, internal memory below all is called memory body for memory, i.e. storage medium), particularly relate to a kind of read operation control method that can increase the memory body of data read accuracy.
Background technology
Dynamic Random Access Memory (Dynamic Random Access Memory; DRAM) have low-cost and jumbo characteristic, therefore many electronic system products all adopt it to be used as the memory body solution, especially one of indispensable spare part of electronic system product.Just use not, DRAM is main application with information products still at present, as desktop PC, mobile computer, dram upgrade module, server and workstation etc.
In communication system or computer system, (cyclic redundancycheck CRC) improves bug check ability to DRAM can to utilize Cyclical Redundancy Check.After data transmission or data storing, CRC can be used for checking whether make a mistake in data transmission procedure.In data transmission procedure, receiving/send out both sides all needs to carry out the CRC computing, by a certain side's comparison CRC result that both sides calculated, can learn whether received data are wrong then.
When desire uses CRC to improve the data read accuracy of memory body, need elder generation's affirmation data to be ready for (ready), just can carry out the CRC computing.If before data are not ready for as yet, just begin these data are carried out the CRC computing, then can obtain wrong CRC operation result.
In addition, in DRAM, some data bus may be shared.When continuous reading of data, if the computing of CRC is not controlled opportunity, data collision takes place easily.When especially CRC operation time was longer, the next record data were delivered to if the CRC computing is not finished as yet, then make a mistake easily.
What is more, if can estimate out finishing opportunity of CRC computing, then can finish and after data bus is sent thus, discharge the right to use of data bus as early as possible in the CRC computing.So, can more accelerate the reading speed of DRAM.
So, the read operation control method of a kind of DRAM better can be arranged, with the shortcoming of improving known techniques and other advantage is provided.
Summary of the invention
The invention provides the read operation control method of a kind of DRAM, it can precisely be simulated/estimate out data (be data, below all be called data) and when be ready for.
The invention provides the read operation control method of a kind of DRAM, it more can precisely be simulated/estimate out the CRC computing and when finish.
The invention provides the read operation control method of a kind of DRAM, it more can avoid the data collision in reading process.
The invention provides the read operation control method of a kind of DRAM, it more can avoid the CRC operation result of output error.
The invention provides the read operation control method of a kind of DRAM, it more can increase reading speed.
Example of the present invention proposes a kind of memory body method of controlling operation thereof, comprising: the reading command of decoding is that a home address (be address, below all be called the address) reads signal; The Input Address signal of decoding is an internal address signal; Read signal and this internal address signal according to this home address, in this memory body, read data; Postpone by analog data transmissions, whether be ready for to indicate this sense data; Indicate this sense data when this data transfer delay analog result and be ready for, this sense data is carried out bug check, whether correct to check this sense data; Simulate the operation time of this bug check, whether finish to indicate this bug check; And work as this mistake analog result and indicate this bug check to finish, send this error check results to this memory body outside.
In addition, another example of the present invention more provides a kind of memory body method of controlling operation thereof, comprising: the reading command of decoding is that a home address reads signal; The Input Address signal of decoding is an internal address signal; Read signal and this internal address signal according to this home address, the data storing in this memory body is partly read data; This sense data is delivered to a bug check unit in this memory body, whether correct to check this sense data; Simulate the operation time of this bug check unit, whether finish to indicate this bug check; And finish when the simulation of this mistake shows this bug check, send this error check results that this bug check unit produced to this memory body outside.
What is more, another example of the present invention provides a kind of memory body method of controlling operation thereof.This memory body comprises a memory cell array at least, a data working storage and a bug check unit.This method comprises: receive and the reading command of decoding is that a home address reads signal; The reception and the Input Address signal of decoding are an internal address signal; Read signal and this internal address signal according to this home address, from this memory cell array sense data; This sense data is sent to this memory body outside; Simulate these data and read out to the data transfer delay that arrives between this data working storage, be ready for signal to produce data from this memory cell array; Be ready for signal according to these data, this sense data is delivered to this bug check unit from this data working storage; By this bug check unit this sense data is carried out bug check, to produce a bug check sign indicating number; Simulate the bug check operation time of this bug check unit, be ready for signal to export a bug check; And be ready for signal according to this bug check, send this bug check sign indicating number that this bug check unit produced to this memory body outside.
For above-mentioned feature and advantage of the present invention can be become apparent, embodiment cited below particularly, and cooperate appended graphicly, be described in detail below.
Description of drawings
Fig. 1 shows that memory body reads the synoptic diagram of control according to an embodiment of the invention.
Fig. 2 shows the synoptic diagram that reads required time that present embodiment is simulated.
101: memory body storehouse 102: working storage
103: first-in first-out working storage 104: wafer drives calibration circuit outward
105:CRC arithmetic element 106:I/O impact damper
107: demoder 108: read the timing simulation device
109:CRC timing simulation device 110: data bus
111: demoder 112: column decoder
21: memory cell array 22: the secondary induction amplifier
23: data bus
Embodiment
Please refer to Fig. 1, it shows that memory body reads the synoptic diagram of control according to an embodiment of the invention.Memory body storehouse (memory bank) 101 is coupled to working storage 102 and first-in first-out working storage (FIFO) 103 by data bus (be bus-bar, below all be called bus) 110.CRC arithmetic element 105 is coupled to working storage 102 and I/O impact damper 106.Wafer drives calibration circuit outward, and (off-chip driver OCD) 104 is coupled to first-in first-out working storage 103.Demoder 107 is coupled to and reads timing simulation device (read timer) 108.CRC timing simulation device (CRC timer) 109 is coupled to and reads timing simulation device 108 and I/O impact damper 106.Demoder 111 is coupled to column decoder (column decoder) 112.
The data of being read from memory body storehouse 101 can be delivered to working storage 102 and first-in first-out working storage 103 by data bus 110.
First-in first-out working storage 103 also is to be used for temporary institute sense data, and the data of being read to allow can be delivered to the memory body outside.Can adjust its operating voltage through driving calibration circuit 104 outside the wafer from the data that first-in first-out working storage 103 is sent.
In DDR (Double Data Rate) II DRAM, wafer drives calibration circuit outward can do correction at the operating voltage that impact damper (I/O buffer) is gone in the output of DRAM, increases the consistance of operating voltage, to improve signal quality.At DRAM with adjusting its driving voltage position standard apart from length between other element; If circuit is longer, driving voltage that need be higher then, vice versa.The operation of OCD comprises: the resistance of setting the I/O impact damper is adjusted its driving voltage, draws in the compensation/pull down resistor; By data offset (skew) being dropped to the minimum signal integrality of improving; Control overshoot (over-shooting) He Xiachong (under-shooting) improves signal quality; Can revise processing procedure difference between the different DRAM supplier by the voltage calibration of I/O impact damper.Drive calibration circuit 104 calibrations outward through wafer, data just can export the memory chip outside to via the I/O impact damper.
CRC arithmetic element 105 is carried out the CRC computing at the data of being read.CRC arithmetic element 105 may comprise multistage logic lock (such as, exor lock EXOR).Such as, when the data of reading comprised 128 bits, CRC arithmetic element 105 may comprise 7 grades exor lock, but every grade of included exor lock quantity possibility may not be identical.
I/O impact damper 106 receives the CRC operation result of being calculated by CRC arithmetic element 105 and the CRC that is produced by CRC timing simulation device 109 is ready for signal CRC_RDY.CRC is ready for signal CRC_RDY can control whether exportable CRC operation result of I/O impact damper 106.Be ready for signal CRC_RDY when occurring as CRC in the present embodiment, represent CRC arithmetic element 105 should finish the CRC computing and obtain correct CRC operation result.So, I/O impact damper 106 just can be sent the CRC operation result.
Demoder 107 can be decoded into reading command R_CMD inner CAS (column addressstrobe, column address strobe) signal CASi.The going out to represent of inner CAS signal CASi begins the memory cell array is carried out reading of data.Demoder 111 also can be decoded into internal address signal INT_ADD with received address signal ADD.
Reading timing simulation device 108 can produce a data read according to the inside CAS signal CASi that demoder 107 is produced and be ready for signal RCAS.Read timing simulation device 108 be used to simulate from memory chip receive reading command R_CMD to memory chip really with the time required the data output or the signal path of process.By the timing simulation that reads timing simulation device 108, just can guarantee when carrying out the CRC computing, be to carry out the CRC computing, and can not carry out the CRC computing last data at desired data.In addition, read required time really, more can shorten data and read out to the time that begins to carry out between the CRC computing, to increase the memory body operating speed if analog result is extremely approached.Just, guaranteeing that data are under the required situation, allow the CRC computing begin as early as possible, to increase the memory body operating speed.
Reading the object that timing simulation device 108 simulated is at least: (1) memory cell array; (2) secondary induction amplifier; And the data transfer path (that is metal wire) between (3) secondary induction amplifier and the working storage 102.Certainly, reading object that timing simulation device 108 simulates needs visual memory body inside structure and decides, and just illustrates at this.At present embodiment, the embodiment that reads timing simulation device 108 has several.
A kind of framework of may implementing that reads timing simulation device 108 comprises: (1) simple memory cell array mimic channel, the data transfer path in its simulation memory cell array; (2) simple secondary induction amplifier mimic channel, the data transfer path in its simulation secondary induction amplifier; And (3) simulation metal wire, the data transfer path (metal wire) between its simulation secondary induction amplifier and the working storage 102.For making simulation more accurate, for example the length of (3) simulation metal wire equals the metal wire length between secondary induction amplifier and the working storage 102; And the layout fraction of this two metal line can be different.Such as, the layout of the metal wire between secondary induction amplifier and the working storage 102 may be orthoscopic, but the layout of (3) simulation metal wire can be winding type.Certainly, if memory cell array, secondary induction amplifier; And the framework of the metal wire between secondary induction amplifier and the working storage 102/layout change, the framework/layout that then reads timing simulation device 108 also needs to change thereupon.
The electrical specification of the metal wire between memory cell array, secondary induction amplifier and secondary induction amplifier and the working storage 102 may slightly change because of the drift of processing procedure.By this analog form,, then read the result that timing simulation device 108 simulated and also can drift about thereupon if processing procedure drifts about to some extent.That is, if processing procedure drift makes the above-mentioned electrical specification that simulated circuit accelerate (or slack-off), the result that simulated also can accelerate (or slack-off) thereupon.
The another kind that reads timing simulation device 108 may be implemented framework and comprise a plurality of delay cells.The total delay time amount of these delay cells (such as for several clock pulse cycles) can guarantee that data read and be sent to working storage 102 from the memory cell array.But, if clock pulse high frequency more and more notes whether the total delay time amount enough contains the real data read time.Under this framework, data read can be ready for the inhibit signal that signal RCAS is considered as inner CAS signal CASi.
CRC timing simulation device 109 is used to simulate the CRC operation time of CRC arithmetic element 105.CRC timing simulation device 109 can be ready for signal RCAS according to data read and be produced CRC and be ready for signal CRC_RDY.CRC is ready for the CRC arithmetic element 105 that goes out to represent of signal CRC_RDY and has finished the CRC computing.In the present embodiment, the framework of may implementing of CRC timing simulation device 109 also has several.
A kind of framework that may implement framework relevant for CRC arithmetic element 105 of CRC timing simulation device 109.Such as, as above-mentioned, when CRC arithmetic element 105 comprise 7 grades the exor lock time, CRC timing simulation device 109 may comprise the exor lock of 7 serial connections.Thus, the output of CRC arithmetic element 105 is gone into time delay (representing real CRC computing required time) between signal and can be equal to 109 outputs of CRC timing simulation device as far as possible and go into time delay (the CRC operation time that representative is simulated) between signal.
The another kind of CRC timing simulation device 109 may be implemented framework and then comprise a plurality of delay cells.The total delay time amount of these delay cells (such as for several clock pulse cycles) need guarantee that CRC arithmetic element 105 finished the CRC computing.But, if clock pulse high frequency more and more notes whether the total delay time amount enough contains real CRC operation time.Under this framework, CRC can be ready for signal CRC_RDY and be considered as the inhibit signal that data read is ready for signal RCAS.
Column decoder 112 can be decoded into column selection line signal CSL (ColumnSelect Line) with inner CAS signal CASi (being solved by demoder 107) and internal address signal INT_ADD (being solved by demoder 111).Column selection line signal CSL comprises the CSL1～CSLn of n bar, and each delivers to one of memory body storehouse 101 respectively, to represent that memory body storehouse 101 to be opened and to send data.
In addition, can utilize to wait and receive the external read number of winning the confidence (as reading command R_CMD) and external address signal (as address signal ADD) as receiver (receiver).
Please refer to Fig. 2, it shows the synoptic diagram that reads required time that present embodiment is simulated.As shown in Figure 2, memory cell array 21 is coupled to secondary induction amplifier (SSA, Second SenseAmplifier) 22.Secondary induction amplifier 22 is coupled to working storage 102 by data bus 23.Working storage 102 is coupled to CRC arithmetic element 105.
After a certain row of memory cell array 21 were opened, data D delivered to working storage 102 through secondary induction amplifier 22, data bus 23.In the present embodiment, reading the time for reading that timing simulation device 108 simulated is that data are sent (that is row are opened) from the memory cell array, by secondary induction amplifier 22 and data bus 23, and arrives transmission time of working storage 102.
At this, data bus 23 may be long metal wire (such as the metal wire that reaches 1000 μ m).
Present embodiment is except can be applicable to one reading command, also applicable to continuous reading command.
In sum, in embodiments of the present invention, read required time, can estimate out data and when read to the data working storage, so can avoid using the data of mistake (or non-required) in the CRC computing by the memory cell array by simulation.
In addition,, can avoid still imperfect tense just the CRC operation result being sent, improve the correctness of CRC output time point in the CRC computing by simulation CRC computing required time.
Though the present invention discloses as above with embodiment; right its is not in order to limit the present invention; has common knowledge in the technical field under any; without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention is as the criterion when looking the scope that claims define.
Claims (16)
1. the read operation control method of a memory body is characterized in that it comprises:
The reading command of decoding is that a home address reads signal;
The address signal of decoding is an internal address signal;
Read signal and this internal address signal according to this home address, read data from this memory body;
Postpone by analog data transmissions, whether be ready for to indicate this sense data;
Indicate this sense data when this data transfer delay analog result and be ready for, this sense data is carried out a bug check, whether correct to check this sense data;
Simulate the operation time of this bug check, whether finish to indicate this bug check; And
When this bug check analog result indicates this bug check to finish, send this error check results to this memory body outside.
2. the read operation control method of memory body according to claim 1 is characterized in that described data transfer delay simulation steps comprises:
Simulate these data and partly read out to a data transfer path between a data working storage of delivering in this memory body from the data storing in this memory body.
3. the read operation control method of memory body according to claim 1 is characterized in that described data transfer delay simulation steps comprises:
Postpone this home address and read signal; And
This home address after postponing reads signal, indicates this sense data to be ready for.
4. the read operation control method of memory body according to claim 1 is characterized in that this step of this operation time of described this bug check of simulation comprises:
Simulate interior being used to of this memory body and carry out the circuit framework of a bug check unit of this bug check.
5. the read operation control method of memory body according to claim 1 is characterized in that this step of this operation time of described this bug check of simulation comprises:
Postpone to be used to this data transfer delay analog result of indicating this sense data to be ready for; And
This data transfer delay analog result after postpone indicates this bug check to finish.
6. the read operation control method of memory body according to claim 1 is characterized in that, wherein reads signal and this internal address signal according to this home address, and this step of reading these data from this memory body comprises:
This home address is read signal and this internal address signal is decoded into a column selection line signal; And
According to this column selection line signal, read this data from this memory body.
7. the read operation control method of a memory body is characterized in that it comprises:
The reading command of decoding is that a home address reads signal;
The address signal of decoding is an internal address signal;
Read signal and this internal address signal according to this home address, the data storing in this memory body is partly read data;
This sense data is delivered to a bug check unit in this memory body, whether correct to check this sense data;
Simulate the operation time of this bug check unit, whether finish to indicate this bug check; And
Finish when this bug check simulation shows this bug check, send this error check results that this bug check unit produced to this memory body outside.
8. the read operation control method of memory body according to claim 7 is characterized in that, this step of wherein simulating this operation time of this bug check unit comprises:
Simulate the circuit framework of this bug check unit.
9. the read operation control method of memory body according to claim 7 is characterized in that, this step of wherein simulating this operation time of this bug check unit comprises:
Postpone to be used to this data transmission analog result of indicating this sense data to be ready for; And
By this data transmission analog result after postponing, indicate this bug check to finish.
10. the read operation control method of memory body according to claim 7 is characterized in that, wherein reads signal and this internal address signal according to this home address, and this step of partly reading these data from this data storing of this memory body comprises:
This home address is read signal and this internal address signal is decoded into a column selection line signal; And
According to this column selection line signal, read this data from this memory body.
11. the read operation control method of a memory body, this memory body comprise a memory cell array at least, a data working storage and a bug check unit is characterized in that this method comprises:
The reception and the reading command of decoding are that a home address reads signal;
The address signal of decoding is an internal address signal;
Read signal and this internal address signal according to this home address, read data from this memory cell array;
This sense data is sent to this memory body outside;
Simulate these data and read out to the data transfer delay that arrives between this data working storage, be ready for signal to produce data from this memory cell array;
Be ready for signal according to these data, this sense data is delivered to this bug check unit from this data working storage;
By this bug check unit this sense data is carried out bug check, to produce a bug check sign indicating number;
Simulate the bug check operation time of this bug check unit, be ready for signal to export a bug check; And
Be ready for signal according to this bug check, send this bug check sign indicating number that this bug check unit produced to this memory body outside.
12. the read operation control method of memory body according to claim 11 is characterized in that, wherein:
This memory body more comprises: a level induction amplifier, and the data bus between between this secondary induction amplifier and this data working storage;
This data transfer delay simulation steps comprises:
Simulate this sense data and send, arrive the transmission path of this data working storage by this secondary induction amplifier and this data bus from this memory cell array.
13. the read operation control method of memory body according to claim 11 is characterized in that, wherein this data transfer delay simulation steps comprises:
Postpone this home address and read signal; And
Read signal by this home address after postponing, indicate this sense data to be ready for.
14. the read operation control method of memory body according to claim 11 is characterized in that, this step of wherein simulating this bug check operation time of this bug check unit comprises:
Simulate the circuit framework of this bug check unit.
15. the read operation control method of memory body according to claim 11 is characterized in that, this step of wherein simulating this bug check operation time of this bug check unit comprises:
Postpone these data and be ready for signal; And
Be ready for signal by these data after postponing, indicate this bug check computing to finish.
16. the read operation control method of memory body according to claim 11 is characterized in that, wherein reads signal and this internal address signal according to this home address, this step of reading these data from this memory cell array comprises:
This home address is read signal and this internal address signal is decoded into a column selection line signal; And
According to this column selection line signal, from this mnemon array sense data.
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| CN2007101017211A CN101295537B (en) | 2007-04-24 | 2007-04-24 | Reading operation control method of memory body |
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| CN2007101017211A CN101295537B (en) | 2007-04-24 | 2007-04-24 | Reading operation control method of memory body |
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| CN101295537B true CN101295537B (en) | 2010-10-27 |
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| CN102568590A (en) * | 2010-12-17 | 2012-07-11 | 西安奇维测控科技有限公司 | Electronic disc self-destructing method based on microcontroller |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5140557A (en) * | 1989-09-13 | 1992-08-18 | Sharp Kabushiki Kaisha | Static random access memory of an energy-saving type |
| US20050033899A1 (en) * | 1998-01-04 | 2005-02-10 | Mosaid Technologies Incorporated | Semiconductor memory asynchronous pipeline |
| CN1655282A (en) * | 2001-08-31 | 2005-08-17 | 富士通株式会社 | Nonvolatile semiconductor memory devices |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5140557A (en) * | 1989-09-13 | 1992-08-18 | Sharp Kabushiki Kaisha | Static random access memory of an energy-saving type |
| US20050033899A1 (en) * | 1998-01-04 | 2005-02-10 | Mosaid Technologies Incorporated | Semiconductor memory asynchronous pipeline |
| CN1655282A (en) * | 2001-08-31 | 2005-08-17 | 富士通株式会社 | Nonvolatile semiconductor memory devices |
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