CN101290582A - Modularized clock precise multi-core system simulator accomplishing method - Google Patents
Modularized clock precise multi-core system simulator accomplishing method Download PDFInfo
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Abstract
The invention discloses a method for realizing a componentized multi-core system simulator with a precise clock. The method takes a multi-core processor as a simulated target, takes componentization as a starting point, encapsulates composition parts of a multi-core system structure as components, guarantees the assembly configuration with the components as a unit, and has good flexibility. The method not only can simulate the motions of in-core pipelines, but also can simulate the motions among a plurality of processor cores. The method realizes the componentized multi-core system simulator with a precise clock, can simulate the motions of the in-core pipelines as well as the motions among the processor cores, takes componentization as the starting point, encapsulates the composition parts of the multi-core system structure as components, guarantees the assembly configuration with the components as the unit, and has good flexibility.
Description
Technical field
The present invention relates to multi-core system structural simulation device, particularly relate to the implementation method of the accurate multi-core system simulator of a kind of modularized clock.
Background technology
And along with the raising of processor host frequency, it is faster that the power consumption of processor raises.The processor of a dominant frequency more than 2GHz for example, its power consumption has reached nearly 100W, and this has been the limit of wind-cooling heat dissipating technology.If continue to increase the dominant frequency of processor, processor can't move because heat radiation is excessive probably.Being the active demand that processor performance is promoted on the one hand, is that present lifting processor performance mode runs into bottleneck on the one hand.In the face of the condition of this embarrassment, each big processor manufacturer all begins the method for the new lifting processor performance of positive searching.
Under such background, the polycaryon processor technology is arisen at the historic moment.The basic thought of polycaryon processor is exactly the processor that substitutes a high primary frequency by the processor of a plurality of low dominant frequency.
On physical arrangement, the polycaryon processor technology is exactly integrated a plurality of processor cores on same silicon chip, and their collaborative work in actual motion is to reach the purpose of performance multiplication.The polycaryon processor of having issued is a lot, and such as the Power4 chip of IBM Corporation, it has at first used two independently to handle core, and high-end Sun Microsystems has also used the process chip of the multinuclear heart.Intel is after Itanium 2, announced that code name is the Itanium development plan of future generation of Tanglewood, brand-new Itanium chip is the highest will comprise 16 separate processor for this, adds Hyper-Threading, and this processor can be handled up to 32 threads.
Along with the raising of processor performance, the structure of processor is also complicated more, makes the deviser need carefully weigh when a high-performance processor of design, can not be again simply by virtue of experience, intuition.Simulator can help the deviser to assess various design proposals, selected rapidly reasonable plan.Therefore in the modern processors structured design process, the status of simulator seems more and more.
Clock accurately simulation is the principal character of a behavioral simulator.Only can carry out meticulous simulation and just can reflect various problems in the system design the behavior of system, thus for the design improvement valuable foundation is provided.
Saved trouble and the cost that just can test after realizing hardware design by hardware carrying out hardware design and research on the simulator.A design cycle flow process of traditional hardware design and solution conceptual design is at first to carry out structural design, realizes by FPGA, carries out the test of every performance again, and is last again at the problem of finding in the test, carries out design improved.Wherein the test link to hardware will spend a large amount of time and efforts.Change all for the every bit of hardware and will be again it to be realized the test that could continue its performance.This is very loaded down with trivial details, very time-consuming thing.If realize to save a lot of time and efforts to the test of hardware design with software.
With respect to hardware, software is more flexible, and each the modification as long as recompility just can be proceeded test makes that test is more convenient.So can test and revise existing hardware systems with simulator earlier, when obtaining a design proposal of being satisfied with relatively, realize with hardware again, test, so just can reduce the design cycle of architecture greatly.
With realize hardware design by hardware description language and utilize logic synthesis software to carry out analysis-by-synthesis again and compare, realize that with simulator the design of hardware can not only describe the waveform situation of each clock period hardware input and output, can also the ruuning situation of hardware be added up as the handling capacity of processor, the operating position of buffer memory, the information such as idle condition of bus; Simultaneously the demand that the deviser can also basis oneself is added the statistical information to hardware ruuning situation, thereby makes the test of hardware design have greater flexibility and extensibility.
Summary of the invention
The object of the present invention is to provide the implementation method of the accurate multi-core system simulator of a kind of modularized clock.
The technical scheme that the present invention solves its technical matters employing is as follows:
1) architecture componentization:
According to function the multi-core system structure is divided, divide the back and form: primary processor nuclear, a plurality of auxiliary processor nuclear, processor bus, Memory Controller Hub and internal memory by five parts;
2) component interface design:
Interface between the design component, component interface mainly contains: the interface of main equipment and processor bus, the interface of slave unit and processor bus, the interface of moderator and processor bus;
The interface of main equipment and processor bus is positioned at the junction of main equipment and processor bus, and its function is to connect main equipment and processor bus, realizes the data transmission between main equipment and the processor bus;
The interface of slave unit and processor bus is positioned at the junction of slave unit and processor bus, and its function is to connect slave unit and processor bus, realizes the data transmission between slave unit and the processor bus;
The interface of moderator and processor bus is positioned at the junction of processor bus and bus arbiter, and its function is to connect moderator and processor bus, makes the request that president's device can be accepted to transmit on the bus, and arbitration result is returned to bus;
3) the accurate simulation of clock comprises:
The first step, the microstructure of simulation actual hardware;
Second step, the different frequency in the simulation system;
The 3rd step, the agreement of realization internal system.
The present invention compares with background technology, and the useful effect that has is:
The present invention is the implementation method of the accurate multi-core system simulator of a kind of modularized clock, its major function is to be simulated target with the polycaryon processor, turn to starting point with assembly, the building block of multi-core system structure is encapsulated as assembly, assurance is the assembled configuration of unit with the assembly, and better flexibility is arranged.The action of streamline in the nuclear can not only be simulated, the action between a plurality of processor cores can also be simulated.This method has realized the accurate multi-core system simulator of clock, helps multicore processor architecture design, multinuclear software performance evaluation and soft or hard collaborative design, thereby proof procedure that can the accelerating hardware design has shortened the cycle of whole hardware design.
(1) high efficiency.This method has realized the accurate multi-core system simulator of modularized clock, can simulate the action of streamline in the nuclear, can also simulate the action between a plurality of processor cores.
(2) dirigibility.Turn to starting point with assembly, the building block of multi-core system structure is encapsulated as assembly, guarantee with the assembly to be the assembled configuration of unit, better flexibility is arranged.
Description of drawings
Fig. 1 is an implementation process synoptic diagram of the present invention.
Fig. 2 is a modularization multi-core system structural representation of the present invention.
Fig. 3 is a component interface design diagram of the present invention.
Embodiment
The present invention is the implementation method of the accurate multi-core system simulator of a kind of modularized clock, below in conjunction with Fig. 1 its specific implementation process is described.
1) architecture componentization:
The design of whole simulator is carried out in the Componentized mode.The implication of " modularization " is that each part of total system all is an independently module, to the modification of certain module with replace the use that does not influence other module." modularization " model also can be called as " general system " model.
Calculating unit and communication component can customize according to the demand of special applications.For calculating unit, may change their quantity or kind; For communication component, may select the particular communication pattern.So just formed one " system masterplate ", only needed the different assemblies in this masterplate of configuration just can produce new application oriented architecture.This shows that " modularization " requires to have the complete interface specification of a cover, and can reasonably divide module according to function.
Multi-core system structural simulation device is an architecture simulation device of supporting multinuclear.Therefore, this simulator structurally except the necessary component that will comprise common PC architecture, also will have the function of supporting the multi-core system structure.For the ease of research with realize, remove the inessential assembly in the general architecture, the truth of simulator structure technical ability reflection hardware that makes design again can brevity and lucidity, is easy to reorganization.
As shown in Figure 2, modularization multi-core system structure is made up of five parts, comprising: primary processor nuclear (being called for short main nuclear), auxiliary processor nuclear (being called for short auxilliary nuclear), processor bus, Memory Controller Hub and internal memory.Wherein can also there be finer structure the inside of primary processor nuclear, auxiliary processor nuclear and processor bus.Wherein, the number of auxilliary nuclear can be configured according to the difference of applied environment, can be one, also can be configured to a plurality of (being no more than 16).
2) component interface design:
Interface between the design component.As shown in Figure 3, component interface mainly contains: the interface of main equipment and processor bus, the interface of slave unit and processor bus, the interface of moderator and processor bus.
The interface of main equipment and processor bus is positioned at the junction of main equipment and processor bus, and its function is to connect main equipment and processor bus, realizes the data transmission between main equipment and the processor bus.Wherein main equipment refers to the requestor of bus transfer.Processor core is exactly a typical main equipment.
The interface of slave unit and processor bus is positioned at the junction of slave unit and processor bus, and its function is to connect slave unit and processor bus, realizes the data transmission between slave unit and the processor bus.Wherein slave unit refers to the recipient of bus transfer.Memory Controller Hub is exactly a typical slave unit.
The interface of moderator and processor bus is positioned at the junction of processor bus and bus arbiter, and its function is to connect moderator and processor bus, makes the request that president's device can be accepted to transmit on the bus, and arbitration result is returned to bus.
3) clock is simulated accurately:
Make the behavior of simulator will meet the ruuning situation of hardware, at first will simulate the microstructure of actual hardware.Such as simulating a processor, also to realize internal components such as demoder, register, arithmetical unit simultaneously.
Different frequency in its less important simulation system.Such as, the time that internal memory reads is a hundreds of clock period, this is not still because the data that read need be transferred to processor from internal memory, and be because internal memory operates on the different clock frequencies with processor, the clock period of an internal memory may be tens times of clock period of a processor.
The 3rd is the agreement that will realize internal system, at first will apply for from the master transmissions on the bus to slave unit such as data, after being arbitrated, obtaining transmitting rights, just can carry out the transmission of data.This process is by the agreement defined of bus, therefore in order to meet the actual conditions of data transmission, also will realize it.
In order to improve the efficient of simulator, simulator can only guarantee that total system is corresponding at the state on the triggering edge of clock and the behavior of hardware, sometimes even can only guarantee to compare with the hardware agenda, the state of total system will be postponed a clock period, and can not guarantee that the state of system is all consistent with hardware at each time point.This mainly is because the actual hardware behavior is a nonlinear structure, and simulator needs the order of a linearity to move.Such as, a gate circuit has two inputs and an output, and in the situation of actual hardware, the change of any one input all can change output.If the behavior of real simulated hardware just need be represented with a thread that respectively the thread of gate circuit will be monitored the variation of two inputs at any time to device and this gate circuit of two inputs, and change output according to the variation of input.Will waste a lot of times like this in the variation of monitoring input.And in fact, for a system that clock control is arranged, the result of output only with the active edges of clock along the time output relevant.Therefore only need the active edges of clock along the time change the output result according to input value and just can guarantee the correctness exported.
Actual hardware system be a nonlinear structure that has feedback, and the flow process of computer program is the structure of a linearity, will find out a method its linearization on original nonlinear structure like this.The main foundation of this linearizing method is in logic a sequencing between physical device.Such as in the processor of a pipeline organization, carrying out an instruction needs first instruction fetch; Through row decoding, determine the function of instruction again; Calculate according to the requirement of instruction again; Being the operation of access memory then, is that result of calculation is write back in the register at last.The device that whole process relates to is just simple to be connected, and does not have order successively, and the order of a priority is logically arranged.Therefore just can be when simulation according to this order, the related device of the design of operation instruction fetch earlier, the related device of the decoding of reruning, by that analogy.
Claims (1)
1. the implementation method of the accurate multi-core system simulator of modularized clock is characterized in that:
1) architecture componentization:
According to function the multi-core system structure is divided, divide the back and form: primary processor nuclear, a plurality of auxiliary processor nuclear, processor bus, Memory Controller Hub and internal memory by five parts;
2) component interface design:
Interface between the design component, component interface mainly contains: the interface of main equipment and processor bus, the interface of slave unit and processor bus, the interface of moderator and processor bus;
The interface of main equipment and processor bus is positioned at the junction of main equipment and processor bus, and its function is to connect main equipment and processor bus, realizes the data transmission between main equipment and the processor bus;
The interface of slave unit and processor bus is positioned at the junction of slave unit and processor bus, and its function is to connect slave unit and processor bus, realizes the data transmission between slave unit and the processor bus;
The interface of moderator and processor bus is positioned at the junction of processor bus and bus arbiter, and its function is to connect moderator and processor bus, makes the request that president's device can be accepted to transmit on the bus, and arbitration result is returned to bus;
3) the accurate simulation of clock comprises:
The first step, the microstructure of simulation actual hardware;
Second step, the different frequency in the simulation system;
The 3rd step, the agreement of realization internal system.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102402482A (en) * | 2011-11-22 | 2012-04-04 | 北京星网锐捷网络技术有限公司 | Test system and method |
| CN102932559A (en) * | 2012-11-09 | 2013-02-13 | 中山爱科数字科技股份有限公司 | Method for reducing power consumption of smartphones |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102402482A (en) * | 2011-11-22 | 2012-04-04 | 北京星网锐捷网络技术有限公司 | Test system and method |
| CN102932559A (en) * | 2012-11-09 | 2013-02-13 | 中山爱科数字科技股份有限公司 | Method for reducing power consumption of smartphones |
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