CN101281309A - Drive circuit of vertical direction matching type LCD device and drive method thereof - Google Patents
Drive circuit of vertical direction matching type LCD device and drive method thereof Download PDFInfo
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- CN101281309A CN101281309A CNA2007100739579A CN200710073957A CN101281309A CN 101281309 A CN101281309 A CN 101281309A CN A2007100739579 A CNA2007100739579 A CN A2007100739579A CN 200710073957 A CN200710073957 A CN 200710073957A CN 101281309 A CN101281309 A CN 101281309A
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Abstract
The invention relates to a driving circuit and driving method of a vertical allocation type liquid crystal display device. The driving circuit of a vertical allocation type liquid crystal display device includes a plurality of scan lines, a plurality of data lines and a plurality of pixel units. The pixel unit includes a first sub-pixel unit and a second sub-pixel unit, wherein, the first sub-pixel unit includes a thin-film transistor, the second sub-pixel unit includes a first diode and a second diode; the first sub-pixel unit is driven by the thin-film transistor, the second sub-pixel unit is driven by the two diode driver.
Description
Technical field
The present invention relates to a kind of driving circuit and driving method of vertical alignment liquid crystal display device.
Background technology
Itself does not have the characteristics of luminescence liquid crystal in the liquid crystal indicator, and it is to adopt the electric field controls liquid crystal molecule to reverse and realize passing through or not passing through of light, thereby reaches the purpose of demonstration.The liquid crystal drive mode of tradition liquid crystal indicator is a nematic mode, yet its angular field of view is narrow,, when observing picture from different perspectives, will observe different display effects that is.For solving the narrower problem in nematic mode liquid crystal indicator visual angle, industry proposes a kind of four territory vertical alignment liquid crystal display devices, by a plurality of "＜" shape projection and groove being set at interval at two substrates, each pixel cell is divided into four zones, the orientation of the liquid crystal molecule in each zone is disperseed, enlarge the overall viewing angle of this pixel, and then improve the viewing angle characteristic of liquid crystal indicator.
Yet, because long axis of liquid crystal molecule is different with the optical index of minor axis, will produce color offset phenomenon when observing four territory vertical alignment liquid crystal display devices from different perspectives, influence display quality.For improving the color offset phenomenon of four territory vertical alignment liquid crystal display devices, industry proposes again a pixel cell is divided into two sub-pixel unit, and provide two operating voltages that sub-pixel unit is different, utilize the angle of inclination difference of liquid crystal molecule under the different operating voltage, and a plurality of "＜" shape projection and groove are set at interval at two substrates, make each sub-pixel unit all realize the four territories orientation of liquid crystal molecule, thereby realize the eight territories demonstration of vertical alignment liquid crystal display device.
Seeing also Fig. 1 and Fig. 2, is a kind of driving circuit synoptic diagram of prior art vertical alignment liquid crystal display device, and Fig. 2 is the part enlarged diagram of the driving circuit of vertical alignment liquid crystal display device shown in Figure 1.The driving circuit 100 of this vertical alignment liquid crystal display device comprises many sweep traces that are parallel to each other 101, many be parallel to each other and with these sweep trace 101 vertically insulated first crossing data line 103 and second data lines 105, a plurality of the first film transistors 111 that are positioned at this sweep trace 101 and these first data line, 103 intersections, a plurality of second thin film transistor (TFT)s 121 that are positioned at this sweep trace 101 and these second data line, 105 intersections, a plurality of first pixel electrodes 113, a plurality of second pixel electrodes 123, a plurality of public electrodes 107, a plurality of first memory capacitance 115 and a plurality of second memory capacitance 125.
The grid of this first film transistor 111 (not indicating) connects this sweep trace 101, and source electrode (not indicating) connects this first data line 103, and drain electrode (not indicating) connects this first pixel electrode 113.The grid of this second thin film transistor (TFT) 121 (not indicating) connects this sweep trace 101, and source electrode (not indicating) connects this second data line 105, and drain electrode (not indicating) connects this second pixel electrode 123.
This first pixel electrode 113, this public electrode 107 and therebetween liquid crystal molecule (figure does not show) constitute a plurality of first liquid crystal capacitances 117.This first memory capacitance 115 is in parallel with this first liquid crystal capacitance 117.This second pixel electrode 123, this public electrode 107 and therebetween liquid crystal molecule (figure does not show) constitute a plurality of second liquid crystal capacitances 127.This second memory capacitance 125 is in parallel with this second liquid crystal capacitance 127.
One the first film transistor 111, one second thin film transistor (TFT) 121, one first liquid crystal capacitance 117, one second liquid crystal capacitance 127, one first memory capacitance 115 and one second memory capacitance, 125 definition, one pixel cell 130.Wherein, this first film transistor 111, first liquid crystal capacitance 117 and first memory capacitance 115 are defined as one first sub-pixel unit 110; This second thin film transistor (TFT) 121, second liquid crystal capacitance 127 and second memory capacitance 125 are defined as one second sub-pixel unit 120.
This sweep trace 101 is used for controlling the conducting of this first film transistor 111 and second thin film transistor (TFT) 121 and ending.This first data line 103 be used for when these the first film transistor 111 conductings, providing gray scale voltage to this first sub-pixel unit 110 to realize its demonstration; This second data line 105 be used for when these second thin film transistor (TFT), 121 conductings, providing gray scale voltage to this second sub-pixel unit 120 to realize its demonstration.Because this first sub-pixel unit 110 and second sub-pixel unit 120 are driven by the first film transistor 111 and second thin film transistor (TFT) 121 respectively, and then these two sub-pixel unit 111,121 have different operating voltages.
Yet, one pixel cell 130 of the driving circuit 100 of this vertical alignment liquid crystal display device needs 103,105 and two thin film transistor (TFT)s of two data lines 111,121 to drive, and makes that wiring complexity, the cost of driving circuit 100 of this vertical alignment liquid crystal display device is higher.
Summary of the invention
For solving complicated, the cost problem of higher of driving circuit wiring of vertical alignment liquid crystal display device in the prior art, be necessary to provide a kind of driving circuit simple, lower-cost vertical alignment liquid crystal display device that connects up.
In addition, also be necessary to provide a kind of driving method of driving circuit of above-mentioned vertical alignment liquid crystal display device.
A kind of driving circuit of vertical alignment liquid crystal display device, it comprises that data line that multi-strip scanning line, many and this sweep trace insulation are intersected and a plurality of this sweep trace and data line intersect the pixel cell that the Minimum Area that constitutes defines.This pixel cell comprises one first sub-pixel unit and one second sub-pixel unit, this first sub-pixel unit comprises a thin film transistor (TFT) and one first pixel electrode, this second sub-pixel unit comprises one first diode, one second diode and one second pixel electrode, wherein, the grid of this thin film transistor (TFT) connects this sweep trace, source electrode connects this data line, drain electrode connects this first pixel electrode, the anode of first diode and the negative electrode of second diode, and the negative electrode of the anode of this first diode and second diode all is connected this second pixel electrode.
A kind of driving method of driving circuit of above-mentioned vertical alignment liquid crystal display device, it comprises the steps: that a. provides the i time sweep signal to this n horizontal scanning line, this data line is exported first gray scale voltage and is loaded into this first pixel electrode by this thin film transistor (TFT), is loaded into this second pixel electrode by this thin film transistor (TFT) and this first diode; B. stop to provide sweep signal to arrive this n horizontal scanning line, this thin film transistor (TFT) ends; C. provide the i+1 time sweep signal to this n horizontal scanning line, this data line is exported second gray scale voltage and is loaded into this first pixel electrode by this thin film transistor (TFT), is loaded into this second pixel electrode by this thin film transistor (TFT) and this second diode; D. stop to provide sweep signal to arrive this n horizontal scanning line, this thin film transistor (TFT) ends.
With respect to prior art, in the driving circuit and driving method of above-mentioned vertical alignment liquid crystal display device, two sub-pixel unit of one pixel cell only need a data line, a thin film transistor (TFT) and two diodes to drive, and can realize that eight territories show, thereby wiring is simple, cost is lower.
Description of drawings
Fig. 1 is a kind of driving circuit synoptic diagram of prior art vertical alignment liquid crystal display device.
Fig. 2 is the part enlarged diagram of the driving circuit of vertical alignment liquid crystal display device shown in Figure 1.
Fig. 3 is the synoptic diagram of driving circuit one better embodiment of vertical alignment liquid crystal display device of the present invention.
Fig. 4 is the part enlarged diagram of the driving circuit of vertical alignment liquid crystal display device shown in Figure 3.
Fig. 5 is the part drive waveforms figure of the driving circuit of vertical alignment liquid crystal display device shown in Figure 3.
Embodiment
See also Fig. 3 and Fig. 4, Fig. 3 is the synoptic diagram of driving circuit one better embodiment of vertical alignment liquid crystal display device of the present invention, and Fig. 4 is the part enlarged diagram of the driving circuit of vertical alignment liquid crystal display device shown in Figure 3.The driving circuit 200 of this vertical alignment liquid crystal display device comprise that many sweep traces that are parallel to each other 201 and many are parallel to each other and with these sweep trace 201 vertically insulated crossing data lines 203.This sweep trace 201 intersects the minimum rectangular area that constitutes with this data line 203 and defines a plurality of pixel cells 230.
This pixel cell 230 comprises one first sub-pixel unit 210 and one second sub-pixel unit 220.This first sub-pixel unit 210 comprises a thin film transistor (TFT) 211, one first pixel electrode 213, a public electrode 207 and one first memory capacitance 215.This second sub-pixel unit comprises one first diode 221, one second diode 222, one second pixel electrode 223, a public electrode 207 and one second memory capacitance 225.
The grid of this thin film transistor (TFT) 211 (not indicating) connects this sweep trace 201, source electrode (not indicating) connects this data line 203, drain electrode (not indicating) connects the anode (not indicating) of this first pixel electrode 213, this first diode 221 and the negative electrode (not indicating) of second diode 222, and the negative electrode (not indicating) of the anode of this first diode 221 (not indicating) and second diode 222 all is connected this second pixel electrode 223.This public electrode 207 and this first pixel electrode 213 and therebetween a plurality of first liquid crystal capacitances 217 of liquid crystal molecule (figure does not show) formation are also with this second pixel electrode 223 and therebetween a plurality of second liquid crystal capacitances 227 of liquid crystal molecule (figure does not show) formation.This first liquid crystal capacitance 217 is in parallel with this first memory capacitance 215, and this second liquid crystal capacitance 227 is in parallel with this second memory capacitance 225.
This sweep trace 201 is used for controlling the conducting of this thin film transistor (TFT) 211 and ending.This data line 203 is used for providing when 211 conductings of this thin film transistor (TFT) gray scale voltage to arrive this pixel cell 230 to realize demonstration.This first sub-pixel unit 210 is driven by this thin film transistor (TFT) 211, and this second sub-pixel unit 220 is driven by these two diodes 221,222.
Seeing also Fig. 5, is the part drive waveforms figure of the driving circuit 200 of this vertical alignment liquid crystal display device.Wherein, G
nBe the sweep signal of n horizontal scanning line, V
D1Be first gray scale voltage of first sub-pixel unit 210, V
D2Be second gray scale voltage of first sub-pixel unit 210, V
D1' be first gray scale voltage of second sub-pixel unit 220, V
D2' be second gray scale voltage of second sub-pixel unit 220, Vcom is the voltage of public electrode 207.
The principle of work of the driving circuit 200 of this vertical alignment liquid crystal display device is as follows:
t
0-t
1During this time, promptly n horizontal scanning line 201 is provided for the i time during the sweep signal, thin film transistor (TFT) 211 conductings on this row, and simultaneously, this data line 203 provides the first gray scale voltage V
D1Source electrode, drain electrode by this thin film transistor (TFT) 211 are loaded into the anode of this first pixel electrode 213, this first memory capacitance 215, this first diode 221 and the negative electrode of second diode 222, these first memory capacitance, 215 chargings, these first diode, 221 conductings, this second diode 222 ends, this first gray scale voltage V
D1By the first gray scale voltage V after these first diode, 221 generation pressure drops
D1' be loaded into this second pixel electrode 223 and this second memory capacitance 225, these second memory capacitance, 225 chargings, and then this first sub-pixel unit 210 is different with the operating voltage of this second sub-pixel unit 220, and its pressure reduction is the conduction voltage drop of this first diode 221, is about 0.7V.
t
1-t
2During this time, promptly the i time sweep signal of this n horizontal scanning line 201 is closed to the i+1 time and is provided before the sweep signal the first gray scale voltage V of these first memory capacitance, 215 these first pixel electrodes 213 of maintenance
D1, this second memory capacitance 225 keeps the first gray scale voltage V of this second pixel electrode 223
D1', to keep the demonstration of this first sub-pixel unit 210 and second sub-pixel unit 220.
t
2-t
3During this time, promptly this n horizontal scanning line 201 is provided for the i+1 time during the sweep signal, thin film transistor (TFT) 211 conductings on this row, and simultaneously, this data line 203 is provided the second gray scale voltage V
D2, because of the needs of inversion driving, this second gray scale voltage V
D2Be low level, and this first liquid crystal capacitance 217 and first memory capacitance 215 still keep the first gray scale voltage V at this moment
D1Be high level, make this first liquid crystal capacitance 217 and first memory capacitance 215 pass through drain electrode, the source electrode discharge of this thin film transistor (TFT) 211, keep the second gray scale voltage V up to this first pixel electrode 213
D2Till; In like manner, also at this moment, this first diode 221 ends, and this second liquid crystal capacitance 227 and this second memory capacitance 225 are also by these second diode, 222 discharges, till being higher than this first pixel electrode 213 about 0.7V to the current potential of this second pixel electrode 223, thus this second gray scale voltage V
D2Be provided to this first pixel electrode 213, this second gray scale voltage V
D2' also be provided to this second pixel electrode 223, and then this first sub-pixel unit 210 is different with the operating voltage of this second sub-pixel unit 220, its pressure reduction is the conduction voltage drop of this second diode 222, is about 0.7V.
t
3-t
4During this time, promptly the i+1 time sweep signal of this n horizontal scanning line 201 is closed to the i+2 time and is provided before the sweep signal the second gray scale voltage V of these first memory capacitance, 215 these first pixel electrodes 213 of maintenance
D2, this second memory capacitance 225 keeps the second gray scale voltage V of this second pixel electrode 223
D2', to keep the demonstration of this first sub-pixel unit 210 and second sub-pixel unit 220.
t
4Repeat above-mentioned steps later on.
With respect to prior art, one pixel cell 230 of the driving circuit 200 of vertical alignment liquid crystal display device of the present invention only needs a data line 203, a thin film transistor (TFT) 211 and two diodes 221,222 to drive, can realize that eight territories show, thereby wiring is simple, cost is lower.
Claims (10)
1. the driving circuit of a vertical alignment liquid crystal display device, it comprises the multi-strip scanning line, many the data lines that intersect with the insulation of this sweep trace and a plurality of this sweep trace and data line intersect the pixel cell that the Minimum Area that constitutes defines, this pixel cell comprises one first sub-pixel unit and one second sub-pixel unit, this first sub-pixel unit comprises a thin film transistor (TFT) and one first pixel electrode, this second sub-pixel unit comprises one second pixel electrode, it is characterized in that: this second sub-pixel unit also comprises one first diode and one second diode, the grid of this thin film transistor (TFT) connects this sweep trace, source electrode connects this data line, drain electrode connects this first pixel electrode, the negative electrode of the anode of first diode and second diode, the negative electrode of the anode of this first diode and second diode all is connected this second pixel electrode.
2. the driving circuit of vertical alignment liquid crystal display device as claimed in claim 1, it is characterized in that: this first sub-pixel unit further comprises a public electrode, and itself and this first pixel electrode and therebetween liquid crystal molecule constitute one first liquid crystal capacitance.
3. the driving circuit of vertical alignment liquid crystal display device as claimed in claim 1, it is characterized in that: this second sub-pixel unit further comprises a public electrode, and itself and this second pixel electrode and therebetween liquid crystal molecule constitute one second liquid crystal capacitance.
4. the driving circuit of vertical alignment liquid crystal display device as claimed in claim 2, it is characterized in that: this first sub-pixel unit comprises one first memory capacitance, it is in parallel with this first liquid crystal capacitance.
5. the driving circuit of vertical alignment liquid crystal display device as claimed in claim 3, it is characterized in that: this second sub-pixel unit comprises one second memory capacitance, it is in parallel with this second liquid crystal capacitance.
6. the driving method of the driving circuit of vertical alignment liquid crystal display device as claimed in claim 1, it comprises the steps:
A. provide the i time sweep signal to this n horizontal scanning line, this data line is exported first gray scale voltage and is loaded into this first pixel electrode by this thin film transistor (TFT), is loaded into this second pixel electrode by this thin film transistor (TFT) and this first diode;
B. stop to provide sweep signal to arrive this n horizontal scanning line, this thin film transistor (TFT) ends;
C. provide the i+1 time sweep signal to this n horizontal scanning line, this data line is exported second gray scale voltage and is loaded into this first pixel electrode by this thin film transistor (TFT), is loaded into this second pixel electrode by this thin film transistor (TFT), this second diode;
D. stop to provide sweep signal to arrive this n horizontal scanning line, this thin film transistor (TFT) ends.
7. the driving method of the driving circuit of vertical alignment liquid crystal display device as claimed in claim 6, it is characterized in that: this first sub-pixel unit further comprises a public electrode and one first memory capacitance, this public electrode and this first pixel electrode and therebetween liquid crystal molecule constitute one first liquid crystal capacitance, this first liquid crystal capacitance is in parallel with this first memory capacitance, in this step a and c, this first memory capacitance is in charged state.
8. the driving method of the driving circuit of vertical alignment liquid crystal display device as claimed in claim 6, it is characterized in that: this second sub-pixel unit comprises a public electrode and one second memory capacitance, this public electrode and this second pixel electrode and therebetween liquid crystal molecule constitute one second liquid crystal capacitance, this second liquid crystal capacitance is in parallel with this second memory capacitance, in this step a and c, this second memory capacitance is in charged state.
9. the driving method of the driving circuit of vertical alignment liquid crystal display device as claimed in claim 7, it is characterized in that: in this step b and d, this first memory capacitance keeps the voltage of this first liquid crystal capacitance.
10. the driving method of the driving circuit of vertical alignment liquid crystal display device as claimed in claim 8, it is characterized in that: in this step b and d, this second memory capacitance keeps the voltage of this second liquid crystal capacitance.
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| Application Number | Priority Date | Filing Date | Title |
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| CNB2007100739579A CN100573247C (en) | 2007-04-06 | 2007-04-06 | The driving circuit of vertical alignment liquid crystal display device and driving method |
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| CNB2007100739579A CN100573247C (en) | 2007-04-06 | 2007-04-06 | The driving circuit of vertical alignment liquid crystal display device and driving method |
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| CN102253549A (en) * | 2011-06-08 | 2011-11-23 | 深圳市华星光电技术有限公司 | Thin-film transistor array and liquid crystal display panel |
| CN104166287A (en) * | 2014-08-13 | 2014-11-26 | 深圳市华星光电技术有限公司 | Array substrate and liquid crystal display device |
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| CN105118471A (en) * | 2015-09-30 | 2015-12-02 | 深圳市华星光电技术有限公司 | Liquid crystal display panel and driving method thereof |
| CN105372890A (en) * | 2015-11-20 | 2016-03-02 | 青岛海信电器股份有限公司 | Pixel structure and liquid crystal display panel |
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| CN102253549A (en) * | 2011-06-08 | 2011-11-23 | 深圳市华星光电技术有限公司 | Thin-film transistor array and liquid crystal display panel |
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| CN104166287A (en) * | 2014-08-13 | 2014-11-26 | 深圳市华星光电技术有限公司 | Array substrate and liquid crystal display device |
| GB2557760A (en) * | 2015-08-11 | 2018-06-27 | Shenzhen China Star Optoelect | Liquid crystal display panel |
| WO2017024607A1 (en) * | 2015-08-11 | 2017-02-16 | 深圳市华星光电技术有限公司 | Liquid crystal display panel |
| CN105068345A (en) * | 2015-08-11 | 2015-11-18 | 深圳市华星光电技术有限公司 | Liquid crystal display panel |
| EA035140B1 (en) * | 2015-08-11 | 2020-05-06 | Шэньчжэнь Чайна Стар Оптоэлектроникс Текнолоджи Ко., Лтд. | Liquid crystal display panel |
| GB2557760B (en) * | 2015-08-11 | 2021-07-07 | Shenzhen China Star Optoelect | Liquid crystal display panel |
| CN105118471A (en) * | 2015-09-30 | 2015-12-02 | 深圳市华星光电技术有限公司 | Liquid crystal display panel and driving method thereof |
| US9786236B2 (en) | 2015-09-30 | 2017-10-10 | Shenzhen China Star Optoelectronics Technology Co., Ltd. | Liquid crystal panels and the driving methods thereof |
| CN105372890A (en) * | 2015-11-20 | 2016-03-02 | 青岛海信电器股份有限公司 | Pixel structure and liquid crystal display panel |
| CN113707107A (en) * | 2021-10-29 | 2021-11-26 | 惠科股份有限公司 | Pixel unit, pixel circuit and display panel |
| CN115657353A (en) * | 2022-12-28 | 2023-01-31 | 惠科股份有限公司 | Pixel circuit, pixel control method and display device |
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