CN101278355A - Non-volatile shadow latch using a nanotube switch - Google Patents

Non-volatile shadow latch using a nanotube switch Download PDF

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CN101278355A
CN101278355A CN200680024940.8A CN200680024940A CN101278355A CN 101278355 A CN101278355 A CN 101278355A CN 200680024940 A CN200680024940 A CN 200680024940A CN 101278355 A CN101278355 A CN 101278355A
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latch
memory device
voltage
circuit
state
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CN101278355B (en
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C·L·伯廷
F·郭
T·鲁克斯
S·L·孔瑟科
M·梅恩霍德
M·斯特拉斯伯格
R·斯瓦拉贾
X·M·H·黄
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Nantero Inc
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Nantero Inc
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Abstract

A non-volatile memory cell includes a volatile storage device that stores a corresponding logic state in response to electrical stimulus; and a shadow memory device coupled to the volatile storage device. The shadow memory device receives and stores the corresponding logic state in response to electrical stimulus. The shadow memory device includes a non-volatile nanotube switch that stores the corresponding state of the shadow device.

Description

Use the non-volatile shadow latch of nanotube switch
The cross reference of related application
The present invention requires following right of priority of applying for according to 35 U.S.C. § 119 (e), and the content of these applications integral body by reference is incorporated into this:
The U.S. Provisional Patent Application No.60/679 that is entitled as " Reversible Nanoswitch (reversible nanotube switch) " that on May 9th, 2005 submitted to, 029;
The U.S. Provisional Patent Application No.60/692 that is entitled as " Reversible Nanoswitch (reversible nanotube switch) " that on June 22nd, 2005 submitted to, 891;
The U.S. Provisional Patent Application No.60/692 that is entitled as " NRAM Nonsuspended Reversible NanoswitchNanotube Array (the non-reversible nanotube switch nano-tube array that suspends of NRAM) " that on June 22nd, 2005 submitted to, 918; And
The U.S. Provisional Patent Application No.60/692 that is entitled as " Embedded CNT Switch Applications For Logic (embedding of the application of CNT switch) " that on June 22nd, 2005 submitted to logic, 765.
The application relates to following application, and the content of these applications integral body by reference is incorporated into this:
The U.S. Patent application No. (waiting to deliver (TBA)) that is entitled as " Two-Terminal Nanotube Devices And Systems AndMethods Of Making Same (two-terminal nanotube devices and system and preparation method thereof) " that submits on the same day with the application; And
The U.S. Patent application No. (waiting to deliver) that is entitled as " Memory Arrays Using Nanotube Articles WithReprogrammable Resistance (use has the memory array of the nanotube articles of re-programmable resistance) " that submits on the same day with the application.
Background
Technical field
The present invention relates generally to the latch field of logic states, relate in particular to the non-volatile shadow latch that uses the two-terminal nanotube switch.
Association area is described
Volatile circuits and to continue be standard in the digital circuit.In the initial development stage, bipolar circuit is widely used in analog-and digital-circuit.More intensive and be easier to the very fast rise of the circuit based on FET integrated but more at a slow speed, and be introduced in the low cost and lower powered application such as counter, and bipolar circuit is used for high-speed applications.In order to eliminate the current bipolar only NMOS or the quiescent dissipation of PMOS chip only, introduced circuit, and almost eliminated quiescent dissipation, because power consumption only when circuit switches, occurs based on complementary cmos (combination NMOS and PMOS) device.FET device convergent-divergent (scaling) is introduced into and successfully is used for every two years circuit quantity being doubled approximately, improves the performance of device and circuit simultaneously, and all these is in low chip power and presses power consumption is maintained acceptable level.
Along with circuit quantity rises to 1,000,000, bipolar power consumption becomes too high, so that CMOS is used to replace bipolar circuit, and CMOS becomes the choice of technology of semiconductor industry to logical circuit, storer and analog equipment.Because the shared CMOS technology platform of various electric function (storer, digital and analog circuit), the System on Chip/SoC of integrated more than one hundred million circuit and several billibits (SoC) becomes possibility.Migration to new more intensive technology generation has realized more function on single-chip, and for economy and performance reason and finish.A new generation's technology (new technology node) causes transistor density to improve, and wherein increase of the current drives of device widths and interconnection distribution are more intensive.Yet for inferior 150nm technology, the convergent-divergent of device threshold voltage is difficulty all the more, causes high FET device OFF state leakage current and corresponding high quiescent dissipation.Use stock size and voltage scaling no longer can satisfy fast and dense chip, the made power consumption constraints speed of single-chip and the combination of function such as SoC.At the 90nm technology node, 25 to 50% of general power (dynamic and static power) is because the quiescent dissipation that leakage current causes.The product for the 65nm technology node is found in prediction, and quiescent dissipation will be above dynamic (operation) power consumption.A new generation's technology is subjected to the restriction of power consumption, especially is subjected to because the restriction of the quiescent dissipation that relatively poor convergent-divergent and the high device OFF state leakage current that is associated cause.Because such as many application such as PC, mobile phone, recreation is that portable also needs are battery-operated, so the control power consumption realizes that simultaneously high speed operation is essential.Since power consumption constraints the size of logical circuit and the combination of operating speed, need new chip architecture and circuit design solution realize continuing to increase of performance function.
U.S. Patent No. 6,097, the 243 described a kind of regulation mechanisms that in the inactive scheduled time slot of circuit, reduce clock speed with the reduction dynamic power of a kind of method proposition that reduce power by framework and design people such as Bertin.Static power is also reduced to increase threshold voltage and to reduce the leakage current that is associated by adjusting source-bulk voltage.Though this method can reduce the power consumption of some circuit, dynamically still keep relative higher with quiescent dissipation.In fact, the threshold voltage modulation that reduces power consumption only body region can be modulated matrix CMOS technology in use.SOI CMOS technology with independent device body zone of isolation can not be as U.S. Patent No. 6,097, and 243 modulate describedly.
In the U.S. Patent No. of passing through as people such as Bertin 6,097,241 described frameworks and design reduce in the correlation technique of power, and it is movable and increase circuit speed in the following stages to realize high speed operation that wherein activity detection circuit is monitored the first logic level place input circuit.Need modulation to have equally and as above be relevant to U.S. Patent No. 6,097, the device threshold voltage of the 243 association restrictions that further describe.
People's such as Bertin U.S. Patent No. 6,345,362 have described by framework and design and have reduced the another correlation technique of power, wherein use on the chip power management block on the processor controls unit and chip will be in functional unit on the multicore sheet of different capacity level be matched with require various speed instruction to optimize the chip power performance.In the above U.S. Patent No. 6,097 that is relevant to, under the 243 association restrictions that further describe, the passing threshold change in voltage is regulated the operand power and the associated speed of each functional unit.
People's such as Datar U.S. Patent No. 6,625,740 has been described by framework and design and has been reduced the distinct methods of power, and wherein instruction is examined and code is rearranged, and makes one group to instruct unwanted circuit to be de-energized.Circuit bank can be switched on by the needs of handling various instructions.In giving example, suppose that circuit needs 10 clock circulations to be in the OFF state, and need 10 circulations to return to full power state.In these circuit of outage dynamically and static power all be lowered, but between turnoff time, data can not be kept in register and will be lost, unless when outage, transfer to storer and when switching on, shift.
People's such as Goodnow U.S. Patent No. 6,658, another distinct methods that reduces power by framework and design has been described in 634, wherein logic is designed to guarantee that key logic net (critical logic net) comprises associated registers, and guarantees that with the logic composite software clock optionally stops and final data remains in the unwanted logic level register of specific instruction sequence.Though this method has reduced dynamic power consumption, quiescent dissipation is still higher because of leakage current.
U.S. Patent No. 5 people such as Bertin, 986, in 962, power reduces by framework and design to be realized, makes each register (latch) have the corresponding shadow register (latch) (cmos device of low current leakage) that keeps designing (optimization) for low-power.The state of this system is transferred to shadow latch when being transformed into low-power mode, and removes power from the part of chip or the logical circuit of entire chip.When power recovers, logic state is returned to each register.Though this method has significantly reduced dynamically and static power, and if entire chip be de-energized then in fact eliminated whole power consumptions except the low-power shadow register, shadow register has been introduced the obvious problem of himself.At first, low-power consumption register (latch) is a problem to α particle sensitivity and data integrity.Can still may need some technique variation to latch application of radiation hardening technique.Secondly, static power still consumes in the low-power shadow latch.And each high-performance latch is added low-power shadow latch enlarged markedly chip area, this has influence on chip design and has reduced the number of chips of monolithic wafer, and then has increased chip cost.
The high integrated products that has such as various circuit function of high logic and memory electric current, System on Chip/SoC (SoC) framework is the important component part of current semi-conductor industry PRACTICE OF DESIGN.Use the high integrated products design of matrix or SOI CMOS technology, for needing the high integration that the SoC device provided and the portable cell operating system particular importance of blended data and signal Processing.Particularly in consumption electronic product, product needed experiences variation with the design progress.The result, the common combination of using different elements of design, these elements comprise such as general (normally RISC framework) embedding microprocessor core, embed DSP, embed embedding, programmable logic functions that ASIC designs (eASIC), embeds FPGA, embedding storer and other function.The market-oriented time of expected product function is most important to the product success or failure, makes that having insufficient time to use usually comes optimizational function such as the method for customizing of optimizing the ASIC design, to have maximum performance under the total power consumption of minimum.Replace, design must comprise than optimal design consumption more manys the programmable logic functions of power, so that revise the dirigibility of product function when being implemented in design cycle and finishing soon and provide multiple use because of economic cause.
On single-chip, realize greater functionality and can be for economy and performance reason and carry out to the migration of new more intensive technology generation.In new technology generation (new technology node), cause that transistor density increases, and the current drives increase and the interconnection distribution of device widths are more intensive.Yet for inferior 150nm technology, device threshold voltage convergent-divergent difficulty increases, and causes high FET device OFF state leakage current and corresponding high quiescent dissipation.
Fig. 1 illustrates and is relevant to the technology node normalization power consumption in (and corresponding time).The source of Fig. 1 is the IEEE ACM (Association of Computing Machinery), in Dec, 2003.End node is represented with related door length with minimum feature size.Static power dwindles with size and is exponential increase, and the rate increase of dynamic (switching) power to relax.At 90nm technology node place, 25 to 50% of general power (dynamic and static power) is because the quiescent dissipation that leakage current causes.Prediction finds that for the product at 65nm technology node place, quiescent dissipation may surpass dynamically (operation) power consumption.New technology generation is subjected to the restriction of power consumption, especially the quiescent dissipation that causes owing to relatively poor convergent-divergent and the high device OFF state leakage current that causes.Use stock size and voltage scaling no longer can satisfy fast and dense chip, the combination of speed and function on the single-chip that made power consumption constraints such as SoC.Because be of portable form and need battery-operatedly such as many application of PC, mobile phone, recreation etc., be very important so control power consumption by chip architecture and circuit design.Yet even in the non-portable use such as workstation and server, the power consumption constraints that is caused by relatively poor CMOS technology convergent-divergent has also limited operating speed and required power management framework.
For success is in conjunction with power management in high integrated products design, the relation of understanding circuit layout efficiency and power consumption is extremely important.Fig. 2 illustrates for the various logic method for designing, realizes the required each operating energy of 32 bit manipulations (skin Jiao).The most flexible and multi-functional FPGA (Field Programmable Gate Array) is that least power is effective, needs 2 for the PC/ workstation, 000pJ and need 200pJ for the RISC architecture microprocessor.On the contrary, least flexible design method ASIC is that power is effective, only consumes 2pJ for identical logic function.DSP also is very effective, is 60pJ, because they are usually as quickening digital signal processing function to carry out specific digital signal processing task.Fig. 2 is derived from the speech that is entitled as " Low-Power Architecture (low-power framework) " of Bill Dally.
Bandwidth occupies leading in the required energy of various operations.Fig. 3 illustrates the required energy of register, ALU and OCD 32 bit manipulations and reads and shift 32 required energy (100pJ) at chip from storer.With the relative higher-energy (100pJ) that the long distance of driving (10mm) on the chip interconnect is associated is the non-scalability of distribution and the result that chip size increases.Fig. 3 is derived from Bill Dally, InternationalSymposium on High-Performance Computer Architecture (high-performance computer framework international symposium) in 2002.
If current uniprocessor chip framework and method for designing do not change, then power consumption that is associated with logic and memory function interconnection on the chip and stand-by period will become the principal element of the chip performance that causes being subjected to Power Limitation.In fact, chip architecture responds, and a plurality of, simple processor, distributed register file, dominance management local storage, more best enhancing floor plans that is provided with and other innovation have prevented to be interconnected on the chip power/performance limiting factor of taking as the leading factor.
By these new improved chip architecture and methods for designing, also always so mainly be owing to embed the logic and memory function to the restriction of chip performance.Yet these embed circuit and more and more are difficult to as above further describe the ground convergent-divergent, and quiescent dissipation begins chip operation is determined performance.
Even the static power in the cmos circuit also can occur under the situation that does not have switching.This is because because of relatively poor scaled devices threshold voltage and the mobile leakage current of operating voltage.Static power can only be by reducing voltage, preferably the voltage in the temporary transient obsolete circuit reduced to zero (selectively removing the voltage that is applied from these circuit) and be minimized.
The logical design technology that is called concurrent operations is used in the high-speed chip design usually.These technology are streamline and concurrency, wherein logic function are divided into the more small pieces (sub-piece) that are called level, and feasible the execution simultaneously because of many operations is improved instruction execution rate.Concurrent logical design technology has a detailed description in below with reference to document: H.B.Bakoglu, " Circuits, Interconnections, and Packaging for VLSI (circuit of VLSI, interconnection and encapsulation) ", Addison-Wesley publishes company limited, nineteen ninety 412-416 page or leaf; And David T.Wang, " Revisiting the FO4 Metric (heavily visiting FO4 tolerance) ".
An importance of concurrent logical operation is that finishing of previous instruction do not waited in the beginning of instruction.Like this, use all parts of hardware in each circulation, the handling capacity of optimum utilization utilogic and increase machine.Dependence between the instruction makes logical performance can not reach best possibility performance; Yet instruction is optimized and be can be used for that pipelining reaches performance faster by for example using.
For example, pipelining is used the random logic piece by register (being also referred to as register file, registers group, pipeline latch or latch) division (separation) of the operating speed that reaches much higher; Promptly be used to improve the streamline of carrying out speed.With the more small pieces that become level that are logically divided into about equally, and insert register (latch) group with interface maintenance nonce (logic state) in logic level.Then, the logical timer frequency is increased to the long delay of logic level and adds the level that the inverse of latch time-delay expense sum is directly proportional.Provide in the 338-349 page or leaf of example in the reference book of the above H.B.Bakoglu that further describes of logic level, register (monolock storage and dual latch design) and clock.Provide in the 349-355 page or leaf of example in the reference book of H.B.Bakoglu of register (latch) design.Design has increased the quantity of register and has reduced the logic level time-delay.As example, register (latch) quantity of using in IBM 750 PowerPC chips is about 10,000 registers.PowerPC design of future generation, IBM 970 uses about 300,000 registers.
Use the design of volatile register (latch)
Power consumption is an important consideration, should be it and logic function is set maximum performance limitations as above with reference to Fig. 1-3 usually with describing in detail.Current, logic state temporarily is stored in the volatile register latch.Yet, introducing non volatile register that each register has the special-purpose nanometer tube device makes logic state be preserved not applying under the voltage condition, i.e. zero-power in the part of integrated circuit (or all), so that reduction power consumption, also move sooner as required thereby make other logical block can consume more power, also have other advantage described below.
Except the feature performance benefit that random logic is divided into fritter more, also there is the test advantage.Logic testing requires each logic node is switched to " 1 " and " 0 " two kinds of logic states.Have such as a large amount of up to ten million or more than one hundred million chips and can not obtain Validity Test, unless with the level (piece) of logical subdivision Cheng Gengxiao.The littler logic level of being separated by latch makes the measurability of logic for example reach 98 to 99%.Also can be for test purpose with register interconnected in series as herein described.Apply test mode logic (test vector) and measure logical response with sign and rejecting defective chip, this is known in industry member.Below with reference to document description the design of logic measurability: H Fujiwara, " Logic Design and Design for Testability (logical design and design for Measurability) ", Cambridge, the Massachusetts, MET Press, 1985,238, the 256-259 page or leaf; And P.H.Bardel, W.H.McAnney and J.Savir, " Built-in Test for VLSI:Pseudorandom Techniques (built-in testing of VLSI: the pseudorandom technology) ", New York, New York, John Wiley ﹠amp; Sons, 1987, the 38-43 page or leaf.
Many different register file circuit designs also are possible (with reference to above Bakoglu).For example, clock control SYN register file-level circuit design can be used the main latch level circuit and the auxilliary latch, stage circuit of the non-overlapping clock of the CLK1 that has shown in Fig. 4 A and CLK2.Perhaps, clock control SYN register file-level circuit design can be used to be had shown in Fig. 4 B and the main latch level circuit and the auxilliary latch, stage circuit of the single clock of the CLK that is described further below (and complementary CLKb).
Fig. 4 A illustrates the prior art pipeline synchronization logic function 5 of using two non-overlapping clock CLK1 and CLK2, comprises the logic level of being separated by the register 7,12,18 (and unshowned other register) that the high speed operation of prior art is designed 10 and 14 (and unshowned other logic level).Exemplary register 12 is made of master (L1) latch 20 and auxilliary (L2) latch 25.Main (L1) latch 20 is made of register cell 1-n and assists (L2) latch 25 by unit 1 '-n ' formation.To constituting, register cell k and the k ' by correspondence constitutes register stage such as register stage 16 by the register cell of correspondence.Notice that logic level 10 and 14 can be constituted or can is that plate such as high-speed synchronous SRAM L1 high-speed cache carries high-speed cache by for example random logic level, this is very important.Master (L1) latch such as master (L1) latch 20 receives data, the data of catching and keeping being imported from last logic level 10 when being activated by clock CLK1.Such as auxilliary (L2) latch of auxilliary (L2) latch 25 master (L1) latch 20 reception information when being activated, and this information sent to next logic level 14, near the end of CLK2 clock round-robin, latch this information then from correspondence by clock CLK2.
Fig. 4 B illustrates the prior art pipeline synchronization logic function 40 of using single clock CLK, comprises the logic level of being separated by the register 45,55,65 (and unshowned other register) that the high speed operation of prior art is designed 50 and 60 (and unshowned other logic level).Exemplary register 55 is made of master (L1) latch 70 and auxilliary (L2) latch 75.Main (L1) latch 70 is made of register cell 1-n and assists (L2) latch 75 by unit 1 '-n ' formation.To constituting, register cell k and the k ' by correspondence constitutes register stage such as register stage 80 by the register cell of correspondence.Notice that logic level 50 and 60 can be constituted or can is that plate such as high-speed synchronous SRAM L1 high-speed cache carries high-speed cache by for example random logic level, this is very important.Master (L1) latch such as master (L1) latch 70 receives data from last logic level 50 during clock CLK the first half of cycling time, the data of catching and keeping being imported, and the section start of half is transferred to auxilliary (L2) latch with these data behind the clock round-robin.Such as auxilliary (L2) latch of auxilliary (L2) latch 75 at back half the section start of clock CLK cycling time from master (L1) the latch 70 reception information of correspondence, and these data are sent to next logic level 60, then clock CLK cycling time back half latch this data near finishing.
Such as the electrology characteristic of the prior art PC chip of the IBM 970 Power PC chips that in Apple computer and game station of Sony, use show operating speed in the high-speed synchronous logic chip that uses the non-overlapping clock design and dynamically, relation between the quiescent dissipation.IBM 970 chips are operated under 1.3V, under the 130nm technology node, use SOI CMOS technology to design, and the plate that the comprises 1MB plate that carries the synchronous SRAM high-speed cache of L1,4MB carry the synchronous SRAM high-speed cache of L2 and have the non-overlapping clock CLK1 that operates and the dual latch of CLK2 (similar with the method for the synchronous logic function 5 of Fig. 4 A) designs under about 3GHz clock frequency by copper wiring.
In the operation, under the clock circulation of about 340ps, main latch receives data with about 170ps from last logic level, catches (latching) these data and these data are ready to auxilliary latch.Auxilliary latch uses about 170ps to receive data from the main latch of correspondence, and this information is sent to next logic level, latchs this information then.
IBM 970 chips have dynamic (activity) power consumption of about 90W and 25W static state (standby) power consumption because of device leakage; Quiescent dissipation is about 28% of activity power consumption.Fig. 5 illustrates relative dynamic (activity) and static (standby) power of prior art IBM 970 PowerPC that are plotted in 130nm technology node place on prior art Fig. 1, Fig. 1 shows based on the relative dynamic of the expectation of cmos device convergent-divergent and static power, comprising the influence of the device leakage electric current that causes owing to the power supply convergent-divergent less than desired threshold voltage and correspondence to the increase of static power.The relative power consumption number of prior art IBM 970 PowerPC chips show the static power problem at least as Fig. 1 with the same important shown in 5, and along with more advanced technology node development, quiescent dissipation may become leading, unless can use framework and circuit design means to prevent that it from taking place.
Fig. 6 illustrates the prior art register file level circuit 500 corresponding to the register stage 80 shown in Fig. 4 B.The description of register file design and operation can be found in below with reference to document: H.B.Bakoglu, " Circuits; Interconnections; and Packaging for VLSI (circuit of VLSI, interconnection and encapsulation) ", Addison-Wesley publishes company limited, nineteen ninety, the 349-356 page or leaf.Prior art register file level circuit 500 comprises main latch level circuit 505 and auxilliary latch, stage circuit 510, all with (clock control) pattern operation synchronously and all be volatibility.That is, if lose or remove power then the data of being stored will be lost.Main latch level circuit 505 has input node 515 and output node 520.Auxilliary latch, stage circuit 510 has the input node 520 and the output node 525 of the output node that also is main latch level circuit 505.Node 520 also is the memory node of auxilliary latch, stage circuit 510.
The input node 515 receiving inputted signal V of main latch level circuit 505 INAnd the transmission gate that is connected in node 535 530 of driving CMOS, and drive first memory node 535 that forms by cross-couplings CMOS phase inverter 545 and 550.Input signal V INCorresponding to V from the logic among Fig. 4 B 50 INCmos transmission gate 530 uses NMOS and PMOS device for example to replace only NMOS transmission gate, comes all changing between power level and the ground voltage level by the pressure drop of abatement device threshold value to guarantee logical one and logical zero two states.Clock CLK 540 and complementary clock CLKb 540 ' are used for by cmos transmission gate 530 being placed ON or OFF enable or block the input signal V that imports on the node 515 INDrive node 535 is determined the logical storage state of cross-linked CMOS phase inverter 545 and 550 thus.Notice that all phase inverters all are the CMOS phase inverters, unless otherwise noted.The CMOS phase inverter comprises the PMOS pull-up device that is connected in power supply and the NMOS pull-down of ground connection, and as below with reference to operating described in the document: H.B.Bakoglu, " Circuits; Interconnections; and Packaging for VLSI (circuit of VLSI, interconnection and encapsulation) ", Addison-Wesley publishes company limited, nineteen ninety, 152 pages.Cross coupling inverter 545 and 550 drives the memory node 555 that is connected in cmos transmission gate 560.Clock CLK and complementary clock CLKb are used for by cmos transmission gate 560 being placed ON and OFF enable or block the output node 520 that logic states node 555 drives main latch memory circuit 505.
The input node 520 of auxilliary latch stores circuit 510 also is the output node of main latch level circuit 505 simultaneously, drives phase inverter 570.The output of phase inverter 570 is exported V on output node 525 OUT, and the input of driving phase inverter 575.Output signal V OUTCorresponding to the V among Fig. 4 B OUT, it is driven into logic 60 with input.The output 580 of phase inverter 575 is connected in cmos transmission gate 585.Clock CLK and complementary clock CLKb are used to enable or block the appearance of backfeed loop, this loop when enabling with phase inverter 570 and 575 cross-couplings.When the storage data, cmos transmission gate 585 is in ON and phase inverter 570 and 575 forms the cross-couplings memory device that has as the node 520 of memory node.When cmos transmission gate 585 was in OFF, phase inverter 570 and 575 was not by cross-couplings and do not form memory device.
In operation, the clock scheme shown in Fig. 4 B is used for the operation of the design of the dual latch shown in Fig. 4 B synchronously 40.Register stage 80 comprises the subclass of the subclass of unit k, master (L1) latch 70 and unit k ', auxilliary (L2) latch 75.
Master (L1) latch such as master (L1) latch 70 receives data from last logic level 50 during clock CLK the first half of cycling time, the data of catching and keeping being imported, and the section start of half arrives this information transfer such as auxilliary (L2) latch of assisting (L2) latch 75 behind the clock round-robin.Such as auxilliary (L2) latch of auxilliary (L2) latch 75 back half section start between clock cycles from master (L1) the latch 70 reception information of correspondence, and this information sent to next logic level 60, then between clock cycles back half latch this information before finishing.If clock stops during clock round-robin the first half, then lead (L1) latch 70 and keep (storage) logic state or data.If half stops clock behind the clock round-robin, then auxilliary (L2) latch keeps (or storage) logic state or data.If remove or lose power, then logic state or data are also lost.
Fig. 6 illustrates corresponding to the prior art main latch level circuit 505 of the unit k of the register file level 80 of master (L1) latch 70 shown in Fig. 4 B and corresponding to the auxilliary latch, stage circuit 510 of the unit k ' of the register file level 80 of auxilliary (L2) latch 75 shown in Fig. 4 B.
In operation, at clock round-robin section start, clock CLK 540 keeps low-voltage from high voltage to the low-voltage transformation and the circulation of the first half clock, and complementary clock CLKb 540 ' remains on high voltage from low-voltage to the high voltage transformation and the circulation of the first half clock.CMOS transmission apparatus 530 is connected, thereby will import the voltage V of node 515 INBe coupled to memory node 535.CMOS transmission apparatus 560 turn-offs and the output of main latch level circuit 505 and the input node 520 of auxilliary latch, stage circuit 510 is isolated.CMOS transmission apparatus 585 also turn-offs, thereby the feedback path between the input 520 of the input 580 of disconnection phase inverter 575 and phase inverter 570 makes node 520 not be re-used as memory node.Voltage V INCan transform to magnitude of voltage in any moment before clock circulates the first half end, thereby the logic state of storing correspondence before the clock conversion for cross coupling inverter 545 and 550 half section start after clock circulates provides sufficient excess time corresponding to correct logic state.
Clock CLK 540 half section start behind the clock round-robin transforms to high voltage and remains on high voltage from low-voltage, and complementary clock CLKb 540 ' changes to low-voltage and remain on low-voltage half behind the clock round-robin from high-voltage variable.CMOS transmission apparatus 530 turn-offs, thereby makes the voltage V of input node 515 INFrom memory node 535 decouplings, wherein memory node remains on the input voltage V corresponding to clock round-robin the first half end INState.560 connections of CMOS transmission apparatus and the input 520 that the state transitions of memory node 555 is arrived phase inverter 570, these inverter drive output node 525 output voltage V OUT, and the input of driving phase inverter 575.CMOS transmission apparatus 585 is connected, and this makes the output 180 of phase inverter 575 can drive the input of phase inverter 570 and the state of the auxilliary latch state levels circuit 510 of storage finishes up to clock round-robin subordinate phase.
In people's such as Bertin U.S. Patent No. 5,986,962, volatibility low-power shadow latch keeps register file logic state or data, makes and can turn-off volatibility high performance register file power to reduce quiescent dissipation, as mentioned above.Yet volatibility low-power shadow latch must keep connecting, therefore consumed power still in logic states or the data in standby mode, if because storer be volatibility and lose power information and will lose.In addition, volatibility low-power consumption shadow latch uses lower bias current to minimize static power and therefore very responsive to disturbance, and wherein logic state of being stored or data may lose or damage.This can take place because of switching noise, α particle or other radiation interference etc. on power supply noise, the chip.And shadow latch needs extra chip area, and this has increased chip size greatly.
Fig. 7 illustrates the prior art subsystem 700 with normal operation mode and two kinds of operator schemes of low-power logic state (or data) maintenance pattern.In normal operation mode, use the high performance system latch to carry out volatibility high-performance and corresponding high active power logical operation.In low-power logic state (or data) maintenance pattern, logic state or data are remained in the low-power shadow latch.Volatibility represents if power loss or be removed then logic state or data message can be lost.
Fig. 7 illustrates by special-purpose coupled circuit 730,730 ' and 730 " be coupled in associated volatile shadow latch circuit 720,720 ' and 720 " a plurality of prior art volatibility system lock storages 710,710 ' and 710 ".The system lock storage also can be described as for example latch circuit or register file or register file circuit.System or latch circuit can be from the V from power source P that is provided by switch S 1 DDPower supply.The same V from power source P of shadow latch circuit from providing by switch S 2 MSPower supply.Yet switch S 1 can obtain power from different sources with S2.Detecting device D is used to detect and can perhaps detects by the monitoring operation code stream ST that calls lower powered code as shown in Figure 7 from the low-power request of low-power interrupt pin (not shown).When detecting device D detected the operational code (or interrupt pin) of calling low-power or standby mode, detecting device D switched on to its output, thereby obtains two kinds of effects.A kind of effect is to make the switch S 1 can be from voltage source V MSPower is provided.Second kind of effect is activator switch S2 after the delay between detecting device D conversion and switch S 2 activation, so that offer the V of latch circuit DDPower is invalid.Introduce time-delay to guarantee when latch circuit cuts off the power supply, enabling shadow latch 720,720 ' and 720 ".Volatibility shadow latch 720,720 ' and 720 " remain on voltage V MSFollowing energising finishes up to reducing power mode, and only is transferred to volatibility system lock storage 710,710 ' and 710 in logic state of being stored or data " just can cut off the power supply afterwards.
General introduction
The invention provides a kind of non-volatile shadow latch that uses nanotube switch.
On the one hand, Nonvolatile memery unit comprises the volatile memory device of storing the counterlogic state in response to electro photoluminescence, thereby and is coupled in this volatile memory device received and stored the counterlogic state in response to electro photoluminescence shadow memory device.This shadow memory device comprises the Nonvolatile nanotube switch, the corresponding states of wherein said nanotube switch storage shade device.On the other hand, the Nonvolatile nanotube switch comprises the two-terminal nanotube switch.
On the other hand, Nonvolatile memery unit also comprises coupled circuit, this circuit can be transferred to the shadow memory device with the logic state of volatile memory device response in response to electro photoluminescence, and can the logic state of shadow memory device be transferred to volatile memory device in response to electro photoluminescence.
On the other hand, Nonvolatile memery unit also comprises coupled circuit, this coupled circuit comprises: programmed circuit, power path is provided between volatile memory device and shadow memory device and in response to programming signal with the counterlogic state transitions of volatile memory device to the shadow memory device; And restoring circuit, power path is provided between shadow memory device and volatile memory device and the logic state of shadow memory device is transferred to volatile memory device in response to restoring signal.
On the other hand, Nonvolatile memery unit also comprises coupled circuit, and this coupled circuit comprises with shadow memory device electric connection and wipes the erasing circuit of the logic state of shadow memory device in response to erase signal.
On the other hand, the output node electric connection of the first terminal of nanotube switch and volatile memory device, and second terminal of nanotube switch and program/erase/read line electric connection.
On the other hand, Nonvolatile memery unit comprises the controller that also can monitor the power level of volatile memory device with the volatile memory device electric connection.On the other hand, this controller can apply electro photoluminescence to the shadow memory device in response to the power loss of volatile memory device.This electro photoluminescence is transferred to the shadow memory device with the logic state of volatile memory device.
On the other hand, this controller can increase in response to the power of volatile memory device and apply electro photoluminescence to the shadow memory device.This electro photoluminescence is transferred to volatile memory device with the logic state of shadow memory device.
On the other hand, by the state of non-volatile nanotube switch storage resistance characterization by the power path in the nanotube switch.
On the other hand, Nonvolatile memery unit comprises the main latch level that can receive voltage and this voltage be outputed to volatile memory device.This voltage is corresponding to logic state.On the other hand, the random logic level provides the voltage corresponding to logic state.On the other hand, plate carries high-speed cache voltage corresponding to logic state is provided.
The accompanying drawing summary
In the accompanying drawings:
Fig. 1 is that the prior art of the dynamic and static normalization power consumption of chip and technology node, minimum gate length and the relation in time is represented;
Fig. 2 is that the prior art of the relative energy efficient of various logic method for designing is represented;
Fig. 3 is that the prior art of the relative energy efficient of various logic operation is represented;
Fig. 4 A is to use the advocate peace prior art synoptic diagram of clock control logic function of auxilliary latch of two non-overlapping clocks and volatibility;
Fig. 4 B is to use the advocate peace prior art synoptic diagram of clock control logic function of auxilliary latch of a clock and volatibility;
Fig. 5 is that the prior art in the normalization power consumption of IBM 970 logic chips of 130nm technology node design that is superimposed upon on Fig. 1 is represented;
Fig. 6 is the prior art synoptic diagram of register file level circuit;
Fig. 7 is coupled in the system lock storage of low-power shadow latch and the prior art synoptic diagram of related power supply by coupled circuit;
Fig. 8 A is that the coupled circuit that passes through of some embodiment according to the present invention is coupled in the system lock storage of Nonvolatile nanotube switch and the synoptic diagram of related power supply;
Fig. 8 B is the system lock storage that is coupled directly to the Nonvolatile nanotube switch of some embodiment and the synoptic diagram of related power supply according to the present invention;
Fig. 9 A and 9B are the cross sectional view of some embodiment of non-volatile two-terminal nanotube switch;
Figure 10 is the synoptic diagram of clock control logic function, volatibility main latch and non-volatile auxilliary latch of a clock of use of some embodiment according to the present invention;
Figure 11 A is the synoptic diagram of the non volatile register file-level that comprises coupled circuit and Nonvolatile nanotube switch of some embodiment according to the present invention;
Figure 11 B is the synoptic diagram of the non volatile register file-level that comprises the Nonvolatile nanotube switch of some embodiment according to the present invention;
Figure 12 A is the circuit diagram of the non volatile register file-level circuit that comprises coupled circuit and Nonvolatile nanotube memory element of some embodiment according to the present invention;
Figure 12 B is the operation waveform diagrammatic sketch of the conversion that is energized to outage of some embodiment according to the present invention, and wherein the logic state (or data) of the auxilliary latch status circuit of volatibility is transferred to the Nonvolatile nanotube switch, subsequently outage;
Figure 12 C is the operation waveform diagrammatic sketch of the outage of some embodiment according to the present invention to the conversion of energising, the logic state (or data) that wherein is stored on the Nonvolatile nanotube switch is transferred to the auxilliary latch status circuit of volatibility, is normal clock control operation subsequently;
Figure 13 A is the circuit diagram of the non volatile register file-level circuit that comprises coupled circuit and Nonvolatile nanotube memory element of some embodiment according to the present invention;
Figure 13 B is the operation waveform diagrammatic sketch of the conversion that is energized to outage of some embodiment according to the present invention, and wherein the logic state (or data) of the auxilliary latch status circuit of volatibility is transferred to the Nonvolatile nanotube switch, subsequently outage;
Figure 13 C is the operation waveform diagrammatic sketch of the outage of some embodiment according to the present invention to the conversion of energising, the logic state (or data) that wherein is stored on the Nonvolatile nanotube switch is transferred to the auxilliary latch status circuit of volatibility, is normal clock control operation subsequently;
Figure 14 A is the circuit diagram of the non volatile register file-level circuit that comprises the Nonvolatile nanotube memory element of some embodiment according to the present invention;
Figure 14 B is the circuit diagram that forms the phase inverter of a non volatile register file-level circuit part, and wherein this inverter controlling comprises that the state of common points of a terminal of phase inverter output and Nonvolatile nanotube switch and phase inverter input are exported with non volatile register file-level circuit and is in same voltage;
Figure 14 C is the operation waveform diagrammatic sketch of the conversion that is energized to outage of some embodiment according to the present invention, and wherein the logic state (or data) of the auxilliary latch status circuit of volatibility is transferred to the Nonvolatile nanotube switch, subsequently outage;
Figure 14 C is the operation waveform diagrammatic sketch of the outage of some embodiment according to the present invention to the conversion of energising, the logic state (or data) that wherein is stored on the Nonvolatile nanotube switch is transferred to the auxilliary latch status circuit of volatibility, is normal clock control operation subsequently;
Figure 15 is the prior art synoptic diagram of high-voltage power supply and decoding circuit;
Figure 16 is the high-tension prior art synoptic diagram with the semiconductor technology compatibility; And
Figure 17 is the synoptic diagram of the compartment system of the high voltage decode of some embodiment according to the present invention and Nonvolatile nanotube switch.
Describe in detail
Better embodiment of the present invention provides the non-volatile shadow that comprises nanotube switch element.Generally speaking, the non-volatile shadow element is coupled in the same volatile latch of the corresponding row that is also referred to as the register file latch.In some embodiments, the shade element is coupled in corresponding system lock storage by coupled circuit.In other embodiments, the shade element is coupled directly to corresponding system lock storage.Generally speaking, when the outage of system lock storage, the state of this latch is transferred to the shade element.Correspondingly, can cut off the power supply or one or more parts of chip are selectively cut off the power supply, and the information in each system lock storage will be transferred to corresponding shade element entire chip.Then, when latch is recovered energising, the state that is stored in the shade element will be transferred back corresponding system lock storage.This can make the operation of preserving critical data and recover the chip subfunction when recovering energising in outage.
In better embodiment, can use with the good integrated technology of existing CMOS technology and make the Nonvolatile nanotube switch.In better embodiment, the nanotube switch in the non-volatile shadow element comprises the nanotube articles with each electric connection of two conducting terminals.This nanotube articles comprises at least one nanotube.By at least one applies suitable electro photoluminescence in conducting terminal, the resistance Reprogrammable ground of the nanotube articles between two conducting terminals is changing between high electrical resistance and the relatively low resistance relatively.The relative resistance of nanotube articles has characterized the logic state that is stored in the non-volatile shadow element.This state is non-volatile, allows logic state (indefinitely) under zero-power to preserve.Though use nanotube switch in said embodiment, generally speaking, can also use the nanotube switch of any other type with both-end.
Use the design of non volatile register file
That the Nonvolatile nanotube switch can be used for is non-volatile (keeping information when outage) and can bear embodiment such as the shadow memory spare of the rugged surroundings of high temperature and high radiation level.In addition, the Nonvolatile nanotube switch can be easily integrated with any CMOS technology such as matrix CMOS or SOI CMOS, and need less relatively additional chip area to realize.Below further describe and in the design of the embodiment of non volatile register file, use the Nonvolatile nanotube switch.The non volatile register file has two kinds of operator schemes, i.e. normal operation mode and zero-power logic state (or data) maintenance pattern.
Fig. 8 A illustrates has the normal operation mode and the embodiment of non-volatile shadow latch subsystem 800 of two kinds of operator schemes of the non-volatile maintenance pattern of zero energy logic state (or data) of outage wherein.In normal operation mode, use high-performance latch to carry out the high active power mode logical operation of volatibility high-performance.In the non-volatile maintenance pattern of zero energy logic state (or data), with logic state or data storage in can bearing and outage such as the Nonvolatile nanotube switch of the rugged surroundings of high temperature and high radiation level.
Fig. 8 A illustrates by special-purpose coupled circuit 830,830 ' and 830 " be coupled in associated non-volatile nanotube switch 820,820 ' and 820 " be also referred to as register file latch 810,810 ' and 810 " a plurality of latchs.The register file latch is by power source 870 power supply, wherein the V that provides of switch 850 DDFrom power supply 855.The Nonvolatile nanotube switch is by power source 870 power supply, wherein erasing-programming/recovery pulse V of providing of switch 840 EPRFrom same power supply 855. Switch 840 and 850 needn't be subjected to from same power supply 855.Erasing-programming/recovery pulse V EPRCan be to put on Nonvolatile nanotube switch 820,820 ' and 820 " so that with non-volatile pattern storage status latch 810,810 ' and 810 " one or several pulses.Power controller 860 monitor power switches 840 and 850 switching are to guarantee having time enough that logic state or data are transferred to the Nonvolatile nanotube switch from the register file latch.At this moment, power supply V DDBe de-energized and erasing-programming/recovery pulse V EPRBe de-energized, make logic state or data under the zero-power state, still be stored in Nonvolatile nanotube switch 820,820 ' and 820 " in.
Fig. 8 B illustrates has normal operation mode and another embodiment of non-volatile shadow latch subsystem 800 ' of two kinds of operator schemes of the non-volatile maintenance pattern of zero energy logic state (or data) of outage wherein.In normal operation mode, use high-performance latch to carry out the high active power mode logical operation of volatibility high-performance.In the non-volatile maintenance pattern of zero energy logic state (or data), with logic state or data storage in can bearing and outage such as the Nonvolatile nanotube switch of the rugged surroundings of high temperature and high radiation level.
Fig. 8 B illustrates and is coupled directly to associated non-volatile nanotube switch 821,821 ' and 821 " be also referred to as register file latch 811,811 ' and 811 " a plurality of latchs.The register file latch is by power source 871 power supply, wherein the V that provides of switch 851 DDFrom power supply 856.The Nonvolatile nanotube switch is by power source 871 power supply, wherein erasing-programming/recovery pulse V of providing of switch 841 EPRFrom same power supply 856. Switch 841 and 851 needn't be subjected to from same power supply 856.Erasing-programming/recovery pulse V EPRCan be to put on Nonvolatile nanotube switch 821,821 ' and 821 " so that with non-volatile pattern storage status latch 811,811 ' and 811 " one or several pulses.Power controller 861 monitor power switches 841 and 851 switching are to guarantee having time enough that logic state or data are transferred to the Nonvolatile nanotube switch from the register file latch.At this moment, power supply V DDBe de-energized and erasing-programming/recovery pulse V EPRBe de-energized, make logic state or data under the zero-power state, still be stored in Nonvolatile nanotube switch 821,821 ' and 821 " in.
The Nonvolatile nanotube switch
The embodiment that can be included in the non-volatile two-terminal nanotube switch in the described shadow latch has description submitting on the same day with the application and have among the U.S. Patent application No. (waiting to deliver) that is entitled as " Two-Terminal Nanotube Devices And SystemsAnd Methods Of Making Same (two-terminal nanotube devices and system and preparation method thereof) " of commonly-assigned us, and the content of this application integral body by reference is incorporated into this.The relational structure that uses this switch and electrology characteristic, method for making have been described and with switch and the integrated method of existing semiconductor technology.
Fig. 9 A illustrates the cross sectional view of non-volatile 2-terminal nanotube switch (2-TNS) 10.Nanotube element 25 is arranged on the substrate 35 that comprises insulator layer 30.Nanotube element 25 is overlapping at least in part with two terminals such as conducting element 15 and 20 that directly deposit on the nanotube element 25.In this embodiment, before or after conducting element 15 and/or 20 depositions, in the zone of definition nanotube element 25 is carried out graphically.
Conducting element 15 contacts with stimulation circuit 50 with 20.At least one stimulates in 50 pairs of conducting elements 15 of stimulation circuit and 20, and this has changed the state of switch 10.Particularly, nanotube element 25 responds this stimulation by the resistance that changes the switch 10 between the conducting element 15 and 20; The relative value of resistance is corresponding to the state of switch.For example, if stimulation circuit 50 applies first electro photoluminescence, this stimulation can be for example to cross over conducting element 15 and 20 relative high voltage and electric current, and then nanotube element 25 responds by the device resistance between conducting element 15 and 20 is become relative high electrical resistance.This is corresponding to " wiping " or " shutoff " state of device, and wherein the conductive phase between the conducting element 15 and 20 is to relatively poor.Under this state, the impedance between the element 15 and 20 is also relative higher.For example, if stimulation circuit 50 applies second electro photoluminescence, this stimulation can be relatively low voltage or an electric current of for example crossing over conducting element 15 and 20, and then nanotube element 25 responds by the switch resistance between conducting element 15 and 20 is become relatively low resistance.This is corresponding to " programming " or " connection " state of device, wherein between the conducting element 15 and 20 conductive phase to better, or even nearly ohmic properties.Under this state, the impedance between the element 15 and 20 is also relatively low." wipe " electric current related with relative higher " wiping " voltage can be greater than or less than and related " programming " electric current of relatively low " programming " voltage." wipe " and " programming " electric current usually in Na An or microampere scope, and select to determine by the geometry of non-volatile two-terminal nanotube switch and material.Generally speaking, resistance between first and second conducting elements of device and impedance phase be about the state of device, and can determine by the electrology characteristic of measuring switch.
Conducting element 15 and 20 is preferably made by conductive material, and depends on the desired properties feature of switch 10 and identical or different.For example, conducting element 15 and 20 can be by such as metal and other suitable metal of Ru, Ti, Cr, Al, Au, Pd, Ni, W, Cu, Mo, Ag, In, Ir, Pb, Sn and constitute.Can use metal alloy, comprise other suitable conductor of CNT self (for example single wall, Duo Bi and/or double-walled) or such as RuN, RuO, TiN, TaN, CoSi such as TiAu, TiCu, TiPd, PbIn and TiW xAnd TiSi xConductive nitride, oxide or silicide.Also can use the conductor or the semiconductor material of other type.Insulator 30 is preferably the suitable insulation material, such as SiO 2, SiN, Al 2O 3, BeO, GaAs, polyimide or other suitable material.The conduction that can use in 2-TNS 10 and the example of insulating material have a detailed description in the U.S. Patent application No. (waiting to deliver) that is entitled as " Two-Terminal Nanotube Devices And Systems And Methods OfMaking Same (two-terminal nanotube devices and system and preparation method thereof) " that submits on the same day with the application.
In some embodiments, nanotube element (goods) the 25th, the works (being also referred to as nanostructure) of the carbon nano-tube of tangling.But the nanotube random orientation in the nanostructure, perhaps its orientation can not be subject to the orientation of nanotube element 25.The nanotube element is complied with the surface usually basically; In some embodiments, the one or more terminals in the two-terminal nanotube switch have vertical orientated surface, and the nanotube element is complied with at least a portion on vertical orientated surface basically.In some embodiments, nanotube element or works are porous, but and at least some holes in the material filled with nanotubes element 25 of conducting element 15 and/or 20.In some embodiments, nanotube element 25 comprises single-walled nanotube (SWNT) and/or many walls nanotube (MWNT) and/or double-walled nanotubes (DWNT).In some embodiments, nanotube element 25 comprises one or more nanotube bundles.Usually, nanotube element 25 comprises at least one nanotube.The method of making nanotube element and nanostructure is known and description is arranged in following document: U.S. Patent No. 6,784,028,6,835,591,6,574,130,6,643,165,6,706,402,6,919,592,6,911,682 and 6,924,538; U.S. Patent Publication No.2005-0062035,2005-0035367,2005-0036365 and 2004-0181630; And U.S. Patent application No.10/341005,10/341055,10/341054,10/341130, the content of these documents integral body by reference is incorporated into this (hereinafter and above being called " references of institute's combination ").Some embodiment that can be used for the nanotube element of 2-TNS10 has a detailed description in the U.S. Patent application No. (waiting to deliver) that is entitled as " Two-TerminalNanotube Devices And Systems And Methods Of Making Same (two-terminal nanotube devices and system and preparation method thereof) " that submits on the same day with the application.
Usually, high resistance and low-resistance value preferably separate at least one magnitude.In some better embodiment, " shutoff " state has than the high at least 10 times resistance of " connection " state.In some better embodiment, " shutoff " state has than the high at least 10 times impedance of " connection " state.In some embodiments, " programming " or " connection " state is by common resistance (R in 100 Ω to 1M Ω scopes between conducting element 15 and 20 ON) characterize.In some embodiments, " wipe " or " shutoff " state by the usually resistance (R in 10M Ω to 10G Ω or higher scope between conducting element 15 and 20 OFF) characterize.Two states is non-volatile, and promptly they do not change, and at least one applies another suitable electro photoluminescence in conducting element 15 and 20 up to stimulation circuit 50, and their hold modes, even remove power from this circuit.Stimulation circuit also can use non-destructive read operation (NDRO) to determine the state of 2-TNS 10.For example, stimulation circuit 50 can be crossed over conducting element 15 and 20 and apply lower measuring voltage, and measures the resistance R between the conducting element.This resistance can by measure between the conducting element 15 and 20 electric current and thus calculated resistance R measure.This makes it can not change the state of device a little less than stimulating enough.By measurement pass conducting element 15 and 20 (between) the bit line precharge capacitor discharge come another example of the method for determining unit state in the U.S. Patent application No. (waiting to deliver) that is entitled as " Memory Arrays UsingNanotube Articles With Reprogrammable Resistance (use has the memory array of the nanotube articles of re-programmable resistance) ", description to be arranged.Example electro photoluminescence of " programming " of some embodiment of two-terminal nanotube switch and " wiping " state and resistance and example " read " to stimulate in the U.S. Patent application No. (waiting to deliver) that is entitled as " Two-Terminal Nanotube DevicesAnd SystemsAnd Methods Of Making Same (two-terminal nanotube devices and system and preparation method thereof) " that submits on the same day with the application and have a detailed description.
In some embodiments, calorifics and/or electricity engineering design, be that calorifics and/or electricity management (design) can be used for strengthening the two-terminal nanotube switch performances, as described in the U.S. Patent application No. (waiting to deliver) that is entitled as " Two-TerminalNanotube Devices And Systems And Methods Of Making Same (two-terminal nanotube devices and system and preparation method thereof) " that proposes on the same day with the application.Fig. 9 B illustrates the cross-sectional view of non-volatile two-terminal nanotube switch (2-NTS) 10 ', and wherein calorifics and/or electricity engineering design or management (design) are by overlapping realization the between restriction nanotube element 25 ' and the conducting element 20 '.Nanotube element 25 ' is arranged on the substrate 35 ' that comprises insulator layer 30 '.Nanotube element 25 ' is arranged to the geometric relationship of appointment with overlapping such as predetermined extent such as directly being deposited in conducting element 15 ' on the nanotube element 25 ' and 20 ' the terminal at least a portion of at least one.
The passivation of NRAM device can be used for making things convenient for device in air, under the room temperature operation and combine as protective seam with stacked material on the NRAM top device.The operation of the NRAM device of passivation is not carried out to remove the water that is absorbed from the nanotube that exposes in such as the inert gas environment of argon, nitrogen or helium or under (the being higher than 125 ℃) sample temperature that raises usually.Therefore, the requirement of passivating film is normally dual.At first, passivation should form effective moist barrier, prevents that nanotube is exposed in the aqueous vapor.Secondly, passivating film should not disturb with the switching mechanism of NRAM device.
A kind of method of passivation relates to the chamber made from the switch region that sealing is provided around the NRAM device.All be made into around independent device (device level passivation) with around two kinds of chambeies of the whole tube core (die-level passivation) of 22 devices.Yet the technological process of making is very complicated, needs at least two additional lithographic steps and at least two additional etching steps.
The another kind of method of passivation relates to the suitable dielectric layer of deposition on the NRAM device.The example of this method is to use the spin coating polyvinylidene fluoride (PVDF) that directly contacts with the NRAM device.PVDF is patterned into the sheet (cover individual devices single) of die-level (at whole tube core active region) or device level.Then, use suitable assisted dielectric passivating film to seal PVDF and the passivation of NRAM being operated robust is provided such as aluminium oxide or silicon dioxide.The NRAM operation is considered to the PVDF that the meeting thermal decomposition covers, and therefore needs auxiliary passivating film seal this device.Because the die-level passivation is generally～sheet of 100 square microns, this exploded can cause the breaking of auxiliary passivation, NRAM device be exposed in the air with and subsequently inefficacy.For fear of this inefficacy of auxiliary passivating film, through the device of die-level passivation by with coming pulsed modulation this device and electricity " wear out " with the 0.5V step-length to the 500ns pulse of 8V from 4V usually.This is regarded as controllably decomposed P VDF and prevents that the auxiliary passivating film that covers from breaking.After burin-in process, but the NRAM device normal running of die-level passivation.It is this aging to use device level PVDF coating and auxiliary passivating film to come the device of passivation not need on handling, and can directly at room temperature operate in the air under operating voltage.By the device level passivation, PVDF is patterned to the shape of accurate CNT works, common 0.5 micron wide long with the 1-2 micron.This little sheet can be regarded as and can decompose under the situation that auxiliary passivating film was lost efficacy.For given defect concentration in the auxiliary passivation, compare with bigger, die-level sheet, on average, might on the littler area coverage of device level PVDF sheet, there be defective.
In this embodiment, in the zone that before or after the deposition of conducting element 15 ' and/or 20 ', defines nanotube element 25 ' is carried out graphically.Conducting element 15 ' is overlapping with a whole stub area of nanotube element 25 ', forms nearly ohmic properties contact.At a relative end of nanotube element 25 ', in overlapping region 45 ', conducting element 20 ' and nanotube element 25 ' the overlapping controlled overlap length 40 '.Controlled overlap length can be for example in the 1-150nm scope, perhaps in the 15-50nm scope.In a better embodiment, controlled overlap length 40 ' is about 45nm.The material of making switch 10 ' is described similar to the switch 10 of above Fig. 8 A with method.
Switch 10 and 10 ' shown in Fig. 9 A and the 9B is intended to the illustrated examples as the two-terminal nanotube switch of the non-volatile shadow latch that can be used for using nanotube switch.Other embodiment that can be used for the 2-TNS of non-volatile shadow latch has a detailed description submitting on the same day with the application and have among the U.S. Patent application No. (waiting to deliver) that is entitled as " Two-TerminalNanotube Devices And Systems And Methods Of Making Same (two-terminal nanotube devices and system and preparation method thereof) " of commonly-assigned us, and the content of this application integral body by reference is incorporated into this.
System with the non-volatile shadow latch that uses nanotube switch
Figure 10 illustrates the system of use based on the non volatile register file latch of reference Fig. 8 A and the described principle of operation of 8B.Non volatile register file latch and logical architecture 900 comprise volatibility master (L1) latch corresponding to the volatibility master among Fig. 4 B (L1) latch; Non-volatile auxilliary (L2) latch; Logic 950 corresponding to logic 50; And corresponding to the logic 960 of logic 60 among Fig. 4 B.
Figure 10 illustrates the pipeline synchronization logical architecture 900 that comprises the logic level of being separated by non volatile register file latch 945,955,965 (and unshowned other non volatile register file latch) 950 and 960 (and unshowned other logic level), wherein non volatile register file latch be the prior art high speed operation and in odd jobs under the moving and zero quiescent dissipation situation in power down register file latch non-volatile logic state or data storage design.Exemplary register 955 is made of volatibility master (L1) latch 970 and non-volatile auxilliary (L2) latch 975.Volatibility master (L1) latch 970 is made of volatile register unit 1-n and non-volatile auxilliary (L2) latch 975 is made of non-volatile cell 1 '-n '.To constituting, volatile register unit k and the non volatile register unit k ' by correspondence constitutes the non volatile register level such as non volatile register level 980 by the register cell of correspondence.Notice that logic level 950 and 960 can be constituted or can is that plate such as high-speed synchronous SRAM L1 high-speed cache carries high-speed cache by for example random logic level, this is very important.Volatibility master (L1) latch such as volatibility master (L1) latch 970 receives data from last logic level 950 during the first half between clock cycles, catch and keep this data, and behind the clock round-robin half section start with this information transfer to non-volatile auxilliary (L2) latch.Such as non-volatile auxilliary (L2) latch of non-volatile auxilliary (L2) latch 975 back half section start between clock cycles from master (L1) the latch 970 reception information of correspondence, and this information sent to next logic level 960, then between clock cycles back half latch this information near finishing.
Non-volatile auxilliary (L2) latch high-speed chip operating period as auxilliary (L2) latch operation of volatibility.If power reduction, then after data had been latched in non-volatile auxilliary (L2) latch, clock CLK was stopping during half behind the clock round-robin.In one embodiment, the logic state of auxilliary (L2) latch of volatibility is by corresponding to the special-purpose coupled circuit shown in Fig. 8 A 830,830 ' and 830 " special-purpose coupled circuit transfer to corresponding to switch 820,820 ' and 820 " the Nonvolatile nanotube switch, below further describe.
In another embodiment, the logic state of non-volatile auxilliary (L2) latch is directly transferred to corresponding to switch shown in Fig. 8 B 821,821 ' and 821 " the Nonvolatile nanotube switch, below further describe.
Figure 11 A is the block diagram 1000 of the non volatile register file-level 980 shown in Figure 10, and it comprises that the logic state with the auxilliary latch of volatibility is delivered to the special-purpose coupled circuit of Nonvolatile nanotube switch.Non volatile register file-level 1005 is corresponding to non volatile register file-level 980 shown in Figure 10.The volatile cells k of non volatile register file-level 980 shown in Figure 10 is corresponding to having an input V shown in Figure 11 A INVolatibility main latch level 1010.The non-volatile cell k ' of non volatile register file-level 980 shown in Figure 10 comprises having an output V shown in Figure 11 A OUTThe auxilliary latch, stage 1015 of volatibility, Nonvolatile nanotube switch 1025, coupled circuit 1020 and corresponding interconnection.Non volatile register file-level 1005 has two operator schemes, the non-volatile maintenance pattern of zero energy logic state (or data) of normal operation mode and outage.
At normal operation mode, volatibility main latch level 1010 receives input voltage V IN, drive the auxilliary latch, stage 1015 of volatibility, by clock control (following further illustrate) and V from providing by power source 1045 DDPower supply.
The auxilliary latch, stage 1015 of volatibility receives input, output voltage V is provided from the output of volatibility main latch 1010 OUT, by clock control (following further illustrate) and V from providing by power source 1045 DDPower supply.The auxilliary latch, stage 1015 of volatibility is coupled in Nonvolatile nanotube switch 1025 by coupled circuit 1020.
From normal operation mode during the non-volatile maintenance mode conversion of zero energy, perhaps from the non-volatile maintenance pattern of zero energy during the normal operation mode conversion, by 1030 V from providing by power source 1045 are provided EPRTo 1025 power supplies of Nonvolatile nanotube switch.Nonvolatile nanotube switch 1025 is connected in coupled circuit 1020 by being electrically connected 1035.
Except to the electrical connection 1035 of Nonvolatile nanotube switch 1025, coupled circuit 1020 also is connected in the auxilliary latch, stage 1015 of volatibility by being electrically connected 1040.The controller (not shown) to the coupled circuit shown in Figure 11 A 1020 provide wipe enable, program enable, recovery enables and set/remove enabling pulse.When from normal operation mode (energising) during to the non-volatile maintenance pattern of zero energy (outage) conversion, wipe enable with program enable pulse (following further illustrate) be used for supply voltage from V DDBe reduced to before zero the logic state of the auxilliary latch, stage 1015 of volatibility is transferred to Nonvolatile nanotube switch 1025.When from the non-volatile maintenance pattern of zero energy (outage) during, and supply voltage is being returned to V from zero to normal operation mode (energising) conversion DDAfterwards, setting/removing enables and recovers enabling pulse (below further describe) to can be used for the logic state that is stored in the Nonvolatile nanotube switch 1025 is transferred to the auxilliary latch, stage 1015 of volatibility.Then, beginning normal operation mode.Only use that following wiping of further describing enables, program enable, setting/removing enables and recover enabling pulse applies potential pulse (or a plurality of pulse) V between normal operation mode and the non-volatile maintenance pattern of zero energy in the conversion process EPR, otherwise V EPRVoltage is zero.
Figure 11 B is the block diagram 1000 ' that the logic state of the wherein auxilliary latch, stage of volatibility is directly transferred to the non volatile register file-level 980 shown in Figure 10 of Nonvolatile nanotube switch.Non volatile register file-level 1005 ' is corresponding to non volatile register file-level 980 shown in Figure 10.The volatile cells k of non volatile register file-level 980 shown in Figure 10 is corresponding to having an input V shown in Figure 11 B INVolatibility main latch level 1010 '.The non-volatile cell k ' of non volatile register file-level 980 shown in Figure 10 comprises having an output V shown in Figure 11 B OUTThe auxilliary latch, stage 1015 ' of volatibility, Nonvolatile nanotube switch 1025 ' and corresponding interconnection.Non volatile register file-level 1005 ' has two operator schemes, i.e. normal operation mode and the wherein non-volatile maintenance pattern of zero energy logic state (or data) of outage.
At normal operation mode, volatibility main latch level 1010 ' receives input voltage V IN, drive the auxilliary latch, stage 1015 ' of volatibility, by clock control (following further illustrate) and V from providing by power source 1045 ' DDPower supply.
The auxilliary latch, stage 1015 ' of volatibility receives input, output voltage V is provided from the output of volatibility main latch 1010 ' OUT, by clock control (following further illustrate) and V from providing by power source 1045 ' DDPower supply.The auxilliary latch, stage 1015 ' of volatibility is coupled in Nonvolatile nanotube switch 1025 ' by being electrically connected 1040 '.
From normal operation mode during the non-volatile maintenance mode conversion of zero energy, perhaps from the non-volatile maintenance pattern of zero energy during the normal operation mode conversion, by 1030 ' V from providing by power source 1045 ' is provided EPRTo the 1025 ' power supply of Nonvolatile nanotube switch.
The controller (not shown) is via the V that is connected in switch 1025 ' by the electrical connection shown in Figure 11 B 1030 ' EPRTo Nonvolatile nanotube switch 1025 ' provide wipe enable, program enable, recovery enables and set/remove enabling pulse.When from normal operation mode (energising) during to the non-volatile maintenance pattern of zero energy (outage) conversion, wipe enable with program enable pulse (following further illustrate) be used for supply voltage from V DDBe reduced to before zero the logic state of the auxilliary latch, stage 1015 ' of volatibility is transferred to Nonvolatile nanotube switch 1025 '.When from the non-volatile maintenance pattern of zero energy (outage) during, and supply voltage is being returned to V from zero to normal operation mode (energising) conversion DDAfterwards, setting/removing enables and recovers enabling pulse (below further describe) to can be used for the logic state that is stored in the Nonvolatile nanotube switch 1025 ' is transferred to the auxilliary latch, stage 1015 ' of volatibility.Then, beginning normal operation mode.Only use that following wiping of further describing enables, program enable, setting/removing enables and recover to apply potential pulse (or a plurality of pulse) V in the process of enabling pulse conversion between normal operation mode and the non-volatile maintenance pattern of zero energy EPR, otherwise V EPRVoltage is zero.
Figure 12 A illustrates an embodiment 1100 corresponding to the non volatile register file-level circuit of non volatile register file-level 1005 among Figure 11 A.Non volatile register file-level 1100 has two operator schemes, i.e. the non-volatile maintenance pattern of zero energy logic state (or data) of normal operation mode and outage.Volatibility main latch level circuit 1104 is corresponding to volatibility main latch level 1010, the auxilliary latch, stage circuit 1106 of volatibility is corresponding to the auxilliary latch, stage 1015 of volatibility, coupled circuit 1108 is corresponding to coupled circuit 1020, and Nonvolatile nanotube switch 1110 is corresponding to the Nonvolatile nanotube switch 1025 among Figure 11 A.Nonvolatile nanotube switch 1110 and supply voltage V EPRBetween electrical connection 1112 corresponding to being electrically connected 1030, coupled circuit 1108 and volatibility are assisted and are electrically connected 1118 and 1119 corresponding to the electrical connection among Figure 11 A 1040 between the latch, stage circuit 1106.Assist the supply voltage V of the phase inverter in latch, stage circuit 1106 (not shown) to volatibility main latch level circuit 1104 (not shown) and volatibility DDConnection connects V corresponding to the power supply among Figure 11 A DD
Shown in Figure 12 A, the input node 1115 receiving inputted signal V of volatibility main latch level circuit 1104 INAnd driving cmos transmission gate 1130, this transmission gate is connected in and drives the memory node 1135 that is formed by cross-couplings COMS phase inverter 1145 and 1150.Input signal V INCorresponding among Figure 10 from the V of logic 950 INCmos transmission gate 1130 uses NMOS and PMOS device for example to replace only NMOS transmission gate, to guarantee the logical one between whole mains voltage level and the ground voltage level and the state transformation of logical zero by the pressure drop of abatement device threshold value.Clock CLK 1140 and complementary clock CLKb 1140 ' are used for enabling or block the input signal V that imports on the node 1115 by turning on and off cmos transmission gate 1130 INDrive memory node 1135, determine the logical storage state of cross-linked CMOS phase inverter 1145 and 1150 thus.Notice that all phase inverters all are the CMOS phase inverters, unless otherwise noted.The CMOS phase inverter comprises PMOS pull-up device that is coupled in power supply and the NMOS pull-down that is coupled in ground connection, and as below with reference to operating described in the document: H.B.Bakoglu, " Circuits; Interconnections; and Packaging for VLSI (circuit of VLSI, interconnection and encapsulation) ", Addison-Wesley publishes company limited, nineteen ninety, 152 pages.Cross coupling inverter 1145 and 1150 drives the memory node 1155 that is connected in cmos transmission gate 1160.Clock CLK and complementary clock CLKb are used for enabling or block the node 1155 driving main latch level nodes 1120 of logic states by turning on and off cmos transmission gate 1160.
Shown in Figure 12 A, the input node 1120 of the auxilliary latch, stage circuit 1106 of volatibility also as the output node of main latch level circuit 1104, drives phase inverter 1170.The output of phase inverter 1170 is the output voltage V on the output node 1125 OUT, and the input of driving phase inverter 1175.Output signal V OUTV corresponding to the input that is driven into logic 960 among Figure 10 OUTThe output 1180 of phase inverter 1175 is connected in cmos transmission gate 1185.Clock CLK and complementary clock CLKb are used to enable or block the appearance of backfeed loop, and this backfeed loop is cross coupling inverter 1170 and 1175 when enabling.In normal high speed operation, for the 130nmCMOS technology node, clock CLK is to switch at a high speed such as the 3GHz clock rate.Phase inverter 1190 provides complementary clock CLKb or clock CLK.When the storage data, cmos transmission gate 1185 is connected and phase inverter 1170 and 1175 forms cross-linked memory device, and wherein node 1120 serves as memory node.When cmos transmission gate 1185 turn-offed, phase inverter 1170 and 1175 did not have cross-couplings and does not form memory device.Auxilliary latch, stage circuit 1106 is coupled in Nonvolatile nanotube switch 1110 by coupled circuit 1108.
Shown in Figure 12 A, Nonvolatile nanotube switch 1110 is connected in supply voltage V EPR, this supply voltage according to use coupled circuit 1108 selected respective operations patterns required provide wipe, programming or recovery voltage pulse (or a plurality of pulse).Nonvolatile nanotube switch 1110 is also by using electrical connection 1114 to be connected in the node 1116 of coupled circuit 1108.Coupled circuit 1108 is connected in the auxilliary latch, stage circuit 1106 of volatibility, and the electrical connection 1119 that wherein is connected in node 1108 is used for programming mode, is used for the recovery pattern and be electrically connected 1118.
Shown in Figure 12 A, coupled circuit 1108 comprises erase feature.Erasing circuit comprises that drain electrode is connected in common points 1116, source ground and input grid and is connected in the nmos pass transistor 1220 of wiping enabling pulse.
Shown in Figure 12 A, coupled circuit 1108 also comprises programing function, and this function comprises that drain electrode is connected in common points 1116, source electrode is connected in the drain electrode of series connection nmos pass transistor 1225 and the nmos pass transistor 1230 that grid is connected in the program enable input.The grid that series connection nmos pass transistor 1225 also has the source electrode of ground connection and is connected in the node 1180 of non-volatile auxilliary latch, stage circuit 1106.Transistor 1225 is used to reflect the logic state of non-volatile auxilliary latch, stage circuit 1106.If node 1180 is in for example V DDHigh voltage, but then transistor 1225 is in ON state and conduction programming electric current.Yet if node 1180 is in the low-voltage such as zero, transistor 1225 is in OFF state and can not the conduction programming electric current.
Shown in Figure 12 A, coupled circuit 1108 also comprises restore funcitons, and this restore funcitons comprises that source electrode is connected in common points 1116, drain electrode is connected in the PMOS transistor 1240 that recovery enables to import at drain electrode and the grid that common points 1237 is connected in nmos pass transistor 1235.The source ground of transistor 1235 and grid are connected in setting/removing and enable input.Common points 1237 is connected in the memory node 1120 of the auxilliary latch, stage circuit 1106 of volatibility.
In normal operation mode, coupled circuit 1108 inertias, and Nonvolatile nanotube switch 1110 is not by V EPREnergising and with auxilliary latch, stage circuit 1106 decouplings of volatibility.Therefore, for the logic product that uses the 130nm technology node to make, the auxilliary latch, stage circuit 1106 of volatibility main latch level circuit 1104 and volatibility is operated under the normal primary/secondary register manipulation operational mode of (routine) synchronous logic with the high-frequency clock speed of common 3GHz, wherein V DD=1.3V.
In normal operation mode, at clock round-robin section start, clock CLK 1140 remains on low-voltage from high voltage to the low-voltage conversion and clock round-robin the first half, and complementary clock CLKb 1140 ' remains on high voltage from low-voltage to the high voltage conversion and clock round-robin the first half.CMOS transmission apparatus 1130 is connected, with the voltage V of input node 1115 INBe coupled to memory node 1135.CMOS transmission apparatus 1160 turn-offs, and the output of volatibility main latch level circuit 1104 and the input node 1120 of the auxilliary latch, stage circuit 1106 of volatibility are isolated.In normal operation mode, clock CLK is connected in the pattern input 1192 of the auxilliary latch, stage circuit 1106 of volatibility, clock CLK is connected in CMOS transmission apparatus 1185, and the complementary clock CLKb of phase inverter 1190 output also is connected in CMOS transmission apparatus 1185, make the CMOS transmission apparatus also turn-off, thereby the feedback path between the output 1180 of interruption phase inverter 1175 and the input 1120 of phase inverter 1170, so node 1120 is no longer as memory node.Voltage V INCan transform to magnitude of voltage in any moment before clock round-robin the first half finishes, provide sufficient excess time thereby before the clock conversion of the section start of half after the clock circulation, on memory node 1155, store the counterlogic state for cross-linked phase inverter 1145 and 1150 corresponding to correct logic state.
In normal operation mode, clock CLK 1140 half section start behind the clock round-robin transforms to high voltage and remains on high voltage from low-voltage, and complementary clock CLKb 1140 ' changes to low-voltage and remain on low-voltage half behind the clock round-robin from high-voltage variable.CMOS transmission apparatus 1130 turn-offs, thereby makes the voltage V of input node 1115 INFrom memory node 1135 decouplings, memory node remains on the input voltage V corresponding to clock round-robin the first half end INState, and 1115 pairs of memory nodes of memory node 1135 keep complementary states.1160 connections of CMOS transmission apparatus and the input 1120 that the state transitions of memory node 1155 is arrived phase inverter 1170, these inverter drive output node 1125 output voltage V OUT, and the input of driving phase inverter 1175.In normal operation mode, clock CLK is connected in the pattern input 1192 of the auxilliary latch, stage circuit 1106 of volatibility, clock CLK is connected in CMOS transmission apparatus 1185, and the complementary clock CLKb of phase inverter 1190 output also is connected in CMOS transmission apparatus 1185, make the CMOS transmission apparatus also connect, thereby between the input 1120 of the output 1180 of phase inverter 1175 and phase inverter 1170, form feedback path, and then node 1120 serves as memory node.Connect by CMOS transmission apparatus 1185, this makes the output 1180 of phase inverter 1175 drive the input of phase inverter 1170 and the state of the auxilliary latch state levels circuit 1110 of storage finishes up to clock round-robin subordinate phase.
In the non-volatile maintenance pattern of zero energy logic state (or data), coupled circuit 1108 inertias, Nonvolatile nanotube switch 1110 is not by V EPRPower supply, and from auxilliary latch, stage circuit 1106 decouplings of volatibility.The power supply of the auxilliary latch, stage circuit 1106 of volatibility main latch level circuit 1104 and volatibility is zero volt.
In operation, when transforming to the non-volatile maintenance pattern of zero energy from normal operation mode, coupled circuit 1108 must be transferred to Nonvolatile nanotube switch 1110 with the logic state of the auxilliary latch, stage circuit 1106 of volatibility before outage.Shown in the waveform 1250 shown in Figure 12 B, when keeping energising, clock CLK stops at low-voltage state, and complementary clock CLKb is in high-voltage state, and wherein high-voltage state is V DD(for example 1.3 to 2.5 volts) and low-voltage state are zero volts.If Nonvolatile nanotube 1110 is not wiped free of, therefore store previous logic state, then guide coupled circuit 1108 to carry out erase operation, carry out programming operation subsequently.If Nonvolatile nanotube 1110 is in erase status, then use coupled circuit 1108 to start programming mode.
In erase operation, wipe enabling pulse and transform to V from zero volt DD(for example 1.3 to 2.5 volts), thus connect transistor 1220 and between node shown in Figure 12 A 1116 and ground connection, provide conductive path.Program enable voltage is in zero volt, and transistor 1230 turn-offs, and does not have conductive path between node 1116 and the ground connection.Recover enable voltage and be in V DD(for example 1.3 to 2.5 volts), transistor 1240 turn-offs, and not from the conductive path of node 1116 by transistor 1240.And setting/removing enable voltage also is in zero volt, and transistor 1235 turn-offs.Do not have conductive path between common points 1237 and node 1116 or the ground connection, make at the state of the auxilliary latch, stage circuit 1106 of the volatibility at node 1120 places undisturbed.Applying amplitude to the terminal of Nonvolatile nanotube switch 1110 is V EV EPRThe erasing voltage pulse.The resistance of the resistance ratio Nonvolatile nanotube switch 1110 of transistor 1220 is much smaller, even switch 1110 is in on-state.If switch 1110 is in on-state, then electric current from node 1112 flow through switch 1110 and be electrically connected 1114 and the raceway groove of the transistor 1220 connected arrive ground connection, and Nonvolatile nanotube switch 1110 is switched to shutoff (wiping) state.If switch 1110 is in off state, then it remains on shutoff (wiping) state.Note, can be at any moment erasable nonvolatile nanotube switch 1110 before the programming.If known switch 1110 is in erase status, starting program immediately then.The stimulation of wiping of some embodiment has a detailed description in the U.S. Patent application No. (waiting to deliver) that is entitled as " Two-Terminal NanotubeDevices And Systems And Methods Of Making Same (two-terminal nanotube devices and system and preparation method thereof) " according to the present invention.
Notice that in erase operation, transistor 1240,1235 and 1230 all turn-offs, thereby the auxilliary latch, stage circuit 1106 of Nonvolatile nanotube switch 1110 and volatibility is isolated.Therefore, erase operation can carry out and not influence the performance that volatibility is assisted latch, stage circuit 1106 in any moment during normal operation mode, and therefore can be made into the logical operation of device transparent.
Shown in Figure 12 B, during programming operation, the program enable pulse transforms to V from zero volt DDThereby, connect transistor 1230, node 1116 is connected in the drain electrode of transistor 1225.If the node 1180 of the auxilliary latch, stage circuit 1106 of volatibility is in the low-voltage such as zero, then transistor 1225 turn-offs.If the node 1180 of the auxilliary latch, stage circuit 1106 of volatibility is in for example V DDHigh voltage, then transistor 1225 is connected.Transform to V in the program enable pulse from zero volt DDAfterwards, applying amplitude to the node 1112 of switch 1110 is V PThe V of (for example 5 volts) EPRPulse.If transistor 1225 turn-offs, then there is not electric current to flow through, do not programme, and Nonvolatile nanotube switch 1110 remains on the erase status of shutoff (opening).Yet if transistor 1225 is connected, electric current flows through, and programme, and Nonvolatile nanotube switch 1110 is from turn-offing (opening) state transformation to (closure) state of connection.The programming of some embodiment stimulation has a detailed description in the U.S. Patent application No. (waiting to deliver) that is entitled as " Two-Terminal Nanotube Devices And Systems And Methods Of Making Same (two-terminal nanotube devices and system and preparation method thereof) " according to the present invention.
During programming operation, will wipe enable voltage and remain on zero volt and transistor 1220 shutoffs.And, will recover enable voltage and remain on V DD, make transistor 1240 turn-off.And, will set/remove recovery voltage and remain on zero, thereby transistor 1235 turn-offs, and makes and only enables programming operation.
In operation, when from the non-volatile maintenance pattern of zero energy during to the normal operation mode conversion, coupled circuit 1108 must recover power supply V DDAfterwards and clock operation logic state is transferred to the auxilliary latch, stage circuit 1106 of volatibility from Nonvolatile nanotube switch 1110 before beginning.Shown in Figure 12 C, even recovering V DDAfterwards, clock CLK still stops at low-voltage state, and complementary clock CLKb is in high-voltage state, and wherein high-voltage state is V DD(for example 1.3 to 2.5 volts) and low-voltage state are zero volts.
Shown in waveform 1300 among Figure 12 C, during recovery operation, be V with amplitude DDThe V of (for example 1.3 to 2.5 volts) EPRPulse is applied to the terminal 1112 of the Nonvolatile nanotube switch 1110 shown in Figure 12 A.Be at time clock CLK under the situation of zero volt, the cmos transmission gate 1160 of volatibility main latch level circuit 1104 turn-offs, thereby isolates the auxilliary latch, stage circuit 1106 of volatibility.At the section start of recovery operation, it is V that the recovery that is applied to the input 1192 of phase inverter 1190 and cmos transmission gate 1185 enables level DD, will be applied to cmos transmission gate 1185 in its complementation of output place of phase inverter 1190, cmos transmission gate 1185 is connected.Under the situation that transmission gate 1185 is connected, the output 1180 of phase inverter 1175 is electrically connected to the input 1120 of phase inverter 1170; Form memory device, wherein 1120 serve as memory node.Be in V in the recovery enable voltage DDSituation under, transistor 1240 turn-offs.Enable under the situation of zero volt in setting/removing, transistor 1235 turn-offs; Therefore, the voltage of common points 1237 is determined by the node 1120 of the auxilliary latch, stage circuit 1106 of volatibility.At the power up that will be connected to the auxilliary latch, stage circuit 1106 of volatibility to V DDAfterwards, the voltage of node 1120 can be in zero volt or V DDAt conversion V EPRTo recover pulse voltage V DDAfterwards, setting/removing enabling pulse is connected transistor 1235, and node 1120 is forced ground connection (zero volt).Then, setting/removing enabling pulse turn-offs, thereby makes memory node 1120 be in zero volt.Then, recover enabling pulse from V DDTransform to ground connection.Cmos transmission gate 1185 turn-offs, thereby the feedback path that interrupts between the phase inverter 1175 and 1170 makes node 1120 no longer serve as memory node.Simultaneously, transistor 1240 is connected, and Nonvolatile nanotube switch 1110 is connected to node 1120.If Nonvolatile nanotube switch 1110 is connected (closure), then the voltage V on the node 1112 EPRBe applied to node 1120 by transistor 1240, i.e. the input of phase inverter 1170.If Nonvolatile nanotube switch 1110 turn-offs (opening) then node 1120 keeps ground connection.By cmos transmission gate 1185 is turn-offed, made things convenient for recovery operation, because the voltage that applies by Nonvolatile nanotube switch 1110 only has the less input load of phase inverter 1170 inputs, and needn't overcome store status through latching.Then, when lying prostrate from zero, recovery/enabling pulse transforms to V DDThe time, cmos transmission gate 1185 is connected and logic state (or data) is stored on the node 1120, is stored on the output node 1125 and replenish.Transistor 1240 turn-offs and Nonvolatile nanotube switch 1120 is assisted latch, stage circuit 1106 decouplings from volatibility.Estimate that recovery operation only expends several nanoseconds.Begin normal operation mode then.
During recovery operation, will wipe enable voltage and remain on zero volt and transistor 1220 shutoffs.And, program enable voltage is remained on zero volt, and transistor 1230 turn-offs the feasible recovery operation of only enabling.
Figure 13 A illustrates second embodiment 1100 ' corresponding to the non volatile register file-level circuit of non volatile register file-level 1005 among Figure 11 A.Non volatile register file-level 1100 ' has two operator schemes, i.e. the non-volatile maintenance pattern of zero energy logic state (or data) of normal operation mode and outage.Volatibility main latch level circuit 1104 ' is corresponding to volatibility main latch level 1010, the auxilliary latch, stage circuit 1106 ' of volatibility is corresponding to volatile latch level 1015, coupled circuit 1108 ' is corresponding to coupled circuit 1020, and Nonvolatile nanotube switch 1110 ' is corresponding to the Nonvolatile nanotube switch 1025 among Figure 11 A.Nonvolatile nanotube switch 1110 ' and supply voltage V EPRBetween electrical connection 1112 ' corresponding to being electrically connected 1030, coupled circuit 1108 ' and volatibility are assisted and are electrically connected 1118 ' and 1119 ' and 1329 corresponding to the electrical connection among Figure 11 A 1040 between the latch, stage circuit 1106 '.Supply voltage V to the phase inverter in volatibility main latch level circuit 1104 (not shown) and auxilliary latch, stage circuit 1106 (not shown) of volatibility DDConnection connects V corresponding to the power supply among Figure 11 A DD
As shown in FIG. 13A, input node 1115 ' the receiving inputted signal V of volatibility main latch level circuit 1104 ' INAnd driving cmos transmission gate 1130 ', this transmission gate is connected in and drives the memory node 1135 ' that is formed by cross-couplings COMS phase inverter 1145 ' and 1150 '.Input signal V INCorresponding among Figure 10 from the V of logic 950 INCmos transmission gate 1130 ' uses NMOS and PMOS device for example to replace only NMOS transmission gate, to guarantee the logical one between whole mains voltage level and the ground voltage level and the state transformation of logical zero by the pressure drop of abatement device threshold value.Clock CLK 1140 and complementary clock CLKb 1140 ' are used for enabling or block the input signal V that imports on the node 1115 ' by turning on and off cmos transmission gate 1130 ' INDrive memory node 1135 ', determine the logical storage state of cross-linked CMOS phase inverter 1145 ' and 1150 ' thus.Notice that all phase inverters all are the CMOS phase inverters, unless otherwise noted.The CMOS phase inverter comprises the PMOS pull-up device that is coupled in power supply and the NMOS pull-down of ground connection, and as below with reference to operating described in the document: H.B.
Figure A20068002494000311
" Circuits, Interconnections, and Packaging for VLSI (circuit of VLSI, interconnection and encapsulation) ", Addison-Wesley publishes company limited, nineteen ninety, 152 pages.Cross coupling inverter 1145 ' and 1150 ' drives the memory node 1155 ' that is connected in cmos transmission gate 1160 '.Clock CLK and complementary clock CLKb are used for enabling or block the input node 1120 ' of node 1155 ' the driving main latch level circuit 1106 ' of logic states by turning on and off cmos transmission gate 1160 '.
As shown in FIG. 13A, the input node 1120 ' of the auxilliary latch, stage circuit 1106 ' of volatibility also as the output node of main latch level circuit 1104 ', drives phase inverter 1170 '.The output of phase inverter 1170 ' is the output voltage V on the output node 1125 ' OUT, and the input of driving phase inverter 1175 '.Output signal V OUTV corresponding to the input that is driven into logic 960 among Figure 10 OUTThe output 1180 ' of phase inverter 1175 ' is connected in cmos transmission gate 1185 '.Clock CLK and complementary clock CLKb are used to enable or block the appearance of backfeed loop, this backfeed loop cross coupling inverter 1170 ' and 1175 ' when enabling.In normal high speed operation, for the 130nmCMOS technology node, clock CLK is to switch at a high speed such as the 3GHz clock rate.Phase inverter 1190 ' produces complementary clock CLKb or clock CLK.When the storage data, cmos transmission gate 1185 ' connects and phase inverter 1170 ' and 1175 ' forms cross-linked memory device, and wherein node 1120 ' serves as memory node.When cmos transmission gate 1185 ' turn-offed, phase inverter 1170 ' and 1175 ' did not have cross-couplings and does not form memory device.Auxilliary latch, stage circuit 1106 ' is coupled in Nonvolatile nanotube switch 1110 ' by coupled circuit 1108 '.
As shown in FIG. 13A, Nonvolatile nanotube switch 1110 ' is connected in supply voltage V EPR, coupled circuit 1108 ' selected respective operations pattern is required to provide erasing voltage pulse (or a plurality of pulse) to this supply voltage according to using.Nonvolatile nanotube switch 1110 ' is also by using electrical connection 1114 ' to be connected in the node 1116 ' of coupled circuit 1108 '.Coupled circuit 1108 ' is connected in the auxilliary latch, stage circuit 1106 ' of volatibility, and the electrical connection 1119 ' and 1329 that wherein is connected in node 1108 ' is used for programming mode, and is electrically connected 1118 ' and is used for the recovery pattern.
As shown in FIG. 13A, coupled circuit 1108 ' comprises erase feature.Erasing circuit comprises that drain electrode is connected in common points 1317, source ground and input grid and is connected in the nmos pass transistor 1220 ' of wiping enabling pulse.During erase operation, transistor 1343 is in the program enable pulse activation of zero volt, and common points 1317 is connected in common points 1116 ', and this node 1116 ' is connected in Nonvolatile nanotube switch 1110 to enable erase operation.
As shown in FIG. 13A, coupled circuit 1108 ' also comprises programing function, this function comprises that drain electrode is connected in common points 1116 ', source electrode and is connected in the PMOS transistor 1343 that common points 1350 and grid are connected in the output of phase inverter 1330, and wherein the input of phase inverter 1330 is connected in the program enable input.Common points 1350 is connected in cross-linked nmos pass transistor 1325 and 1325 ', and PMOS transistor 1327 and 1327 ' forms high voltage conversion circuit 1360.Nmos pass transistor 1325 and 1325 ' source ground, PMOS transistor 1327 and 1327 ' source electrode are connected in program voltage V PROGComplementary input 1119 ' and 1329 is connected to the input NMOS transistor 1325 and the NMOS 1325 ' of high-voltage variable converter circuit 1360, makes the logic state of high-voltage variable converter circuit 1360 assist the state of latch, stage 1106 ' corresponding to volatibility.V PROGThe auxilliary latch, stage potential circuit 1106 ' of the comparable volatibility of voltage is much higher.By PMOS transistor 1327 program voltage is put on common points 1350, and then put on common points 1116 ' and Nonvolatile nanotube switch 1110 ' by PMOS transistor 1343.If by nmos pass transistor 1325 common node 1350 is kept ground connection, then do not have program voltage to be applied to common points 1350, and Nonvolatile nanotube switch 1110 ' is not programmed.
As shown in FIG. 13A, coupled circuit 1108 ' also comprises restore funcitons, and this restore funcitons comprises having the V of being connected in DDSource electrode, be connected in the PMOS transistor 1365 of drain electrode of the input 1120 ' of the auxilliary latch, stage circuit 1106 ' of volatibility by connector 1118 '.During recovery operation, PMOS transistor 1365 is used for input node 1120 ' is pre-charged to V DD, turn-off then.Nmos pass transistor 1370 has by connector 1118 ' and is connected in input 1120 ' source electrode, is connected in the drain electrode of common points 1317 and is connected in and recover the grid that enables to import.Nmos pass transistor 1342 is in the ON state during recovery operation, and by Nonvolatile nanotube switch 1110 ' and at input node common points 1317 and V EPRBetween discharge path is provided.V EPRDuring recovery operation, be in zero volt.Enable input when activating when transistor 1370 is resumed,, then import node 1120 ' and discharged if Nonvolatile nanotube switch 1110 ' is connected; If non-volatile switch 1110 ' turn-offs, then import node and remain on V DDThe state of the auxilliary latch, stage circuit 1106 ' of volatibility is restored to the state corresponding to the non volatile state of Nonvolatile nanotube switch 1110 '.
In normal operation mode, coupled circuit 1108 ' inertia, and Nonvolatile nanotube switch 1110 ' is not by V EPRPower supply and with the auxilliary latch, stage circuit 1106 ' decoupling of volatibility.Therefore, for the logic product that uses the 130nm technology node to make, the auxilliary latch, stage circuit 1106 ' of volatibility main latch level circuit 1104 ' and volatibility is operated under the normal primary/secondary register manipulation operational mode of (routine) synchronous logic with the high-frequency clock speed of common 3GHz, wherein V DD=1.3V.
In normal operation mode, at clock round-robin section start, clock CLK 1140 remains on low-voltage from high voltage to the low-voltage conversion and clock round-robin the first half, and complementary clock CLKb 1140 ' remains on high voltage from low-voltage to the high voltage conversion and clock round-robin the first half.CMOS transmission apparatus 1130 ' is connected, and will import the voltage V of node 1115 ' INBe coupled to memory node 1135 '.CMOS transmission apparatus 1160 ' turn-offs, and the output of volatibility main latch level circuit 1104 ' and the input node 1120 ' of the auxilliary latch, stage circuit 1106 ' of volatibility are isolated.In normal operation mode, clock CLK is connected in the pattern input 1192 ' of the auxilliary latch, stage circuit 1106 ' of volatibility, clock CLK is connected in CMOS transmission apparatus 1185 ', and the complementary clock CLKb of phase inverter 1190 ' output also is connected in CMOS transmission apparatus 1185 ', make the CMOS transmission apparatus also turn-off, thereby the feedback path between the output 1180 ' of interruption phase inverter 1175 ' and the input 1120 ' of phase inverter 1170 ', so node 1120 ' is no longer as memory node.Voltage V INCan transform to magnitude of voltage in any moment before clock round-robin the first half finishes, provide sufficient excess time thereby before the clock conversion of the section start of half after the clock circulation, go up storage counterlogic state at memory node 1155 ' for cross-linked phase inverter 1145 ' and 1150 ' corresponding to correct logic state.
In normal operation mode, clock CLK 1140 half section start behind the clock round-robin transforms to high voltage and remains on high voltage from low-voltage, and complementary clock CLKb 1140 ' changes to low-voltage and remain on low-voltage half behind the clock round-robin from high-voltage variable.CMOS transmission apparatus 1130 ' turn-offs, thereby makes the voltage V of input node 1115 ' INFrom memory node 1135 ' decoupling, memory node remains on the input voltage V corresponding to clock round-robin the first half end INState, and memory node 1115 ' keeps complementary state to memory node 1135 '.1160 ' connection of CMOS transmission apparatus and the input 1120 ' that the state transitions of memory node 1155 ' is arrived phase inverter 1170 ', this inverter drive output node 1125 ' output voltage V OUT, and the input of driving phase inverter 1175 '.In normal operation mode, clock CLK is connected in the pattern input 1192 ' of the auxilliary latch, stage circuit 1106 ' of volatibility, clock CLK is connected in CMOS transmission apparatus 1185 ', and the complementary clock CLKb of phase inverter 1190 ' output also is connected in CMOS transmission apparatus 1185 ', make the CMOS transmission apparatus also connect, thereby between the input 1120 ' of the output 1180 ' of phase inverter 1175 ' and phase inverter 1170 ', form feedback path, and then node 1120 ' serves as memory node.Connect by CMOS transmission apparatus 1185 ', the output 1180 ' of phase inverter 1175 ' drives the input of phase inverter 1170 ' and the state of the auxilliary latch state levels circuit 1110 ' of storage finishes up to clock round-robin subordinate phase.
In the non-volatile maintenance pattern of zero energy logic state (or data), coupled circuit 1108 ' inertia, Nonvolatile nanotube switch 1110 ' is not by V EPRPower supply, and from the auxilliary latch, stage circuit 1106 ' decoupling of volatibility.The power supply of the auxilliary latch, stage circuit 1106 ' of volatibility main latch level circuit 1104 ' and volatibility is in zero volt.
In operation, when from normal operation mode during to the non-volatile maintenance mode conversion of zero energy, coupled circuit 1108 ' was transferred to Nonvolatile nanotube switch 1110 ' with the logic state of the auxilliary latch, stage circuit 1106 ' of volatibility before outage.Shown in the waveform 1250 ' shown in Figure 13 B, when keeping energising, clock CLK stops at low-voltage state, and complementary clock CLKb is in high-voltage state, and wherein high-voltage state is V DD(for example 1.3 to 2.5 volts) and low-voltage state are zero volts.If Nonvolatile nanotube 1110 ' is not wiped free of, and therefore store previous logic state, then guide coupled circuit 1108 ' to carry out erase operation, carry out programming operation subsequently.If Nonvolatile nanotube 1110 ' is in erase status, then use coupled circuit 1108 ' to start programming mode.
In erase operation, the program enable input voltage is zero volt, and by the output of phase inverter 1330 transistor 1342 is remained on the ON state.Wipe enabling pulse and transform to V from zero volt DD(for example 1.3 to 2.5 volts), thus transistor 1320 connected and the connection transistor 1342 and 1320 by as shown in FIG. 13A provides conductive path between node 1116 ' and ground connection.Be in program enable voltage under the situation of zero volt, transistor 1343 remained on the OFF state by the output of phase inverter 1330.Recover enable voltage and be in zero volt and transistor 1370 shutoffs, and the recovery pre-charge voltage is in V DDAnd transistor 1365 turn-offs, and input 1120 ' is isolated, and makes at the state of the auxilliary latch, stage circuit 1106 ' of volatibility at node 1120 places undisturbed.Applying amplitude to the terminal of Nonvolatile nanotube switch 1110 ' is V EV EPRThe erasing voltage pulse.The resistance of the transistor 1342 of series connection and 1320 resistance ratio Nonvolatile nanotube switch 1110 ' is much smaller, even switch 1110 ' is in on-state.If switch 1110 ' is in on-state, then electric current from node 1112 ' flow through switch 1110 ' and be electrically connected 1114 ' and the transistor 1342 connected and 1320 raceway groove arrive ground connection, and Nonvolatile nanotube switch 1110 ' is switched to shutoff (wiping) state.If switch 1110 ' is in off state, then it remains on shutoff (wiping) state.Note, can be at any moment erasable nonvolatile nanotube switch 1110 ' before the programming.If known switch 1110 ' is in erase status, starting program immediately then.The stimulation of wiping of some embodiment has a detailed description in the U.S. Patent application No. (waiting to deliver) that is entitled as " Two-Terminal Nanotube Devices And Systems And Methods OfMaking Same (two-terminal nanotube devices and system and preparation method thereof) " according to the present invention.
Notice that in erase operation, transistor 1370,1365 and 1343 all turn-offs, thereby the auxilliary latch, stage circuit 1106 ' of Nonvolatile nanotube switch 1110 ' and volatibility is isolated.Therefore, erase operation can carry out and not influence the performance that volatibility is assisted latch, stage circuit 1106 ' in any moment during normal operation mode, and therefore can be made into the logical operation of device transparent.
Shown in Figure 13 B, during programming operation, V EPRBe in zero volt, and the program enable pulse transforms to V from zero volt DDThereby, connect transistor 1343, node 1116 ' is connected in common points 1350, this node also is the output of high-voltage variable converter circuit 1360.If PMOS transistor 1350 is connected and nmos pass transistor 1325 turn-offs then common points 1350 is in high voltage V PROGIf nmos pass transistor 1325 connection PMOS transistors 1327 turn-off then common points 1350 is in zero volt.If common points 1350 is in high voltage V PROG, then electric current flows through and Nonvolatile nanotube switch 1110 ' transforms to the ON state from OFF.Yet common points 1350 is in ground connection, and Nonvolatile nanotube switch 1110 ' remains on the OFF state.The programming of some embodiment stimulation has a detailed description in the U.S. Patent application No. (waiting to deliver) that is entitled as " Two-Terminal Nanotube Devices AndSystemsAnd Methods Of Making Same (two-terminal nanotube devices and system and preparation method thereof) " according to the present invention.
During programming operation, will wipe enable voltage and remain on zero volt and transistor 1320 shutoffs.Output by phase inverter 1330 remains on the OFF position with transistor 1342.And, will recover enable voltage and remain on zero volt, make transistor 1370 turn-off.And, will recover pre-charge voltage and remain on zero, thereby transistor 1365 turn-offs, and makes and only enables programming operation.
In operation, when from the conversion of the non-volatile maintenance pattern of zero energy row normal operation mode, coupled circuit 1108 ' must be at power supply V DDAfter recovering and clock operation logic state is transferred to the auxilliary latch, stage circuit 1106 ' of volatibility from Nonvolatile nanotube switch 1110 ' before beginning.Shown in Figure 13 C, even recovering V DDAfterwards, clock CLK still stops at low-voltage state, and complementary clock CLKb is in high-voltage state, and wherein high-voltage state is V DD(for example 1.3 to 1.8 volts) and low-voltage state are zero volts.
Shown in waveform 1300 among Figure 13 C, during recovery operation, with V EPRKeep ground connection (zero volt) and lie prostrate the terminal 1112 ' that is applied to Nonvolatile nanotube switch 1110 ' as shown in FIG. 13A zero.Be at time clock CLK under the situation of zero volt, the cmos transmission gate 1160 ' of volatibility main latch level circuit 1104 ' turn-offs, thereby isolates the auxilliary latch, stage circuit 1106 ' of volatibility.At the section start of recovery operation, it is V that the recovery that is applied to the input 1192 ' of phase inverter 1190 ' and cmos transmission gate 1185 ' enables level DD, will be applied to cmos transmission gate 1185 ' in its complementation of output place of phase inverter 1190 ', cmos transmission gate 1185 ' is connected.Under the situation that transmission gate 1185 ' is connected, the output 1180 ' of phase inverter 1175 ' is electrically connected to the input 1120 ' of phase inverter 1170 '; Form memory device, wherein 1120 ' serves as memory node.Recover the pre-charge voltage pulse from V DDTransform to ground connection and get back to V DD, of short duration connection transistor 1365 also is pre-charged to positive voltage with node 1120 '.Then, recover enable voltage transistor 1370 and connect, node 1120 ' is connected to common points 1317.The program enable input voltage is zero volt in recovery operation, and the output of phase inverter 1330 remains on the ON state with transistor 1342, thus the terminal that common points 1370 is connected to common points 1116 ' and is connected to Nonvolatile nanotube switch 1110 ' by connector 1114 '.Be at transistor 1370 and 1342 under the situation of ON state, the auxilliary latch, stage circuit 1106 ' of volatibility is connected in the V that remains on ground connection (zero volt) EPRThe power up that will be connected to the auxilliary latch, stage circuit 1106 ' of volatibility before recovery operation begins is to V DDAnd before the recovery enable operation begins, node 1120 ' is pre-charged to V DDSituation under, the auxilliary latch, stage circuit 1106 ' of volatibility is in node 1120 ' and is in V DDState in.If Nonvolatile nanotube switch 1110 ' is connected (closure), then the voltage V on the node 1120 ' DDDischarged, and the input of phase inverter 1170 ' transforms to ground connection.If Nonvolatile nanotube switch 1110 turn-offs (opening) then node 1120 ', i.e. the input of phase inverter 1170 ' remains on V DDBy cmos transmission gate 1185 ' is turn-offed, made things convenient for recovery operation, because the voltage that applies by Nonvolatile nanotube switch 1110 ' only has the less input load of phase inverter 1170 ' input, and needn't overcome store status through latching.Then, when recovering enabling pulse from V DDWhen transforming to zero volt, cmos transmission gate 1185 ' is connected and logic state (or data) is stored on the node 1120 ', and complementation is stored on the output node 1125 '.Transistor 1370 turn-offs and Nonvolatile nanotube switch 1120 ' is assisted latch, stage circuit 1106 ' decoupling from volatibility.Estimate that recovery operation only expends several nanoseconds.Begin normal operation mode then.
During recovery operation, will wipe enable voltage and remain on zero volt and transistor 1320 shutoffs.And, program enable voltage is remained on zero volt, and transistor 1343 turn-offs and transistor 1342 is connected and made and only enable recovery operation.
Figure 14 A illustrates the 3rd embodiment 1100 corresponding to the non volatile register file-level circuit of non volatile register file-level 1005 ' among Figure 11 B ".Non volatile register file-level 1100 " have two operator schemes, the i.e. non-volatile maintenance pattern of zero energy logic state (or data) of normal operation mode and outage.Volatibility main latch level circuit 1104 " corresponding to volatibility main latch level 1010 '; volatibility is assisted latch, stage circuit 1106 " corresponding to the auxilliary latch, stage 1015 ' of volatibility, and Nonvolatile nanotube switch 1110 " corresponding to the Nonvolatile nanotube switch 1025 ' among Figure 11 B.Nonvolatile nanotube switch 1110 " and supply voltage V EPRBetween electrical connection 1112 " corresponding to being electrically connected 1030 ', Nonvolatile nanotube switch 1110 " and assist with volatibility be electrically connected 1114 between the latch, stage circuit 1106 ' " corresponding to the electrical connection 1040 ' among Figure 11 B.To the auxilliary latch, stage circuit 1106 of volatibility main latch level circuit 1104 ' (not shown) and volatibility " the supply voltage V of phase inverter in the (not shown) DDConnection connects V corresponding to the power supply among Figure 11 B DDNote the 3rd embodiment non volatile register file-level circuit 1100 " at non volatile register file-level circuit 1102 " and Nonvolatile nanotube switch 1110 " between do not have coupled circuit.
Shown in Figure 14 A, volatibility main latch level circuit 1104 " input node 1115 " receiving inputted signal V INAnd drive cmos transmission gate 1130 ", this transmission gate is connected in and drives by cross-couplings COMS phase inverter 1145 " and 1150 " memory node 1135 that forms ".Input signal V INCorresponding among Figure 10 from the V of logic 950 INCmos transmission gate 1130 " use NMOS and PMOS device for example to replace only NMOS transmission gate, to guarantee the logical one between whole mains voltage level and the ground voltage level and the state transformation of logical zero by the pressure drop of abatement device threshold value.Clock CLK 1140 and complementary clock CLKb 1140 ' are used for by turning on and off cmos transmission gate 1130 " enable or block the input node 1115 " on input signal V INDrive memory node 1135 ", determine cross-linked CMOS phase inverter 1145 thus " and 1150 " the logical storage state.Notice that all phase inverters all are the CMOS phase inverters, unless otherwise noted.The CMOS phase inverter comprises the PMOS pull-up device that is connected in power supply and the NMOS pull-down of ground connection, and as below with reference to operating described in the document: H.B.Bakoglu, " Circuits; Interconnections; and Packaging for VLSI (circuit of VLSI, interconnection and encapsulation) ", Addison-Wesley publishes company limited, nineteen ninety, 152 pages.Cross coupling inverter 1145 " and 1150 " drive be connected in cmos transmission gate 1160 " memory node 1155 ".Clock CLK and complementary clock CLKb are used for by turning on and off cmos transmission gate 1160 " enable or block the node 1155 of logic states " drive main latch level circuit 1106 " and input node 1120 ".
Shown in Figure 14 A, volatibility is assisted latch, stage circuit 1106 " input node 1120 ", also as main latch level circuit 1104 " output node, drive phase inverter 1170 ".Phase inverter 1170 " output be output node 1125 " on output voltage V OUT, and drive phase inverter 1175 " input.Output signal V OUTCorresponding to the V that drives the input of logic 960 among Figure 10 OUT Phase inverter 1175 " output 1180 " be connected in cmos transmission gate 1185 ".Clock CLK and complementary clock CLKb are used to enable or block the appearance of backfeed loop, and this backfeed loop is cross coupling inverter 1170 when enabling " and 1175 ".In normal high speed operation, for 130nm CMOS technology node, clock CLK is to switch at a high speed such as the 3GHz clock rate.Phase inverter 1190 " generation complementary clock CLKb or clock CLK.When storage during data, cmos transmission gate 1185 " connect and phase inverter 1170 " and 1175 " form cross-linked memory device, wherein node 1120 " serve as memory node.When cmos transmission gate 1185 " when turn-offing, phase inverter 1170 " and 1175 " do not have cross-couplings and do not form memory device.Auxilliary latch, stage circuit 1106 " by connector 1114 " be coupled directly to Nonvolatile nanotube switch 1110 ".
Shown in Figure 14 A, Nonvolatile nanotube switch 1110 " be connected in supply voltage V EPR, this supply voltage provides and wipes, programmes and recover pulse (or a plurality of pulse) as required.Nonvolatile nanotube switch 1110 " also by connector 1114 " be directly connected in the auxilliary latch, stage circuit 1106 of volatibility ".
Figure 14 B illustrates in greater detail by connector 1114 " be directly connected in the auxilliary latch, stage circuit 1106 of volatibility " common points 1180 " Nonvolatile nanotube switch 1110 ".Use source electrode to be connected in voltage source V PSAnd drain electrode is connected in common points 1180 " on draw PFET transistor 1177 " and source ground and drain electrode be connected in common points 1180 " drop-down NFET transistor 1178 " form phase inverter 1175 ".PFET transistor 1177 " grid and NFET transistor 1178 " grid all be connected in node 1125 shown in Figure 14 A ".
In normal operation mode, all direct-coupled Nonvolatile nanotube switches 1110 " all be in OFF (high resistance) state, and V EPRCan be near zero volt or zero volt.Therefore, for the logic product that uses the 130nm technology node to make, volatibility main latch level circuit 1104 " and the auxilliary latch, stage circuit 1106 of volatibility " under the normal primary/secondary register manipulation operational mode of (routine) synchronous logic, operating V wherein with the high-frequency clock speed of common 3GHz DD=1.3V.
In normal operation mode, at clock round-robin section start, clock CLK 1140 " remain on low-voltage from high voltage to the low-voltage conversion and clock round-robin the first half, and complementary clock CLKb 1140 ' " remain on high voltage from low-voltage to the high voltage conversion and clock round-robin the first half.CMOS transmission apparatus 1130 " connect, will import node 1115 " voltage V INBe coupled to memory node 1135 ".CMOS transmission apparatus 1160 " turn-off, and with volatibility main latch level circuit 1104 " output and the auxilliary latch, stage circuit 1106 of volatibility " input node 1120 " isolation.In normal operation mode, clock CLK is connected in the auxilliary latch, stage circuit 1106 of volatibility " pattern input 1192 ", clock CLK is connected in CMOS transmission apparatus 1185 "; and phase inverter 1190 " complementary clock CLKb output also be connected in CMOS transmission apparatus 1185 "; make the CMOS transmission apparatus also turn-off; thus interrupt phase inverter 1175 " output 1180 " with phase inverter 1170 " input 1120 " between feedback path, so node 1120 " no longer be used as memory node.Voltage V INCan transform to magnitude of voltage in any moment before clock round-robin the first half finishes, thereby be cross-linked phase inverter 1145 corresponding to correct logic state " and 1150 " before half the clock conversion of section start of clock circulation back at memory node 1155 " go up the excess time that storage counterlogic state provides abundance.
With reference to Figure 14 A, in normal operation mode, clock CLK 1140 " half section start transforms to high voltage and remains on high voltage from low-voltage behind the clock round-robin, and complementary clock CLKb 1140 ' " change to low-voltage and behind the clock round-robin, remain on low-voltage half from high-voltage variable.CMOS transmission apparatus 1130 " turn-off, thereby make input node 1115 " voltage V INFrom memory node 1135 " decoupling, memory node remains on the input voltage V corresponding to clock round-robin the first half end INState, and memory node 1155 " keep and memory node 1135 " become complementary state.CMOS transmission apparatus 1160 " connect and with memory node 1155 " state transitions to phase inverter 1170 " input 1120 ", this inverter drive output node 1125 " output voltage V OUT, and drive phase inverter 1175 " input.In normal operation mode, clock CLK is connected in the auxilliary latch, stage circuit 1106 of volatibility " pattern input 1192 ", clock CLK is connected in CMOS transmission apparatus 1185 "; and phase inverter 1190 " complementary clock CLKb output also be connected in CMOS transmission apparatus 1185 "; make the CMOS transmission apparatus also connect; thus at phase inverter 1175 " output 1180 " and phase inverter 1170 " input 1120 " between form feedback path, and then node 1120 " serve as memory node.By CMOS transmission apparatus 1185 " connect phase inverter 1175 " output 1180 " drive phase inverter 1170 " and input and the auxilliary latch state levels circuit 1110 of storage " state finish up to clock round-robin subordinate phase.
In operation, at non volatile register file-level circuit 1102 " normal running before wipe (shutoff) Nonvolatile nanotube switch 1110 ".During erase operation, select the input V shown in Figure 14 A IN, make volatibility assist latch, stage circuit 1106 " node 1180 " remain on zero volt.When corresponding to V OUTPhase inverter 1175 " input 1125 " when being in the positive voltage of 1.8-3 volt, node 1180 " be zero volt.When input voltage 1125 " be in positive voltage, NFET 1178 " connect and PFET 1177 " when turn-offing, common points 1180 " be near zero volt or zero volt.
At NFET 1178 " under the situation about connecting, V EPRErasing pulse is as waveform 1250 among Figure 14 C " shown in transform to 10 volts.If Nonvolatile nanotube switch 1110 " be for example 1M Ω at ON state and resistance; and NFET 1178 " be for example 200K Ω at ON state and channel resistance, then with the voltage jump of 8.3V at nanotube switch 1110 " on, and the electric current of 8.3 μ A flows through nanotube switch 1110 " and NFET 1178 " raceway groove arrives ground connection.If Nonvolatile nanotube switch 1110 " erased conditions is the electric current of 8V and 1-5 μ A for example, then nanotube switch 1110 " and transform to the OFF state from ON, have 10M Ω to 1G Ω or higher high resistance state.Then, V EPRZero volt is returned in the erasing pulse conversion, and erase operation finishes.If Nonvolatile nanotube switch 1110 " at the section start of erase operation at the OFF state, it just remains on the OFF state.At Nonvolatile nanotube switch 1110 " afterwards, the beginning normal running.
In operation, when from normal operation mode during, the auxilliary latch, stage circuit 1106 of volatibility before outage to the non-volatile maintenance mode conversion of zero energy " logic state be directly transferred to Nonvolatile nanotube switch 1110 ".As waveform 1250 among Figure 13 B " shown in, when keeping energising, then clock CLK stops at low-voltage state, and complementary clock CLKb is in high-voltage state, and wherein high-voltage state is in V DD(for example 1.3-1.8V).
Shown in Figure 14 C, erasing mode carries out programming operation makes Nonvolatile nanotube switch 1110 " be in the OFF state.During programming operation, V EPRThe high voltage of programming pulse from the null transformation to 5V.If volatibility is assisted latch, stage circuit 1106 " logic state make V OUTBe in for example interior positive voltage of 1.8-3.0V scope, then common points 1125 " be in positive voltage, NFET 1178 " connect and PFET 1177 " turn-off common points 1180 " be near zero volt or the zero volt.The program voltage V of 5V PBe connected in switch 1110 " terminal; and Nonvolatile nanotube switch 1110 " another terminal by connector 1114 " be connected in common terminal 1180 ", this terminal is connected in the transistor NFET 1178 of connection " drain electrode and NFET 1178 by connecting " transistor ground connection.At first, Nonvolatile nanotube switch 1110 " be in high-resistance off state, whole 5V is connected across switch 1110 " on.Then, along with switch 1110 " transform to ON state, switch 1110 " resistance becomes for example about 1M Ω.If NFET 1178 " have for example connection resistance of 200K Ω, then a cross-over connection Nonvolatile nanotube switch 1110 during programming operation " keep the program voltage of 4.2V, and the electric current of 4.2 μ A is from V EPRSource and course is crossed Nonvolatile nanotube switch 1110 " and NFET 1178 " connection transistor arrival ground connection.If for example the Nonvolatile nanotube switch 1110 " programming need stride switch 1110 " keep the program voltage of 3.5-4V, and the program current of 1-4 μ A is by switch 1110 ", then the Nonvolatile nanotube switch 1110 " be programmed to for example low resistance on-state of 1M Ω.Then, V EPRProgramming pulse transforms to zero volt, and Nonvolatile nanotube switch 1110 " the auxilliary latch, stage circuit 1106 of storage volatility " corresponding to positive V OUTLogic state as the ON state, and removable power.
If volatibility is assisted latch, stage circuit 1106 " logic state make V OUTBe for example zero volt, then common points 1125 " be zero volt, PFET 1177 " connect and NFET 1178 " turn-off common points 1180 " be in for example positive voltage V of 3.0V PSOr near it.Programming pulse shown in Figure 14 C from 0 V to 5V PConversion.Common points 1180 " be under the situation of 3V; cross over Nonvolatile nanotube switch 1110 " program voltage that applies can not surpass for example desired program voltage 3.5V, and Nonvolatile nanotube switch 1110 " remain on OFF (high resistance) state of having wiped.Then, V EPRProgramming pulse transforms to zero volt, and Nonvolatile nanotube switch 1110 " the auxilliary latch, stage circuit 1106 of storage volatility " corresponding to V OUT=0 logic state is as the OFF state, and removable power.
In operation, when from the non-volatile maintenance pattern of zero energy during, Nonvolatile nanotube switch 1110 to the normal operation mode conversion " state must be at power supply V DDAfter recovering and clock operation be directly transferred to the auxilliary latch, stage circuit 1106 of volatibility before beginning ".At non volatile register file-level circuit 1102 " and Nonvolatile nanotube switch 1110 " before, the control circuit shown in Fig. 8 B is powered.Control circuit provides/controls clock waveform, recovers to enable waveform, imports waveform, controls power conversion and provide and carry out non-volatile maintenance pattern to the normal operation mode conversion and with normal manipulation mode operation non volatile register file-level circuit 1102 " other required waveform.Shown in Figure 14 D, recover regularly to realize in the increment at three.Recover regularly in the increment first, use connector 1114 " with the auxilliary latch, stage circuit 1106 of volatibility " be connected to Nonvolatile nanotube switch 1110 " and common points 1180 " be set at positive voltage, be independent of Nonvolatile nanotube switch 1110 " state (ON or OFF).Recover regularly in the increment, second for the Nonvolatile nanotube switch 1110 of ON state ", common points 1180 " be discharged into low-voltage, and for the Nonvolatile nanotube switch 1110 of OFF state ", common points 1180 " remain on high voltage.Recover regularly to carry out erase operation in the increment the 3rd, make nanotube switch 1110 in the ON state " transform to the OFF state; The nanotube switch 1110 of OFF state " remain on the OFF state.At this moment, can start normal non volatile register file-level circuit 1102 ".
Recover regularly in the increment V first EPRTransform to for example positive recovery voltage V of 2.2V RRecovery enables to be set at voltage V DD, CLK uprises (V for example DD), and the CLKb step-down.V INRemain on for example low pressure of zero volt.Volatibility main latch level circuit 1104 " with the auxilliary latch, stage circuit 1106 of volatibility " drive and remain on low pressure V such as zero volt OUT, this makes PFET 1177 " connect and NFET 1178 " shutoff (Figure 14 B).To the Nonvolatile nanotube switch 1110 in ON or the OFF state ", with for example supply voltage V PS=2.2V is by PFET 1177 " be applied to node 1180 ".Nonvolatile nanotube switch 1110 for the OFF state ", V EPRTo common points 1180 " influence can ignore, and PFET 1177 " with common points 1180 " be driven into V PS=2.2V; Nonvolatile nanotube switch 1110 for the ON state ", V EPRWith PFET 1177 " both are to common points 11802 " apply 2.2V.CLK becomes ground connection then, and CLKb becomes V DD, CMOS is by door (a pass gate) 1160 " turn-off and the auxilliary latch, stage circuit 1106 of volatibility " input node 1120 " with volatibility main latch level circuit 1104 " decoupling, but remain on 2.2V.Recovery enables to remain on V DD, and cmos transmission gate 1185 " remain on the ON state, constitute the auxilliary latch, stage circuit 1106 of volatibility " backfeed loop.
Recover regularly in the increment V second EPRTransform to 0V from 2.2V.If volatibility nanotube switch 1110 " be in the OFF state, then common points 1180 " remain on positive 2.2V, and V OUTRemain near zero volt or zero volt; Yet, if Nonvolatile nanotube switch 1110 " be in ON state, common points 1180 " voltage reduce.If for example PFET 1177 " the connection channel resistance be 1.75M Ω and Nonvolatile nanotube switch 1110 " connection resistance be 1M Ω, then common points 1180 " voltage drop to 0.8V from 2.2V; and the auxilliary latch, stage circuit 1106 of volatibility " switch to inverse state and V OUTFor just, for example be V DDPFET 1177 " turn-off and NFET 1178 " connect.
Recover regularly to carry out erase operation to guarantee Nonvolatile nanotube switch 1110 in the increment the 3rd " be in the OFF state.Erasing voltage V EPRBe elevated to V from zero EOr for example near the 10V.If for example the Nonvolatile nanotube switch 1110 " at the ON of 1M Ω state; then NFET 1178 " be in the ON state of 200K Ω, then electric current flows through the Nonvolatile nanotube switch 1110 of series connection " and NFET 1178 ", and about 8.3V is connected across Nonvolatile nanotube 1110 " on, electric current is about 8.3 μ A.For 8V, the Nonvolatile nanotube switch 1110 of electric current in 1-8 μ A scope at least " erased conditions, Nonvolatile nanotube switch 1110 " switch to the OFF state.If Nonvolatile nanotube switch 1110 " at the OFF state of for example 1G Ω, then in fact all the erasing pulse of 10V is connected across Nonvolatile nanotube switch 1110 " on, and switch 1110 " remain on the OFF state.Simultaneously, recovery operation is finished, and non volatile register file-level circuit 1102 " the beginning normal running.
The more high voltage that satisfies the Nonvolatile nanotube switch requirement of wiping and programme
In as the volatibility main latch level circuit 1104 of non volatile register file-level circuit 1100 parts shown in Figure 12 A and the auxilliary latch, stage circuit 1106 of volatibility employed FET device for example to the high speed operation under the 3GHz clock rate of 130nm technology node optimize such as V DDOperation is depressed in the low-shrinkage discharge of=1.3V.Coupled circuit 1108 is isolated the Nonvolatile nanotube switch 1110 that these latch circuits and relative high voltage require.
Operation is described in detail at the Nonvolatile nanotube switch described in Figure 12 B 1110 as above, in some embodiments, during erase operation, be about 10V to wiping of applying of the node 1112 of Nonvolatile nanotube switch 1110, and during programming operation, be about 5V with program voltage.The process engineering design and the circuit design that realize relative operate at higher voltages in semi-conductor chip have description in people's such as Bertin U.S. Patent No. 5,818,748.The transistor that uses in high voltage circuit requires specific semiconductor structure to adapt to, and uses trap and drain electrode design, thicker gate oxide and bigger FET channel length to adapt to high-tension circuit usually.
Figure 15 illustrates US Patent No, and 5,818, the prior art high voltage circuit 1400 shown in 748, it can provide the voltage up to about 12V.High-tension circuit 1400 comprises high-voltage power supply 1410, and it can generate on the chip or provide outside chip.But high-voltage power supply and can be that U.S. Patent No. 6,346,846 as people such as Bertin is distributed in the high pressure on the chip describedly on the design chips.The electrology characteristic of the outer programmable power supply of chip has description in " Basics ofPower Supplies-Use of the HP E3631A Programmable Power Supply (use of power supply basis-HPE3631A programmable power supply) ".Scalable off-chip capacitive source can operated in than wide-voltage range such as 1V-12V, and voltage can be adjusted in for example less than 1 millisecond.
Model selection input 1420 determines whether output 1430 and 1435 provides program voltage or the recovery voltage in the 1.3V-2.5V scope of the erasing voltage of about 10V, about 5V.Can be from V DDPower supply but not high-tension circuit 1400 provides recovery voltage.
Output conductor 1440 uses the output stage that comprises compatible PMOS 1445 of high pressure and the compatible NMOS 1450 of high pressure to a plurality of Nonvolatile nanotube switches 1110,1110 ' and 1110 " voltage is provided.The compatible PMOS 1445 of high pressure is connected in high-voltage power supply 1410 and compatible NMOS 1450 ground connection of high pressure by conductor 1430.V PERVoltage is zero volt (ground connection).Comprise that the preposition output stage of compatible PMOS 1455 of high pressure and the compatible NMOS 1460 of high pressure drives the input of output stage.The compatible PMOS 1455 of high pressure is connected in high-voltage power supply 1410 by conductor 1455, and compatible NMOS 1460 ground connection of high pressure.The input of preposition output stage is subjected to the control of the output of demoder 1465.Input signal S 1-S NDetermine to select which output conductor 1440.The output of demoder 1465 is connected in high-voltage power supply 1410.
Figure 16 illustrates people's such as Bertin U.S. Patent No. 5,818, the structure 1500 of 748 described prior art processes design is such as corresponding to triple-well driver transistor 1510 structures in compatible NMOS 1450 of high pressure shown in Figure 14 and the 1460 transistorized P doped substrate 1520.The introducing of P-trap 1525 and N-trap 1530 is to dash and provide as required datum below the ground voltage in order to bear following below the earth level.PMOS structure 1540 and NMOS structure 1550 be the CMOS transistor normally.
As U.S. Patent No. 5,818,748 described high-tension circuit 1400 layouts cause the output conductor 1440 and the spacing of corresponding adjacent conductor to be about the twice of using spacing under the low-voltage circuit situation.For the present invention, wherein the Nonvolatile nanotube switch 1110,1110 ' and 1110 " as the shade device in the register file, the spacing of this output conductor 1440 provides bigger density required for the present invention.
Figure 17 illustrates and is designed to provide corresponding to a plurality of output conductors 1605,1610 of output conductor among Figure 15 1440 and 1615 power source 1600.Each output conductor has a plurality of nanotube switch such as 1605-1,1605-2 to 1605-n.V REFIt is zero volt.High-voltage power supply 1620, model selection input 1625, output stage 1630 and demoder 1635 correspond respectively to as shown in figure 15 high-voltage power supply 1410, model selection input 1420, comprise output stage and the demoder 1465 of PMOS 1445 and NMOS 1450.Power source 1600 can be used for register file level circuit 1110,1110 ' and 1110 ".
Employed transistor in coupled circuit shown in Figure 12 A and 13A 1108 and 1108 ' is applied higher voltage.During erase operation, according to some embodiment of the present invention shown in 12A, NMOS1220 is at the erasing voltage V that applies 10V to node 1112 EPRConnect before, wherein the FET channel resistance usually than the resistance of the Nonvolatile nanotube switch 1110 in the ON state to when young 5 times.For example for the erasing voltage of 10V, the drain electrode of NMOS 1220 is in about 2V.If nanotube switch 1110 has been wiped free of (at the OFF state), then the drain voltage of NMOS 1220 will be near zero.
During programming operation,, apply the program voltage V of 5V to the node 1112 of the Nonvolatile nanotube switch 1110 shown in Figure 12 A according to some embodiment of the present invention EPRIf Nonvolatile nanotube switch 1110 is connected, then can apply voltage to common points 1116 near 5V.The node of the drain electrode of the NMOS 1220 that turn-offs, the source electrode of PMOS transistor 1240 and NMOS 1230 and 1225 is all near 5V.Therefore, forming the NMOS of coupled circuit 1108 and PMOS device may need process engineering design to bear 5V between the terminal.
The present invention can not deviate from its spirit and essential characteristic by other concrete form realization.Therefore, embodiments of the present invention should be considered to be illustrative and be nonrestrictive.

Claims (13)

1. Nonvolatile memery unit comprises:
Volatile memory device is stored the counterlogic state in response to electro photoluminescence; And
The shadow memory device, thereby be coupled in described volatile memory device and receive and store described counterlogic state in response to electro photoluminescence, described shadow memory device comprises the Nonvolatile nanotube switch, and wherein said nanotube switch is stored the corresponding states of described shade device.
2. Nonvolatile memery unit as claimed in claim 1 is characterized in that, described Nonvolatile nanotube switch comprises the two-terminal nanotube switch.
3. Nonvolatile memery unit as claimed in claim 1, it is characterized in that, also comprise coupled circuit, described coupled circuit can arrive described shadow memory device with the counterlogic state transitions of described volatile memory device in response to electro photoluminescence, and can the logic state of described shadow memory device be transferred to described volatile memory device in response to electro photoluminescence.
4. Nonvolatile memery unit as claimed in claim 1 is characterized in that, also comprises coupled circuit, and described coupled circuit comprises:
Programmed circuit provides power path between described volatile memory device and described shadow memory device, and in response to programming signal with the counterlogic state transitions of described volatile memory device to described shadow memory device; And
Restoring circuit provides power path, and in response to restoring signal the logic state of described shadow memory device is transferred to described volatile memory device between described shadow memory device and described volatile memory device.
5. Nonvolatile memery unit as claimed in claim 1 is characterized in that, also comprises coupled circuit, and described coupled circuit comprises:
Erasing circuit is with the described shadow memory device electric connection and the logic state of wiping described shadow memory device in response to erase signal.
6. Nonvolatile memery unit as claimed in claim 1, it is characterized in that, the output node electric connection of the first terminal of described nanotube switch and described volatile memory device, and second terminal of wherein said nanotube switch and program/erase/read line electric connection.
7. Nonvolatile memery unit as claimed in claim 1 is characterized in that, also comprises the controller that also can monitor the power level of described volatile memory device with described volatile memory device electric connection.
8. Nonvolatile memery unit as claimed in claim 7, it is characterized in that, described controller can apply electro photoluminescence to described shadow memory device in response to the power loss of described volatile memory device, and described electro photoluminescence is transferred to described shadow memory device with the logic state of described volatile memory device.
9. Nonvolatile memery unit as claimed in claim 7, it is characterized in that, described controller can increase in response to the power of described volatile memory device and apply electro photoluminescence to described shadow memory device, and described electro photoluminescence is transferred to described volatile memory device with the logic state of described shadow memory device.
10. Nonvolatile memery unit as claimed in claim 1 is characterized in that, is characterized by the state of the described non-volatile nanotube switch storage resistance by the power path in the described nanotube switch.
11. Nonvolatile memery unit as claimed in claim 1 is characterized in that, also comprises the main latch level, can receive voltage and described voltage is outputed to described volatile memory device, described voltage is corresponding to logic state.
12. Nonvolatile memery unit as claimed in claim 11 is characterized in that, the random logic level produces the described voltage corresponding to described logic state.
13. Nonvolatile memery unit as claimed in claim 11 is characterized in that, plate carries the described voltage of high-speed cache generation corresponding to described logic state.
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