CN101272501A - Video/audio encoding and decoding method and device - Google Patents
Video/audio encoding and decoding method and device Download PDFInfo
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- CN101272501A CN101272501A CNA2008101059929A CN200810105992A CN101272501A CN 101272501 A CN101272501 A CN 101272501A CN A2008101059929 A CNA2008101059929 A CN A2008101059929A CN 200810105992 A CN200810105992 A CN 200810105992A CN 101272501 A CN101272501 A CN 101272501A
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Abstract
The invention discloses a video and audio coding and decoding method and a device, which adopts double DSP principal and subordinate architectures. The principal DSP sends a code command to the subordinate DSP. Image data are collected from the subordinate DSP and are coded. A video bit stream is generated and is stored in a data postpositional memory zone, and a data receiving command is sent to the principal DSP; the principal DSP polls the command of the subordinate DSP, and the video bit stream is read according to a data receiving command and is output through a net mouth after being packed; the principal DSP codes by collecting audio data, and an audio bit stream is generated and output through a net mouth after being packed; the principal DSP receives the video bit stream and the audio bit stream which are input from the net mouth and are synchronously processed after being decoded, and images and sounds are output. By adopting the technical proposal of the invention, full-duplex real-time video and audio coding and decoding can be realized and the requirements of bidirectional talkback and bidirectional visibility in video monitoring can be satisfied.
Description
Technical field
The present invention relates to multimedia technology field, relate in particular to a kind of video/audio encoding and decoding method and device.
Background technology
Along with professional development such as digital video monitoring, also come also to carry high more to the requirement of coding standard.H.264 video coding compression standard (hereinafter to be referred as H.264) is one of at present previous in the world compression standard.H.264 advantage is than MPEG-2 and H.263 saves code check about 50%, and the network compatibility is good, helps the processing to error code and packet loss, and the range of application broad is to satisfy the demand of different rates, different resolution and different transmission (storage) occasions.
(Digital Signal Processor, DSP) looking coding is a kind of system realization scheme of high performance-price ratio to use digital signal processor.The DSP disposal ability is strong, be particularly useful for real-time applications such as digital video-audio coding, the encoding scheme that the coding of realizing on DSP is realized than chip has upgradeable huge advantage, same hardware platform both can constantly have been upgraded and improved the performance of current encoder, also can be for becoming another kind of encoder after update software, the highly versatile of system can provide lasting upgrade service, also can realize various customization function easily according to user's request.
But because the restriction of DSP disposal ability, single DSP is difficult to realize the real time codec of full duplex, and along with two-way intercommunication in the digital video monitoring, the demand that bidirectional visual etc. are new continues to bring out, and common coding/decoding apparatus can not satisfy the needs of digital monitor system.
Summary of the invention
The objective of the invention is to propose a kind of video/audio encoding and decoding method and device, be suitable for H.264, the AVS field, can realize the real-time video/audio encoding and decoding of full duplex, satisfied two-way intercommunication in the video monitoring, bidirectional visual demand.
For reaching this purpose, the present invention by the following technical solutions:
A kind of video/audio encoding and decoding method may further comprise the steps:
A, main DSP be to sending coded command from DSP, describedly encodes from the DSP acquisition of image data, is stored in data buffer area after generating video code flow, and sends the Data Receiving instruction to described main DSP;
B, the described order from DSP of described main DSP poll are read described video code flow according to described Data Receiving instruction, and export by network interface the packing back;
C, described main DSP gather voice data and encode, and generate audio code stream, and export by network interface the packing back;
D, described main DSP receive from the video code flow and the audio code stream of network interface input, carry out Synchronous Processing, output image and sound after the decoding.
Steps A further may further comprise the steps:
A1, described order from the described main DSP of DSP poll are according to described coded command parameter configuration encoder;
A2, described from the DSP acquisition of image data, and generate the code stream unit;
A3, inquiry have or not empty data buffer area, if having, then write valid data successively earlier, write data message again, full mark are set for the data buffer area of said write;
A4, describedly send the instruction of described Data Receiving from DSP to described main DSP, described Data Receiving instruction comprises reading of data order and data buffer area index.
Step B further may further comprise the steps:
B1, the described order of described main DSP poll from DSP;
If B2 has new data, all data that do not read of mark read the described data that do not read, and are stored in the local cache district of described main DSP after the packing;
B3, described main DSP give and describedly to write reading of data from DSP and reply, and empty mark are set for the buffer area of the described data that read.
A kind of video/audio encoding and decoding device, comprise main DSP, from DSP and fpga chip, described main DSP is connected from DSP with described, described fpga chip is connected from DSP with described with described main DSP respectively, described main DSP is used for video decode, audio coding decoding, system master, user interface application layer program, agreement assembling and parsing and network send and receive, described fpga chip is used to control LCD and shows, button decoding, status indicator lamp, produce synchronised clock and expansion external interface, describedly be used for images acquired and video coding and send to described main DSP from DSP.
Described main DSP and described from connecting by 32 HPI buses between the DSP, described fpga chip is connected by 8 bit data bus from DSP with described with described main DSP respectively.
External internal storage location of described main DSP and flash cell are used for data processing and storage, and be described from the external internal storage location of DSP, is used for data processing.
Save as described main DSP and described communication shared drive district in the described high-order 2MB from DSP from DSP, comprise the command area of 1MB and the data field of 1MB, described command area is divided into principal and subordinate's order, master-slave response, from main command with from four districts of primary response, each district takies 64KB, be used to deposit command/response word and relevant parameter and the running state data of being provided with, data separation is the buffer area of 8 128kB, is used to store described coded data from DSP.
Described fpga chip also comprises a counter, is used to provide the timestamp of the video encoding of described main DSP and described DSP.
Adopted technical scheme of the present invention, can realize the real-time video and the audio coding decoding of full duplex, satisfied two-way to needs such as the bidirectional visuals of making peace in the monitoring, generality of hardware is strong, is suitable for various video and audio coding standard.
Description of drawings
Fig. 1 is the structural representation of video/audio encoding and decoding device in the specific embodiment of the invention;
Fig. 2 is the flow chart of video/audio encoding and decoding in the specific embodiment of the invention.
Embodiment
Further specify technical scheme of the present invention below in conjunction with accompanying drawing and by embodiment.
The main thought of technical solution of the present invention is to adopt two DSP architecture designs, realizes the collaborative work of two DSP, realizes the encoding and decoding of video and audio frequency simultaneously.
Fig. 1 is the structural representation of video/audio encoding and decoding device in the specific embodiment of the invention.As shown in Figure 1, this video/audio encoding and decoding device comprise main DSP101, from DSP102 and fpga chip 103.Main DSP is used for video decode, audio coding decoding, system master, user interface application layer program, agreement assembling and parsing and network send and receive, fpga chip is used to control LCD demonstration, button decoding, status indicator lamp, generation synchronised clock and expansion external interface, is used for images acquired and video coding and sends to main DSP from DSP.
Main DSP and FPGA finish the system master function jointly, comprise the control, video output, audio frequency I/O, code stream I/O, the I/O of alarm switch amount of User Interface (as the web page, indicator light, button and liquid crystal panel etc.), video and audio collection/output equipment, from functions such as the control of DSP and system's power supplies, finish basic IMAQ and image encoding function from DSP.
Main DSP and from adopting 32 HPI buses to connect between the DSP, connects from adopting 8 bit data bus between DSP and the FPGA main DSP, carries out the transmission of order, data, the control of peripheral hardware, draws extended pin to guarantee the extensibility of system by FPGA.Main DSP can be used as a relatively independent subsystem, and external internal storage location (SDRAM) 104 and flash cell (FLASH) 105 are used to store data, depend on main DSP from DSP, only external internal storage location (SDRAM) 106 is used to store data, can not directly control peripheral hardware.
Main DSP and take high-order 2MB internal memory from DSP from the shared drive district of DSP communication comprises the command area of 1MB and the data field of 1MB.The command area is divided into principal and subordinate's order, master-slave response, from main command with from four districts of primary response, each district takies 64KB, can deposit the command/response word and relevant parameter and running state data are set, data separation is the buffer area of 8 128kB, only is used for storing the coded data from DSP.
128B is the relevant information area of data in the current cache district before in the buffer area, and valid data biasing 128B deposits.
Main DSP is to when DSP gives an order, and main DSP places principal and subordinate's command area to the order from DSP, comprises command word and parameter is set, and orders the data into 32bit, and high 16bit is the type of order, and low 16bit is the counting of order.To from the command area, the order of the similar and different type of command type counting is different then to be judged to new order from DSP poll master, according to the command configuration encoder or read coder state, and writes and replys from the primary response district.
, when main DSP sends data, generate code stream unit from dsp code, and be written to the sky buffer area successively from DSP, write valid data earlier, write information such as data length again, wait for if no empty buffer area then suspends coding.Write finish after, the command area of Xiang Congzhu writes the reading of data order.Main DSP poll is from main command area, the order counting difference of the similar and different type of command type then is judged to new order, by the low level 3bit index data district of order, demarcate all not read datas according to the preceding index that once runs through data, the master-slave response district is answered in the concurrent response of reading of data successively.
Designed the counter 107 of a 90kHz among the FPGA, main DSP and all produce by this counter from the timestamp of DSP sound, video coding.
Fig. 2 is the flow chart of video/audio encoding and decoding in the specific embodiment of the invention.As shown in Figure 2, the flow process of this video/audio encoding and decoding may further comprise the steps.
If step 206 has new data, all data that do not read of mark, the data that do not read, and be stored in the local cache district of main DSP after the packing.
The above; only for the preferable embodiment of the present invention, but protection scope of the present invention is not limited thereto, and anyly is familiar with the people of this technology in the disclosed technical scope of the present invention; the variation that can expect easily or replacement all should be encompassed within protection scope of the present invention.Therefore, protection scope of the present invention should be as the criterion with the protection range of claim.
Claims (8)
1, a kind of video/audio encoding and decoding method is characterized in that, may further comprise the steps:
A, main DSP be to sending coded command from DSP, describedly encodes from the DSP acquisition of image data, is stored in data buffer area after generating video code flow, and sends the Data Receiving instruction to described main DSP;
B, the described order from DSP of described main DSP poll are read described video code flow according to described Data Receiving instruction, and export by network interface the packing back;
C, described main DSP gather voice data and encode, and generate audio code stream, and export by network interface the packing back;
D, described main DSP receive from the video code flow and the audio code stream of network interface input, carry out Synchronous Processing, output image and sound after the decoding.
2, a kind of video/audio encoding and decoding method according to claim 1 is characterized in that steps A further may further comprise the steps:
A1, described order from the described main DSP of DSP poll are according to described coded command parameter configuration encoder;
A2, described from the DSP acquisition of image data, and generate the code stream unit;
A3, inquiry have or not empty data buffer area, if having, then write valid data successively earlier, write data message again, full mark are set for the data buffer area of said write;
A4, describedly send the instruction of described Data Receiving from DSP to described main DSP, described Data Receiving instruction comprises reading of data order and data buffer area index.
3, a kind of video/audio encoding and decoding method according to claim 1 is characterized in that step B further may further comprise the steps:
B1, the described order of described main DSP poll from DSP;
If B2 has new data, all data that do not read of mark read the described data that do not read, and are stored in the local cache district of described main DSP after the packing;
B3, described main DSP give and describedly to write reading of data from DSP and reply, and empty mark are set for the buffer area of the described data that read.
4, a kind of video/audio encoding and decoding device, it is characterized in that, comprise main DSP, from DSP and fpga chip, described main DSP is connected from DSP with described, described fpga chip is connected from DSP with described with described main DSP respectively, described main DSP is used for video decode, audio coding decoding, system master, user interface application layer program, agreement assembling and parsing and network send and receive, described fpga chip is used to control LCD and shows, button decoding, system state indicator, audio sync clock and external expansion interface are looked in generation, describedly are used for images acquired and video coding and send to described main DSP from DSP.
5, a kind of video/audio encoding and decoding device according to claim 4, it is characterized in that, described main DSP and described from connecting by 32 HPI buses between the DSP, described fpga chip is connected by 8 bit data bus from DSP with described with described main DSP respectively.
6, a kind of video/audio encoding and decoding device according to claim 4 is characterized in that, external internal storage location of described main DSP and flash cell are used for data processing and storage, and is described from the external internal storage location of DSP, is used for data processing.
7, a kind of video/audio encoding and decoding device according to claim 6, it is characterized in that, save as described main DSP and described communication shared drive district in the described high-order 2MB from DSP from DSP, comprise the command area of 1MB and the data field of 1MB, described command area is divided into principal and subordinate's order, master-slave response, from main command with from four districts of primary response, each district takies 64KB, be used to deposit command/response word and relevant parameter and the running state data of being provided with, data separation is the buffer area of 8 128kB, is used to store described coded data from DSP.
8, a kind of video/audio encoding and decoding device according to claim 4 is characterized in that, described fpga chip also comprises a counter, is used to provide the timestamp of the video encoding of described main DSP and described DSP.
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| CN2008101059929A CN101272501B (en) | 2008-05-07 | 2008-05-07 | Video/audio encoding and decoding method and device |
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Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101729240A (en) * | 2009-11-13 | 2010-06-09 | 北京中创信测科技股份有限公司 | Method and device for realizing time synchronization |
| CN101964893A (en) * | 2010-06-09 | 2011-02-02 | 杭州海康威视数字技术股份有限公司 | Method for expanding multichannel decoding and multichannel intelligent video processing functions and device thereof |
| CN102098510A (en) * | 2010-11-25 | 2011-06-15 | 深圳市融创天下科技发展有限公司 | Methods and devices for decoding and coding audio/video data |
| CN102270228A (en) * | 2011-07-11 | 2011-12-07 | 杭州华三通信技术有限公司 | Video search method, front-end equipment and rear-end server |
| WO2012028021A1 (en) * | 2010-09-01 | 2012-03-08 | 中兴通讯股份有限公司 | Method and device for video recording |
| CN103179449A (en) * | 2011-12-23 | 2013-06-26 | 联想(北京)有限公司 | Media file playing method, electronic device and virtual machine framework |
| CN103455361A (en) * | 2013-09-06 | 2013-12-18 | 南京南自信息技术有限公司 | Design method for calling 32-bit decoding library under 64-bit operating system |
| CN108650545A (en) * | 2015-07-27 | 2018-10-12 | 青岛海信移动通信技术股份有限公司 | A kind of method for recording and device of multimedia file |
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2008
- 2008-05-07 CN CN2008101059929A patent/CN101272501B/en not_active Expired - Fee Related
Cited By (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101729240A (en) * | 2009-11-13 | 2010-06-09 | 北京中创信测科技股份有限公司 | Method and device for realizing time synchronization |
| CN101729240B (en) * | 2009-11-13 | 2012-10-10 | 北京中创信测科技股份有限公司 | Method and device for realizing time synchronization |
| CN101964893B (en) * | 2010-06-09 | 2012-09-05 | 杭州海康威视数字技术股份有限公司 | Method for expanding multichannel decoding and multichannel intelligent video processing functions and device thereof |
| CN101964893A (en) * | 2010-06-09 | 2011-02-02 | 杭州海康威视数字技术股份有限公司 | Method for expanding multichannel decoding and multichannel intelligent video processing functions and device thereof |
| WO2012028021A1 (en) * | 2010-09-01 | 2012-03-08 | 中兴通讯股份有限公司 | Method and device for video recording |
| CN102098510B (en) * | 2010-11-25 | 2014-07-09 | 深圳市融创天下科技股份有限公司 | Methods and devices for decoding and coding audio/video data |
| CN102098510A (en) * | 2010-11-25 | 2011-06-15 | 深圳市融创天下科技发展有限公司 | Methods and devices for decoding and coding audio/video data |
| CN102270228A (en) * | 2011-07-11 | 2011-12-07 | 杭州华三通信技术有限公司 | Video search method, front-end equipment and rear-end server |
| CN103179449A (en) * | 2011-12-23 | 2013-06-26 | 联想(北京)有限公司 | Media file playing method, electronic device and virtual machine framework |
| CN103179449B (en) * | 2011-12-23 | 2016-03-02 | 联想(北京)有限公司 | The player method of media file, electronic equipment and virtual machine architecture |
| CN103455361A (en) * | 2013-09-06 | 2013-12-18 | 南京南自信息技术有限公司 | Design method for calling 32-bit decoding library under 64-bit operating system |
| CN103455361B (en) * | 2013-09-06 | 2017-02-08 | 南京南自信息技术有限公司 | Method for calling 32-bit decoding library under 64-bit operating system |
| CN108650545A (en) * | 2015-07-27 | 2018-10-12 | 青岛海信移动通信技术股份有限公司 | A kind of method for recording and device of multimedia file |
| CN108650545B (en) * | 2015-07-27 | 2021-01-19 | 青岛海信移动通信技术股份有限公司 | Method and device for recording multimedia file |
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| CN101272501B (en) | 2010-10-13 |
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