CN101266577B - Programmable on-chip memorizer interface NOR flash memory reading quickening control method - Google Patents
Programmable on-chip memorizer interface NOR flash memory reading quickening control method Download PDFInfo
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- CN101266577B CN101266577B CN2008100352109A CN200810035210A CN101266577B CN 101266577 B CN101266577 B CN 101266577B CN 2008100352109 A CN2008100352109 A CN 2008100352109A CN 200810035210 A CN200810035210 A CN 200810035210A CN 101266577 B CN101266577 B CN 101266577B
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Abstract
The invention discloses an accelerating control method for the NOR flash memory read of the memory interface on a programmable chip belonging to an embedded memory technology field, first, in an objective program instruction needed in the executing of the NOR flash memory, configuring the interface of the NOR flash memory and the memory on chip according to the address space of the objective program in the NOR flash memory; then, reading the objective program instruction in the NOR flash memory and sending the read objective program instruction to the on chip memory through the interface whenexecuting the objective program first time; the system reads the objective program instruction in the memory on chip directly and executes in the following course of executing the objective program, instead of reading the objective program instruction in the NOR flash memory, when the system executes other instructions, the system reads the instruction in the NOR flash memory and executes still. The invention increases the read speed, and can support the on chip memory with different sizes through hardware interface programming, avoided the problem of compatibility.
Description
Technical field
What the present invention relates to is a kind of control method of electronic engineering technical field memory interface, specifically is the NOR flash memory reading and control method thereof that has memory interface on a kind of programmable chip.
Background technology
NOR (or non-) flash memories has obtained using widely in system level chip and handheld mobile device.But the required time for reading of NOR flash memory is still too slow with respect to the clock frequency of system level chip and handheld mobile device.It is a lot of to read the research of acceleration for the NOR flash memory in the past, such as history buffer, read in advance, the parallel mechanism etc. that reads of polylith flash memory, analyze from hardware point of view, constantly improve its reading speed, but the research majority that reads acceleration for the NOR flash memory is limited or cost is excessive to the lifting of speed, and improve the few of NOR flash memory from the research of software-hardware synergism design point of view, and along with the application of multimedia technology and Flame Image Process, the research of this part is more and more important, and it has directly determined the execution speed of instruction.
Find by prior art documents, Oren Avissar etc. were " ACM Transactions onEmbedded Computing Systems " (Association for Computing Machinery's embedded computing system transactions) 2002, at on-chip memory a kind of allocation strategy of selecting element to put into on-chip memory has been proposed in " An Optimal Memory Allocation Scheme forScratch-Pad-Based Embedded Systems " (a kind of optimal Storage distribution mechanism) that the 1st phase 6-26 page or leaf is delivered based on embedded on-chip memory, use the on-chip memory of fixed size, choose data by allocation strategy and put into the high speed on-chip memory, thereby reach the purpose that improves reading speed.But, the weak point of this method is that on-chip memory needs the relative complex allocation strategy to choose suitable data, this has increased the task amount of software section in the software-hardware synergism design to a certain extent, for different application programs, need different allocation strategies, reduced the ease for use of design, this is unacceptable in actual applications.
Summary of the invention
The present invention is directed to deficiency of the prior art, the NOR flash memory that has memory interface on a kind of programmable chip reading and control method thereof is provided, make it when execution is stored in built-in application program in the NOR flash memory, in order to eliminate because of reading the clock period that the NOR flash memory increases, utilize programmable on-chip memorizer, by analyzing fast target program of carrying out and specific acceleration request, and then select the interface of suitable on-chip memory and NOR flash memory by hardware programming, the data of NOR flash memory that will be corresponding with interface are put into on-chip memory, reduce the number of times that reads the NOR flash memory, obviously improved execution efficient.
The present invention is achieved by the following technical solutions, and the present invention is specific as follows:
At first, in the objective program instruction of the required execution of NOR flash memory, be configured according to the interface of the address space situation of target program in the NOR flash memory to NOR flash memory and on-chip memory;
If when being positioned at the address space of NOR flash memory in the instruction set of target program, it is corresponding with on-chip memory to wait to quicken address space by hardware interface programming;
When if the instruction of target program is scattered in address space in the NOR flash memory, then these dispersions are waited that to quicken address space corresponding by address spaces different on hardware interface programming and the on-chip memory.
Then, when carrying out target program for the first time, read the objective program instruction in the NOR flash memory, simultaneously the instruction of reading is imported into on-chip memory by interface; In the process of carrying out target program subsequently, the objective program instruction that system directly reads in the on-chip memory is carried out, and does not need to read the objective program instruction in the NOR flash memory, and system still reads the instruction execution in the NOR flash memory when carrying out other instructions.
Described target program is meant: the application program that embedded system is performed, this application program needs to be repeatedly used in the process of system's operation, therefore needs to quicken this program implementation process, carries out efficient with the raising system.
Described NOR flash memory, be meant: be used for the nonvolatile memory of storage instruction, be responsible for all instructions that the storage embedded system is carried out, comprise the instruction of target program, the data reading speed of NOR flash memory is generally slower, and reading an instruction generally needs 4 system clock cycles.
Described on-chip memory is meant the high speed on-chip memory that is used to quicken target program, and it reads an instruction only needs 1 system clock cycle, and the storage space of on-chip memory is less than the NOR flash memory.
Described address space is meant: the set of objective program instruction all address realms in the NOR flash memory.
Address space described to be quickened is meant: the address space of target program in the NOR flash memory.Address space can be to concentrate certain the part address space that is positioned at the NOR flash memory, also can be that a component is dispersed in the address space of NOR flash memory.
Described hardware interface programming, for concentrating the address space to be quickened that is arranged in the NOR flash memory, be specially: start address 0 address of the start address A1 that waits to quicken address space corresponding to on-chip memory, other addresses of waiting to quicken address space correspond to on-chip memory by the deviation of itself and start address, when programming, quicken the start address A1 of address space with waiting and wait to quicken length L 1 storage of address space, carry out the interface correspondence by these 2 data, during instruction in reading the NOR flash memory, if the address AS of this instruction is waiting to quicken among the address space, be A1≤AS≤A1+L-1, the address that promptly shows this instruction is by the address BS of hardware interface programming corresponding to on-chip memory, BS=0+AS-A1;
Described hardware interface programming, be dispersed in address space to be quickened in the NOR flash memory for a component, be specially: each start address of waiting to quicken address space corresponding to current not by the start address of the on-chip memory of correspondence, other addresses of waiting to quicken address space correspond to on-chip memory by the deviation of itself and start address, when programming, to wait that at first quickening address space numbers from 1 to N, N is dispersed in treating in the NOR flash memory to quicken the address amount of space, again each is waited to quicken the start address Ai of address space and wait to quicken the length L i storage of address space, 1≤i≤N, carry out the interface correspondence by this 2N data, during instruction in reading the NOR flash memory, if the address AS of this instruction is among certain waits to quicken address space, be Ax≤AS≤Ax+Lx-1,1≤x≤N, the address that shows this instruction is by the address BS of hardware interface programming corresponding to on-chip memory, BS=0+L1+L2+ ... + Lxx+AS-Ax, xx=x-1.
Compared with prior art, the present invention has following beneficial effect: the present invention has not only introduced the mechanism that on-chip memory quickens, and has improved reading speed, and has programmed by hardware interface, avoid the use of complicated software distribution strategy, can support the on-chip memories of different sizes simultaneously flexibly.The present invention does not have compatibility issue, and application program need not to make any modification at the present invention and can use.Application program of the present invention can reduce by 75% instruction time for reading at most in carrying out.
Description of drawings
Fig. 1 reads expedited data flow direction figure for programmable on-chip memorizer interface NOR flash memory;
Fig. 2 is hardware interface programming synoptic diagram.
Embodiment
Below in conjunction with accompanying drawing embodiments of the invention are elaborated: present embodiment is being to implement under the prerequisite with the technical solution of the present invention, provided detailed embodiment and concrete operating process, but protection scope of the present invention is not limited to following embodiment.
Quicken the executory example that is applied as with Advanced Encryption Standard (AES) encrypting and decrypting of carrying out based on the NOR flash memory in the present embodiment.
AES encrypts and comprises a S map function commonly used, and the address space of 1024 bytes of this action need is used to deposit the constant data; The AES deciphering comprises a S inverse transformation operation commonly used, and this operation needs the address space of 1024 bytes to be used to deposit the constant data equally.Each S map function is read 16 constant data according to the different needs of enciphered data in the S of 1024 bytes conversion constant space, each AES encrypts and needs 48 S map functions at least; Each S inverse transformation operation is read 16 constant data according to the different needs of data decryption in the S of 1024 bytes inverse transformation constant space, each AES deciphering needs 48 S inverse transformation operations at least.In the present embodiment S conversion and S inverse transformation are quickened, the data that are about to 1024+1024=2048 byte deposit on-chip memory in and read acceleration, and processing procedure is as follows:
As Fig. 1, at first the AES encrypting and decrypting code that external interface is transmitted by the data input all writes in the NOR flash memory.Next analyzes the AES instruction, determines address space to be quickened, and wherein: the address space of S map function is positioned at address 0x1720-0x1B19 on the NOR flash memory, and the address space of S inverse transformation operation is positioned at address 0x1D20-0x2119 on the NOR flash memory.
Then, as Fig. 2, wait to quicken address space and determine, the start address A1 that waits to quicken address space 1 is 0x1720, and length L 1 is 0x400; The start address A2 that waits to quicken address space 2 is 0x1D20, and length L 2 is 0x400.It is corresponding with on-chip memory to wait to quicken address space by hardware interface programming again, and correspondence waits that the corresponding address space 1 of quickening address space 1 is positioned at address 0x000-0x399 (L1-1) on the on-chip memory; Correspondence waits that the corresponding address space 2 of quickening address space 2 is positioned at address 0x400 (L1) on the on-chip memory-0x799 (L1+L2-1).
When carrying out AES encrypting and decrypting instruction AS (AS is this instruction address in the NOR flash memory), the start address A1 of the acceleration address space stored of basis at first, A2 and wait to quicken the length L 1 of address space, L2 judges whether this instruction is the instruction that can quicken.If A1≤AS≤A1+L1-1, but then AS is an assisted instruction, and its corresponding on-chip memory address is AS-A1; If A2≤AS≤A2+L1-1, but then AS is an assisted instruction, and the on-chip memory address of device correspondence is L1+AS-A2; If be other situations, then AS is can not assisted instruction, provides instruction by the output of the low speed data among Fig. 1.
, then judge whether to read for instruction for the first time by the output of the high speed among Fig. 1 control if but AS is an assisted instruction.If for instruction is for the first time read, then provide instruction by low speed data output and with instruction storage in the on-chip memory address of instruction AS correspondence; Read if not instruction for the first time, then directly will instruct sense order the on-chip memory of AS correspondence from on-chip memory.
Present embodiment is not when considering the low speed data output that the first time, assisted instruction read, the individual instructions of a plurality of clock period can be read and be reduced to a clock period, for reading the NOR flash memory that an instruction generally needs 4 system clock cycles, can reach 4 times of acceleration effects that read.
Claims (7)
1. the NOR flash memory reading and control method thereof that has memory interface on the programmable chip, it is characterized in that, at first, in the objective program instruction of the required execution of NOR flash memory, be configured according to the interface of the address space situation of target program in the NOR flash memory NOR flash memory and on-chip memory, specific as follows:
If when being positioned at the address space of NOR flash memory in the instruction set of target program, it is corresponding with on-chip memory to wait to quicken address space by hardware interface programming;
When if the instruction of target program is scattered in address space in the NOR flash memory, then these dispersions are waited that to quicken address space corresponding by address spaces different on hardware interface programming and the on-chip memory;
Then, when carrying out target program for the first time, read the objective program instruction in the NOR flash memory, simultaneously the instruction of reading is imported into on-chip memory by memory interface; In the process of carrying out target program subsequently, the objective program instruction that system directly reads in the on-chip memory is carried out, and does not need to read the objective program instruction in the NOR flash memory, and system still reads the instruction execution in the NOR flash memory when carrying out other instructions.
2. have the NOR flash memory reading and control method thereof of memory interface on the programmable chip according to claim 1, it is characterized in that, described NOR flash memory is meant: be used for the nonvolatile memory of storage instruction, be responsible for all instructions that the storage embedded system is carried out.
3. have the NOR flash memory reading and control method thereof of memory interface on the programmable chip according to claim 1 and 2, it is characterized in that, described NOR flash memory, it reads an instruction needs 4 system clock cycles.
4. have the NOR flash memory reading and control method thereof of memory interface on the programmable chip according to claim 1, it is characterized in that, described on-chip memory, its storage space is less than the NOR flash memory.
5. according to the NOR flash memory reading and control method thereof that has memory interface on claim 1 or the 4 described programmable chips, it is characterized in that, described on-chip memory, it reads an instruction needs 1 system clock cycle.
6. the NOR flash memory reading and control method thereof that has memory interface on the programmable chip according to claim 1, it is characterized in that, described hardware interface programming, for concentrating the address space to be quickened that is arranged in the NOR flash memory, be specially: start address 0 address of the start address A1 that waits to quicken address space corresponding to on-chip memory, other addresses of waiting to quicken address space correspond to on-chip memory by the deviation of itself and start address, when programming, quicken the start address A1 of address space with waiting and wait to quicken length L 1 storage of address space, carry out the interface correspondence by these 2 data, during instruction in reading the NOR flash memory, if the address AS of this instruction is waiting to quicken among the address space, be A1≤AS≤A1+L-1, the address that shows this instruction is by the address BS of hardware interface programming corresponding to on-chip memory, BS=0+AS-A1.
7. the NOR flash memory reading and control method thereof that has memory interface on the programmable chip according to claim 1, it is characterized in that, described hardware interface programming, be dispersed in address space to be quickened in the NOR flash memory for a component, be specially: each start address of waiting to quicken address space corresponding to current not by the start address of the on-chip memory of correspondence, other addresses of waiting to quicken address space correspond to on-chip memory by the deviation of itself and start address, when programming, to wait that at first quickening address space numbers from 1 to N, N is dispersed in treating in the NOR flash memory to quicken the address amount of space, again each is waited to quicken the start address Ai of address space and wait to quicken the length L i storage of address space, 1≤i≤N, carry out the interface correspondence by this 2N data, during instruction in reading the NOR flash memory, if the address AS of this instruction is among certain waits to quicken address space, be Ax≤AS≤Ax+Lx-1,1≤x≤N, the address that shows this instruction is by the address BS of hardware interface programming corresponding to on-chip memory, BS=0+L1+L2+ ... + Lxx+AS-Ax, xx=x-1.
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| US20100306453A1 (en) * | 2009-06-02 | 2010-12-02 | Edward Doller | Method for operating a portion of an executable program in an executable non-volatile memory |
| CN101710297B (en) * | 2009-12-17 | 2015-05-06 | 北京中星微电子有限公司 | Method for running application and controller |
| CN106325822A (en) * | 2016-08-25 | 2017-01-11 | 江苏绿扬电子仪器集团有限公司 | Method for improving DSP (digital signal processor) operation performance |
| CN111190644A (en) * | 2019-12-27 | 2020-05-22 | 核芯互联科技(青岛)有限公司 | Embedded Flash on-chip read instruction hardware acceleration method and device |
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| CN1326136A (en) * | 2000-05-25 | 2001-12-12 | 英业达股份有限公司 | Access control method for flash memory of palm computer |
| CN1728282A (en) * | 2004-07-30 | 2006-02-01 | 深圳市朗科科技有限公司 | Method for increasing speed of writing data into flash memory disk |
| CN1869915A (en) * | 2005-05-24 | 2006-11-29 | 三星电子株式会社 | Memory card providing hardware acceleration for read operations |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1326136A (en) * | 2000-05-25 | 2001-12-12 | 英业达股份有限公司 | Access control method for flash memory of palm computer |
| CN1728282A (en) * | 2004-07-30 | 2006-02-01 | 深圳市朗科科技有限公司 | Method for increasing speed of writing data into flash memory disk |
| CN1869915A (en) * | 2005-05-24 | 2006-11-29 | 三星电子株式会社 | Memory card providing hardware acceleration for read operations |
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| JP特开平5-250256A 1993.09.28 * |
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