CN101262464A - Method for reconfiguring quick Fourier conversion in OFDM system - Google Patents

Abstract

The invention provides a reconfigurable fast fourier transform method used in orthogonal frequency division multiplexing (OFDM) system, which relates to an FFT/IFFT scheme to reconfigure a 64 point and a 256 point based on FPGA by adopting interpolation method. The scheme comprises the steps: first, pretreatment is carried out to the received data, and the 64 points data is made into 256-point/group data by interpolating all-zero data which is then directly made into 256-point/group; afterwards, each group of data is sent to FFT/IFFT arithmetic unit of the 256 point to be processed; finally, the processed data can be output by choosing the 64 point or the 256 point. By adopting FPGA of Altera Company as a hardware platform and using IP cores of Altera Company in large quantities, the scheme greatly saves resources and can obtain high data rate.

Description

The method of reconfigurable fast Fourier transform in the ofdm system

Technical field

The present invention relates to a kind of implementation of the reconfigurable fast Fourier transform (FFT) based on FPGA (field programmable gate array), belong to communication technical field.

Background technology

In order to break away from installation work loaded down with trivial details in the local area network (LAN), wireless lan (wlan) arises at the historic moment, and he is the product that radio communication combines with local area network technology.Up to the present IEEE802.11 series wlan standard mainly comprises 21 standards, and wherein the IEEE802.11a standard operation is used the OFDM modulation technique on the 5GHz frequency range, can support the transmission rate of 54Mbps.Its physical layer OFDM modulated sub-carriers number is 64.In time domain, (IFFT) can produce the OFDM waveform by inverse fast fourier transform

Along with popularizing rapidly and development of multimedia technology of Internet, the user is more and more higher to the requirement of bandwidth.BWA (BWA) progressively is being subjected to the favor of telecommunications industry with advantages such as its small investment instant effects.At present, based on the most popular topic in the BWA technology of the WiMAX technology of IEEE802.16 series standard,, can satisfy the broadband data service demands of different scenes such as fixing, nomadic, portable and mobile because this technological side uses to the metropolitan area level.And in October, 2007, International Telecommunication Union announces that approval WiMAX becomes mobile radio standard, and this will play huge impetus for the development and the commercialization of WiMAX technology.The IEEE802.16 series standard has carried out standard to the air interface physical layer and the MAC layer of BWA.IEEE802.16 standard physical layer adopts OFDM (OFDM) modulation, and its subcarrier is 256.

WiFi is the Local Area Network access technology, and its signal radius has only hundreds of rice far away.WiMAX's is metropolitan area network (MAN) access technology, and its transmission of wireless signals distance can reach 50km farthest.WiMAX and WiFi can mutually combine effectively and be complementary.

In May, 1992, in U.S.'s telecommunication system meeting, the Joe Mitola of MITRE company has clearly proposed the notion of software radio (SDR) first.Software radio is a kind of new approaches that realize radio communication, its core concept is with by terminal hardware resources such as reconfigurable base band, radio frequencies, control by various customizable, alternative, convertible establishment modules, realization is to the support of multiple wireless interface technology, i.e. the notion of multimode/change mould terminal.

FPGA is the abbreviation of Filed Programmable Gate Array, i.e. field programmable gate array.FPGA is the novel high-performance programmable logic device that grows up on the basis of CPLD, and it generally adopts SRAM technology, also has some dedicated devices to adopt Flash technology or anti-fuse technology etc.The integrated level of FPGA is very high, and its device density does not wait to tens million of system doors from tens thousand of system doors, can finish extremely complicated sequential and combinational logic circuit function, is applicable to high speed, highdensity high-end digital logic circuit design field.The element of FPGA has I/O unit able to programme, basic programmable logic cells, embedded quick RAM, abundant interconnection resource, bottom to embed functional unit, embedded special-purpose stone etc.

It is platform that the reconfigurable system physical layer adopts FPGA, realizes the support to WiFi and WiMAX technology physics layer, the core of this reconfigurable system physical layer be exactly one reconfigurable be 64 and 256 s' FFT/IFFT module.

Summary of the invention

Technical problem: the purpose of this invention is to provide the method for reconfigurable fast Fourier transform in a kind of ofdm system, code is multiplexing on hardware, thereby saves the resource of FPGA, raises the efficiency.

Technical scheme: the method for reconfigurable fast Fourier transform in the ofdm system of the present invention, realize that based on the method for the use interpolation of OFDM and extraction reconfigurable is and the positive inverse transformation of fast Fourier at 64 at 256, this method is made up of three modules, data preprocessing module, FFT/IFFT module, Data Post module, the method for its realization is:

Data preprocessing module: according to reshuffling marking signal,, then receive 64 data, and, be assembled into one group 256 data in 3 full remainder certificates of the middle interpolation of each data if 64 FFT/IFFT are carried out in this signal indication; If 256 FFT/IFFT are carried out in this signal indication, then receive 256 data and directly form one group 256 data;

The FFT/IFFT module:

Step 1: the data that will treat FFT/IFFT are earlier got altogether and are gripped,

Step 2: the data that will get after the conjugation are divided into four groups,

Step 3: carry out following three steps then: 1., get data for every group, 2. from tables of data, read corresponding complex exponential according to value, 3. butterfly computation by in four groups that tell in same group;

Step 4: carry out the judgement whether butterfly computation finishes, if not, then return step 2; If then carry out every group of data number and whether be 4 judgement, if then grip altogether, inverted order; If not, then every group of data are further divided into four groups, return step 2 then; Wherein used twiddle factor is produced and is handled by cordic algorithm.

The Data Post module: the data that at first receive the output of FFT/IFFT module are temporary, and then according to reshuffling marking signal, if this signal is designated as 64 FFT/IFFT, then order is exported preceding 64 data, otherwise exports whole 256 data.

The method of data being got conjugation is: the imaginary part that will treat the FFT/IFFT data multiply by-1.

The method of packets at different levels is: in the decimation in frequency method, the packet assembling mode of 256 FFT/IFFT data in the butterfly computation of 4 grades of bases 4 is: the first order, input data after 256 conjugation are one group with 64 sequentially are divided into 4 groups, and in 4 groups, take out the butterfly computation that data are carried out base 4 respectively at every turn; The second level is divided into every group of 16 data with every group of 64 data again by the mode of the first order, has so just obtained partial 16 groupings, fetches data respectively and carries out butterfly computation; The third level is divided by same mode before 16 groupings again, has just obtained 64 groupings, and every group has 4 data, because what adopt is the butterfly unit of base 4, so needn't divide into groups downwards again.

The implementation method of base 4 butterfly processing elements is: suppose that 4 plural numbers that take out the grouping back are A, B, C, D, then the output A of butterfly processing element _t, B _t, C _t, D _tFor:

A _t＝(A+C)+(B+D)；

B _t＝(A-C)-j(B-D)；

C _t＝(A+C)-(B+D)；

D _t＝(A-C)+j(B-D)；

Beneficial effect: this programme adopts the method for inserting extraction to realize reshuffling of 64 and 256 FFT/IFFT, and it has adopted FPGA as hardware platform, has obtained very high data processing rate.This method core is 256 FFT/IFFT computing modules, and this module has adopted cordic algorithm, needn't use embedded multiplier resources extremely valuable in the fpga chip.In addition, this programme carries out modular method, and a lot of modules have adopted the IP kernel of Altera FPGA, do like this and have optimized system design, have saved resource.

Description of drawings

Fig. 1 is the structured flowchart of top layer design of the present invention.

Fig. 2 is the structured flowchart of pretreatment module of the present invention.

Fig. 3 is a pretreatment module flow chart of the present invention.

Fig. 4 is the structured flowchart of 256 FFT/IFFT modules of the present invention.

Fig. 5 is 256 FFT/IFFT modules of the present invention flow chart.

Fig. 6 is a post-processing module structured flowchart of the present invention.

Fig. 7 is a post-processing module flow chart of the present invention.

Embodiment

This method has adopted the Cyclone II of altera corp Series FPGA chip EP2C70F672C8 as hardware platform, finishes the design of reconfigurable FFT/IFFT system.

This system is made up of three parts: data preprocessing module, FFT/IFFT module, Data Post module.Wherein the effect of data preprocessing module is the data set for the treatment of FFT/IFFT to be dressed up 256 data; The FFT module is one 256 point, adopts the basic 4FFT nuclear of cordic algorithm; The data of Data Post module after with FFT/IFFT are with 64 every group or 256 every group output, and carry out the processing in some gains.

The pretreated method of data: this module is made up of 3 submodules: be respectively control submodule, two-port RAM and data chooser module.After receiving a START signal, marking signal is reshuffled in control submodule inspection, receives or input data at 64 at 256, and deposits data in RAM.After the reception data were finished, control submodule control RAM OPADD was reshuffled the output that marking signal is selected data by data chooser module basis, thereby is finished the preliminary treatment of data.

The method of FFT/IFFT: FFT/IFFT cushions DRAM, basic 4 butterfly-unit modules, address control module, twiddle factor generation module and cordic algorithm module by I/O and forms.DRAM is used for storing the intermediate data of input data and computings at different levels; The address control module is used to control each time the address of butterfly-unit desired data and the generation of various external control signals; The cordic algorithm module adopts cordic algorithm, realizes twiddle factor and basic 4 butterfly computation results' product; Export successively data after FFT/IFFT finishes among the DRAM and corresponding address.

The method of Data Post: this module is made up of two-port RAM and control section, and control section receives data and the address thereof by the output of FFT/IFFT module, and deposits data in RAM by the address.Receive the back control section and read 64 or 256 data among the RAM according to reshuffling marking signal again.

Concrete this method is made up of three modules: data preprocessing module, FFT/IFFT module, Data Post module.It is with regard to structured flowchart such as Fig. 1.

Data preprocessing module:

Data preprocessing module has three parts: be respectively the two-port RAM and the interpolation of data submodule of control submodule, the degree of depth 256, its structured flowchart is seen shown in Figure 2, wherein controls submodule and generates the sequential that various control signals are controlled whole module; RAM is used for data cached, uses the IP kernel of Altera to generate.

The handling process of this module in a work period is as follows: after receiving a commencing signal, counter is counted at the beginning, marking signal is reshuffled in the control module inspection, begin to receive the input data simultaneously: be " 00 " if reshuffle marking signal, then mean and to carry out 64 FFT/IFFT computing, the count range of counter one is 0 to 63, and when counting 63, then the output of FFT/IFFT module commencing signal ' 1 '; If this signal is " 11 ", then carry out 256 FFT/IFFT computing, count range from 0 to 255 was counted 255 o'clock, FFT/IFFT module commencing signal output ' 1 '.The output of counter one is directly linked on the Input Address holding wire of RAM, and the data that received deposit in the two-port RAM successively by the address.After the reception data are finished, counter two begins counting, count range is 0 to 255, control module detects once more reshuffles marking signal: if this signal is " 00 ", the output of counter two moves to right and links on the OPADD line of RAM after 2, the RAM dateout is inserted 3 complete 0 data through the interpolation of data submodule behind useful data of every output simultaneously; If marking signal is " 11 ", the output of counter two is directly linked on the RAM OPADD line, and the RAM dateout directly outputs in the FFT/IFFT module.The flow chart of preprocessing part such as Fig. 3

The FFT/IFFT module:

The basic ideas of FFT (IFFT) are that long sequence is decomposed into short sequence, utilize the periodicity of trigonometric function and symmetry to reduce operand.Because the OFDM modulation is equivalent to IFFT (invert fast fourier transformation), that is:

$\mathrm{IFFT}\left[X\left(k\right)\right]=\frac{1}{N}{\left\{\mathrm{FFT}\right[X^{*}\left(k\right)\left]\right\}}^{*}$

Therefore call the conjugation submodule by twice and realize modulation.Because be to adopt a word table to show a plural number, high half-word and low half-word are represented imaginary part and real part respectively, so the conjugation submodule only is that high half-word be multiply by-1.

The FFT submodule adopts basic 4 algorithms, and fundamental formular is as follows:

$X(k_2,k_1,k_0)=\underset{n_0=0}{\overset{3}{\mathrm{\Σ}}}\left\{\underset{n_1=0}{\overset{3}{\mathrm{\Σ}}}\right[\underset{n_2=0}{\overset{3}{\mathrm{\Σ}}}x(n_2,n_1,n_0)\left(W_{64}^{4^2{n}_2{k}_0}\right)W_{64}^{({4n}_1+n_0)k_0}\left]\left(W_{64}^{4^2{n}_1{k}_1}{W}_{64}^{{4n}_0{k}_1}\right)\right\}\left(W_{64}^{4^2{n}_0{k}_2}\right)$

When algorithm is realized sequence is divided into four groups, once gets one and carry out butterfly computation, after first order butterfly computation finishes from every group, each group is further divided into four groups, the same second level butterfly computation that carries out decomposes one by one in each group and has only four elements, carries out the afterbody butterfly computation.Owing to be to realize IFFT, need take advantage of a constant coefficient with FFT Again because this fft algorithm needs log altogether ₄Therefore the computing of N level will

Be decomposed into log ₄N

Being about to constant coefficient decomposes in the computings at different levels.This algorithm is with the location algorithm, does not need extra cushion space.

Twiddle factor W is generated by the twiddle factor maker, and delivers in the cordic algorithm module with the data of butterfly type arithmetic element and to handle.The basic ideas of cordic algorithm: adopt the angle rotation θ that quantizes _n=arctan (1/2 ⁿ) (θ of promptly each rotation _n) approach corresponding phase angle (phase) step by step, wherein n is 0 to the interior value of PIPELINE scope, increases progressively step by step.θ _nDuring greater than phase, Xi, Yi (former vector magnitude) deduct corresponding amount of bias, otherwise, add corresponding amount of bias.Along with the increase of n, the precision of approaching will be more and more higher, and PIPELINE is chosen as 2*STAGE+2 (STAGE is the progression of FFT/IFFT computing, and STAGE gets 4 among 256 FFT in this place) herein.Therefore the quantitative rotation by angle can be similar to the final range value of determining vector, has promptly realized approximate multiplication output.

The dateout that adopts above scheme is an inverted order, but has exported data corresponding address in sequence simultaneously, just can finish the inverted order computing like this in follow-up processing module.

The structured flowchart of FFT/IFFT module as shown in Figure 4, flow chart is as shown in Figure 5.

The Data Post module:

Data, address and the useful signal of the output of FFT/IFFT module are directly delivered to data terminal, the address end of RAM and are write Enable Pin, and the data behind the FFT/IFFT are write among the RAM temporary.Simultaneously, the control submodule detects the address of input, when the address is complete ' 1 ' time, indicate that receiving data finishes, counter begins counting, what the count value of gained was delivered to RAM reads the address end, the control submodule also will detect reshuffles marking signal, if this signal is " 00 ", counter progressively increases and is set to 256 again to 63, otherwise if this signal is " 01 ", counter progressively increases to 256.When count value is not equal to 256, the dateout useful signal is put ' 1 '.

The structured flowchart of Data Post module such as Fig. 6, flow chart are as shown in Figure 7.

Claims (4)

1, the method for reconfigurable fast Fourier transform in a kind of ofdm system, it is characterized in that method based on the use interpolation of OFDM and extraction realizes that reconfigurable is and the positive inverse transformation of fast Fourier at 64 at 256, this method is made up of three modules, data preprocessing module (1), FFT/IFFT module (2), Data Post module (3), the method for its realization is:

Data preprocessing module (1): according to reshuffling marking signal,, then receive 64 data, and, be assembled into one group 256 data in 3 full remainder certificates of the middle interpolation of each data if 64 FFT/IFFT are carried out in this signal indication; If 256 FFT/IFFT are carried out in this signal indication, then receive 256 data and directly form one group 256 data;

FFT/IFFT module (2):

Step 1: the data that will treat FFT/IFFT are earlier got altogether and are gripped,

Step 2: the data that will get after the conjugation are divided into four groups,

Step 3: carry out following three steps then: 1., get data for every group, 2. from tables of data, read corresponding complex exponential according to value, 3. butterfly computation by in four groups that tell in same group;

Step 4: carry out the judgement whether butterfly computation finishes, if not, then return step 2; If then carry out every group of data number and whether be 4 judgement, if then grip altogether, inverted order; If not, then every group of data are further divided into four groups, return step 2 then; Wherein used twiddle factor is produced and is handled by cordic algorithm.

Data Post module (3): the data that at first receive the output of FFT/IFFT module are temporary, and then according to reshuffling marking signal, if this signal is designated as 64 FFT/IFFT, then order is exported preceding 64 data, otherwise exports whole 256 data.

2. the method for reconfigurable fast Fourier exchange in the ofdm system as claimed in claim 1, it is characterized in that the method for data being got conjugation is: the imaginary part that will treat the FFT/IFFT data multiply by-1.

3. the method for reconfigurable fast Fourier transform in the ofdm system as claimed in claim 1, the method that it is characterized in that packets at different levels is: in the decimation in frequency method, the packet assembling mode of 256 FFT/IFFT data in the butterfly computation of 4 grades of bases 4 is: the first order, input data after 256 conjugation are one group with 64 sequentially are divided into 4 groups, and in 4 groups, take out the butterfly computation that data are carried out base 4 respectively at every turn; The second level is divided into every group of 16 data with every group of 64 data again by the mode of the first order, has so just obtained partial 16 groupings, fetches data respectively and carries out butterfly computation; The third level is divided by same mode before 16 groupings again, has just obtained 64 groupings, and every group has 4 data, because what adopt is the butterfly unit of base 4, so needn't divide into groups downwards again.

4. the method for reconfigurable fast Fourier transform in the ofdm system as claimed in claim 1, the implementation method that it is characterized in that basic 4 butterfly processing elements is: suppose that 4 plural numbers that take out the grouping back are A, B, C, D, then the output A of butterfly processing element _t, B _t, C _t, D _tFor:

A _t＝(A+C)+(B+D)；

B _t＝(A-C)-j(B-D)；

C _t＝(A+C)-(B+D)；

D _t＝(A-C)+j(B-D)。

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