CN101256328B - Liquid crystal display panel - Google Patents

Liquid crystal display panel Download PDF

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Publication number
CN101256328B
CN101256328B CN2008100818255A CN200810081825A CN101256328B CN 101256328 B CN101256328 B CN 101256328B CN 2008100818255 A CN2008100818255 A CN 2008100818255A CN 200810081825 A CN200810081825 A CN 200810081825A CN 101256328 B CN101256328 B CN 101256328B
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electrode
substrate
liquid crystal
display panels
voltage
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CN101256328A (en
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廖干煌
刘品妙
陈予洁
丁天伦
陈东佑
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AU Optronics Corp
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AU Optronics Corp
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Abstract

The invention provides a drive array substrate, electrode substrate and liquid crystal display panel. The liquid crystal display panel comprises the drive array substrate, electrode substrate and a liquid crystal layer. The drive array substrate comprises a substrate, a plurality of scanning lines, a plurality of data lines, a plurality of pixel electrodes and drive elements. The scanning lines and the data lines are disposed on the substrate and mutually perpendicular. Each drive element is respectively and electrically connected with the corresponding scanning lines, data lines and pixel electrode to define a pixel area and a non-display area. The electrode substrate is composed of one substrate and one common electrode on the substrate. The liquid crystal layer is disposed between the drive array substrate and the electrode substrate. The liquid crystal layer comprises a plurality of liquid crystal molecules and ions. The liquid crystal molecule has one start voltage and one saturation voltage. The ions in a certain proportion are in the not-display area.

Description

Display panels
Technical field
The invention relates to a kind of active array substrate, electrode base board and display panels, particularly about a kind of can be with the impurity in the liquid crystal layer and ion limit active array substrate, electrode base board and display panels built in the specific region.
Background technology
LCD is widely used at present because have the characteristic of frivolous, short and small and low radiation.But in the processing procedure of the display panels of LCD, with liquid crystal filling, splash into that processing procedure carries out preceding, carry out in or carry out after, can have pollutant or chaff interferences such as some impurity or ion in the liquid crystal layer.When display panels in follow-up use, under long-time the driving, moving, rotate or tilting of liquid crystal can change these impurity or the distribution situation of ion in liquid crystal layer.These impurity or ion can influence the electric field level that becomes to making the liquid crystal activity in the liquid crystal layer, so when display panels during in display frame, brightness, GTG or the quality of image all can be subjected to bad influence.
Disclosed U.S. 20060256245A1 patent application case disclosed a kind of lateral ion and removed device on November 16th, 2006, be arranged in the display panels, addressed areas (addressable area) zone in addition, lateral ion remove device in order to ion is removed to addressed areas zone in addition.By experimental result as can be known, remove the effect of device via lateral ion, the ion concentration in the addressed areas in the pixel can reduce gradually.Yet, inevasiblely in the pixel still have ion, so image quality can't effectively promote.Moreover the running time that lateral ion removes must be elongated, and also removes a big shortcoming of device for lateral ion.
In sum, how to make impurity in the display panels or ion in liquid crystal layer by suitable control, and do not influence the image quality and the task performance of display panels, technical field problem anxious to be solved under being still.
Summary of the invention
The present invention a purpose be to provide a kind of display panels, for solve display panels the problem of picture inequality.Comprise for reaching this display panels of this purpose:
One active array array base palte a: substrate, multi-strip scanning line, many data lines, a plurality of pixel electrode, a plurality of active member and at least one auxiliary electrodes.Described sweep trace is arranged in this substrate.Described data line is vertical with described sweep trace.Respectively this active member correspond to described sweep trace one of them, described data line one of them and described pixel electrode one of them.Respectively this active member electrically connects to define a pixel region and a non-display area with corresponding this sweep trace, this data line and this pixel electrode respectively.This at least one auxiliary electrode is arranged in this substrate, and is positioned at this non-display area.This at least one auxiliary electrode is in order to receive a boosting voltage, and wherein this boosting voltage is between being between-30 volts to 30 volts;
One electrode base board a: substrate; One common electrode is arranged in the substrate of described electrode base board, presses in order to receive energising altogether;
One liquid crystal layer is arranged between described active array substrate and the described electrode base board, comprises: a plurality of liquid crystal molecules, have an initial voltage and a saturation voltage, and a plurality of ion;
The absolute value of the difference of wherein said boosting voltage and common electric voltage is less than the starting potential of liquid crystal molecule, in described liquid crystal layer, the liquid crystal molecule that corresponds to pixel region and non-pixel region has different toppling directions, so that described ion is limited in the non-display area.
This active array substrate also can comprise a capacitance electrode, is arranged in this substrate, and this capacitance electrode electrically connects with this at least one auxiliary electrode.This active array substrate also can comprise a capacitance electrode, is arranged in this substrate, and wherein this capacitance electrode and this auxiliary electrode are insulated from each other and be arranged at same one deck.One of them electric connection of at least one auxiliary electrode of this of this active array substrate and described sweep trace.
Another object of the present invention is to provide a kind of electrode base board, be the problem of the picture inequality that solves display panels.For reaching this purpose, this electrode base board comprises a substrate, a common electrode and a plurality of masking structure.This common electrode is arranged in this substrate.Described masking structure is arranged in this substrate, and to separate this common electrode be a plurality of blocks, and the voltage of wherein said masking structure is-30 volts to 30 volts.
Another object of the present invention is to provide a kind of electrode base board, be the problem of the picture inequality that solves display panels.For reaching this purpose, this electrode base board comprises a substrate and a common electrode.This substrate has a plurality of pixel regions, and respectively this pixel region has a pixel wide.This common electrode is arranged in this substrate.This common electrode has a plurality of slits, and wherein respectively a width of this slit is 1/20 times to 1/5 times of this pixel wide.
Another purpose of the present invention is to provide a kind of display panels, its comprise above-mentioned active array substrate or above-mentioned electrode base board one of them.
By above-mentioned configuration, the present invention display panels, the particle that can limit in the liquid crystal layer moves, and avoids the particle maldistribution in the liquid crystal layer or is arranged in pixel region, causes the generation of the ghost problem of picture inequality.In addition, the present invention display panels, particle in the liquid crystal layer can be limited in the specific region, non-display area for example, avoid pixel region that too much particle is arranged, influence the optical characteristics of the liquid crystal molecule that is positioned at pixel region in the liquid crystal layer, reach the purpose of avoiding picture inequality or ghost problem by this.
For above-mentioned and other purposes, feature and advantage of the present invention can be become apparent, preferred embodiment cited below particularly, and conjunction with figs. are described in detail below.After consulting, affiliated technical field has knows that usually the knowledgeable just can understand other purposes of the present invention, and technological means of the present invention and enforcement aspect.
Description of drawings
Fig. 1 describes the explosive view of display panels of the present invention;
Fig. 2 a is the sectional view of the profile line I-I ' of depiction 1;
Fig. 2 b is the sectional view of the profile line II-II ' of depiction 1;
Fig. 3 a is another sectional view of the profile line I-I ' of depiction 1;
Fig. 3 b is another sectional view of the profile line II-II ' of depiction 1;
Fig. 4 is that top view is amplified in the part of the area B of depiction 1;
Fig. 5 a is a top view of describing the active array substrate of first embodiment;
Fig. 5 b is a top view of describing the display panels of first embodiment;
Fig. 5 c is a sectional view of describing the display panels of first embodiment;
Fig. 6 a is a top view of describing the active array substrate of second embodiment;
Fig. 6 b is a top view of describing the display panels of second embodiment;
Fig. 6 c is a sectional view of describing the display panels of second embodiment;
Fig. 7 a is a top view of describing the active array substrate of the 3rd embodiment;
Fig. 7 b is a top view of describing the display panels of the 3rd embodiment;
Fig. 7 c is a sectional view of describing the display panels of the 3rd embodiment;
Fig. 8 a is a top view of describing the electrode base board of the 4th embodiment;
Fig. 8 b is a top view of describing the display panels of the 4th embodiment;
Fig. 8 c is a sectional view of describing the display panels of the 4th embodiment;
Fig. 9 a is a top view of describing the electrode base board of the 5th embodiment;
Fig. 9 b is a top view of describing the display panels of the 5th embodiment;
Fig. 9 c is a sectional view of describing the display panels of the 5th embodiment;
Figure 10 a is a top view of describing the active array substrate of the 6th embodiment;
Figure 10 b is a top view of describing the display panels of the 6th embodiment;
Figure 10 c is a sectional view of describing the display panels of the 6th embodiment;
Figure 11 a is a top view of describing the active array substrate of the 7th embodiment;
Figure 11 b is a top view of describing the display panels of the 7th embodiment;
Figure 11 c is a sectional view of describing the display panels of the 7th embodiment;
Figure 12 a is a top view of describing the active array substrate of the 8th embodiment;
Figure 12 b is a top view of describing the display panels of the 8th embodiment; And
Figure 12 c is a sectional view of describing the display panels of the 8th embodiment.
Drawing reference numeral:
1,2,3,4,5,6,7,8,9 display panels
10,20,30,40,50,60,70,80,90 active array substrates
101,201,301,401,501,601,701, data line
801、901
102,202,302,402,402 ', 502,602, sweep trace
702、802、902、902a、902b
103,203,303,403,403 ', 503,603, active member (thin film transistor (TFT))
703、803、903
104,204,304,404,504,604,704, pixel electrode
804、904
11,21,31,41,51,61,71,81,91 electrode base boards
12,22,32,42,52,62,72,82,92 liquid crystal layers
120 ions
121a, 121b liquid crystal molecule
200,300,400,500,600,700,800, substrate
900
2011,3011,4011,5011,6011,7011, go up capacitance electrode
8011、9011
2021,3021,4021,5021,6021,7021, capacitance electrode down
8021、9021
2022,3022,4022,7040,8040,9040 auxiliary electrodes
The 2022a main part
2022b branch
203C, 303C, 403C, 503C, 603C, 703C, channel layer
803C、903C
203D, 303D, 403D, 503D, 603D, 703D, drain electrode
803D、903D
203G, 303G, 403G, 503G, 603G, 703G, grid
803G、903G
203S, 303S, 403S, 503S, 603S, 703S, source electrode
803S、903S
205,305,405,505,605,705,805, insulation course
905
206,306,406,506,606,706,806, dielectric layer
906
210,310,410,510,610,710,810, substrate
910
211,311,411,511,611,711,811, chromatic filter layer
911
212,312,412,512,612,612a, 612b masking structure
712、812、912
213,313,413,513,613,713,813, protective seam
913
214,314,414,514,614,714,814, common electrode
914
5140,6140 slits
6020 cover the voltage connection gasket
620 web members
7020 boosting voltage connection gaskets
The A pixel region
The NA non-display area
H1, H3, H ' contact the hole
Embodiment
Because existing pixel region has the problem of ion.Below will active array substrate of the present invention, electrode base board and display panels be described with several embodiment.
Before each embodiment of explanation, please be earlier referring to figs. 1 through Fig. 4.Fig. 1 is a display panels explosive view of the present invention, summarily presents the structure of display panels of the present invention.Display panels 1 comprise an active array substrate 10, an electrode base board 11 and be arranged at active array substrate 10 and electrode base board 11 between a liquid crystal layer 12.Liquid crystal layer 12 comprises a plurality of liquid crystal molecules and a plurality of particle, and wherein particle can be ion, organic substance, dead matter, impurity or combinations thereof or other pollutants.
It is array base palte and the colored filter substrate that active member constitutes that active array substrate 10 and electrode base board 11 can be respectively with the thin film transistor (TFT).It is the common array base palte that constitutes of active member and chromatic filter layer that active array substrate 10 also can be with the thin film transistor (TFT), for example chromatic filter layer the array upper substrate (color filter on array, COA).Electrode base board 11 also can be the electrode base board that the common electrode position constitutes together on base plate.
The set display panels 1 according to the present invention, its liquid crystal layer 12 can present in two kinds of different modes.First kind of presentation mode be please referring to Fig. 2 a and Fig. 2 b, and it is respectively the profile line I-I ' of corresponding diagram 1 and profile line II-II ' and the sectional view that plots.Liquid crystal layer 12 is divided into pixel region A and non-display area NA, electric field difference by pixel region A and non-display area NA in the control liquid crystal layer 12, for example be that pixel region A has different voltage differences with non-display area NA, making corresponding has different toppling direction with liquid crystal molecule 121a in the non-display area NA with 121b at pixel region A.Particularly, the liquid crystal molecule 121b of position in non-display area NA is that horizontally thus, ion 120 can be limited in the non-display area NA, and promptly the interior ion concentration of ion 120 concentration ratio viewing area A is big in the non-display area NA.For example, the several times that ion 120 concentration are about ion concentration in the A of viewing area in the non-display area NA are preferably 2 times to 900 times, so picture picture displayed inequality or ghost problem just can be enhanced to hundreds of times.
Second kind of presentation mode, please referring to Fig. 3 a to Fig. 3 b, it is the profile line I-I ' of corresponding diagram 1 and profile line II-II ' and the sectional view that plots respectively.Liquid crystal layer 12 is divided into pixel region A and non-display area NA, electric field by pixel region A and non-display area NA in the control liquid crystal layer 12 differs, for example be that pixel region A has different voltage differences with non-display area NA, and cause corresponding with 121b different toppling directions being arranged with liquid crystal molecule 121a in the non-display area NA at pixel region A.Particularly, the liquid crystal molecule 121b of position in non-display area NA is homeotropic alignment, thus, ion 120 can be limited in the non-display area NA, be that the interior ion concentration of ion 120 concentration ratio viewing area A is big in the non-display area NA, for example, ion 120 concentration are about the several times of ion concentration in the A of viewing area to hundreds of times in the non-display area NA, picture picture displayed inequality or ghost problem be preferably 2 times to 900 times, so just can be enhanced.
In other words, in order to reach the effect of Fig. 2 a, Fig. 2 b or Fig. 3 a, Fig. 3 b, display panels 1 of the present invention comprises active array substrate 10, electrode base board 11 and liquid crystal layer 12.Further, active array substrate 10 comprises a substrate, multi-strip scanning line, a plurality of data lines, a plurality of pixel electrode and a plurality of active members.Sweep trace and data line are arranged in the substrate, and data line is vertical with sweep trace.Respectively this active member correspond to sweep trace one of them, data line one of them and pixel electrode one of them.Respectively this active member electrically connects to define pixel region A and non-display area NA with corresponding sweep trace, data line and pixel electrode respectively.Electrode base board 11 comprises a substrate and a common electrode, and wherein common electrode is arranged in this substrate.Liquid crystal layer 12 is arranged between active array substrate 10 and the electrode base board 11, and liquid crystal layer 12 comprises liquid crystal molecule 121a, 121b and ion 120. Liquid crystal molecule 121a, 121b have an initial voltage (threshold voltage) and a saturation voltage (saturation voltage), and a predetermined ratio of ion is positioned at this non-display area NA.
Display panels 1 can further comprise at least one auxiliary electrode, and wherein auxiliary electrode is arranged in the substrate of active array substrate 10, not in non-display area NA.This auxiliary electrode is in order to receiving a boosting voltage, and common electrode presses in order to receive energising altogether, and wherein the absolute value of the difference of boosting voltage and common electric voltage is less than the starting potential of liquid crystal molecule 121a, 121b.In addition, when liquid crystal molecule is vertical orientation type (Vertical alignment, VA) liquid crystal, stable twisted nematic (Twisted Nematic, TN) liquid crystal or automatically controlled birefringence type (Electrical Control Birefringence, ECB) during liquid crystal, the absolute value of the difference of boosting voltage and common electric voltage is greater than the saturation voltage of liquid crystal molecule 121a, 121b.When liquid crystal molecule 121a, 121b comprised vertical orientation type liquid crystal, stable twisted nematic liquid crystal or automatically controlled birefringence type liquid crystal, the absolute value of the difference of boosting voltage and common electric voltage was greater than the saturation voltage of liquid crystal molecule 121a, 121b.
Top view is amplified in the part of the area B of the active array substrate 10 of the display panels 1 of Fig. 4 depiction 1.Understand for convenient, Fig. 4 only describes four complete pixels, and affiliated technical field has knows that usually the knowledgeable can know the pixel set-up mode of the Zone Full of understanding active array substrate 10 thus.Active array substrate 10 comprises substrate (indicate), multi-strip scanning line 102, a plurality of data lines 101, a plurality of pixel electrode 104 and a plurality of thin film transistor (TFT) 103 vertical with sweep trace 102.Each thin film transistor (TFT) 103 is connected to corresponding pixel electrode 104, data line 101 and sweep trace 102 respectively.In addition, active array substrate 10 also comprises at least one auxiliary electrode (not illustrating) and/or capacitance electrode (not illustrating).Data line 101, sweep trace 102 and pixel electrode 104 define pixel region A and non-display area NA.The clear scope that shows four pixel region A of Fig. 4, it is the zone that is used for display frame, and the zone beyond pixel region A is non-display area NA, the zone that is set up of data line 101, sweep trace 102, thin film transistor (TFT) 103, auxiliary electrode and capacitance electrode just, non-display area NA can't display frame.
Please be simultaneously with reference to Fig. 2 a-Fig. 3 b and Fig. 4, when ion 120 is limited in non-display area NA, just a predetermined ratio of ion 120 (also being most ion 120) is when being positioned at non-display area NA or so-called line areas, liquid crystal molecule 121a in the pixel region A just is not vulnerable to the influence of ion 120, causes non-correct rotation or inclination, ghost, brightness is cut down or contrasts inaccurate or the like problem and reduce.
Each embodiment detailed structure of the display panels 1 of Fig. 1, active array substrate 10 and electrode base board 11 is in following explanation.
First embodiment
Fig. 5 a, Fig. 5 b, Fig. 5 c are respectively the top view of the active array substrate 20 of the first embodiment of the present invention, the top view of display panels 2 and the sectional view of display panels 2.More specifically, Fig. 5 c describes along the sectional view of the profile line V-V ' of Fig. 5 b.In addition, for convenience of description, dot structure of the only clear demonstration of Fig. 5 a and Fig. 5 b.
Active array substrate 20 comprise a substrate 200, multi-strip scanning line 202, auxiliary electrode 2022, down capacitance electrode 2021, insulation course 205, many data lines 201, active members 203, go up capacitance electrode 2011, dielectric layer 206 and a plurality of pixel electrode 204.Sweep trace 202, auxiliary electrode 2022 and following capacitance electrode 2021 all are formed in the substrate 200.Insulation course 205 whole substrate 200, sweep trace 202, auxiliary electrode 2022 and the following capacitance electrodes 2021 of covering.Data line 201 is formed on the insulation course 205.
Active member 203 is formed in the substrate 200, and each active member 203 correspond to sweep trace 202 one of them, data line 201 one of them and electrically connect with corresponding scanning line 202 and data line 201.Particularly, active member 203 has that grid 203G is connected with sweep trace 202, source electrode 203S and data line 201 are connected, drain 203D and channel layer 203C between grid 203G and source electrode 203S/ drain electrode 203D.The active member 203 of present embodiment is an example with the bottom-gate amorphous silicon film transistor, certainly, have in the affiliated technical field and know that usually the knowledgeable also can use in top grid polycrystalline silicon thin film transistor (TFT) and the appropriate change active member other relative positions relations in the structure and present embodiment.Promptly, the structure of active member is not to be used for limiting interest field of the present invention yet.
Last capacitance electrode 2011 is connected with drain electrode 203D and forms storage capacitors with following capacitance electrode 2021.Dielectric layer 206 covers said elements substantially comprehensively and has a contact hole H and exposes drain electrode 203D.Pixel electrode 204 is arranged on the dielectric layer 206, and electrically connects by contact hole H and drain electrode 203D.
Auxiliary electrode 2022 and sweep trace 202 reach the conductive layer in advance of capacitance electrode 2021 formation one earlier simultaneously down, and patterning forms again.Auxiliary electrode 2022 and sweep trace 202 and capacitance electrode 2021 is insulated from each other and be arranged at same one deck down.Auxiliary electrode 2022 is arranged in the non-display area NA.Shown in Fig. 5 a, auxiliary electrode 2022 has main part 2022a and the 2022b of branch.The 2022b of the branch number that is positioned between two pixels of present embodiment is two, but viewable design and demand, and the number that changes the 2022b of branch is one or greater than two.Similarly, alternative auxiliary electrode 2022 is designed to only have main part 2022a or the 2022b of branch and constitutes strip, or similar ring texture.In other words, can all can use in order to the shape of the auxiliary electrode of reaching purpose of the present invention, for example, the shape of auxiliary electrode 2022 can be a ring-type, a strip, a U word shape and a ㄇ word shape one of them.Auxiliary electrode 2022 is in order to receive a boosting voltage, and wherein boosting voltage is-30 volts to 30 volts, and preferable then is-10 volts to 25 volts.
Please refer to Fig. 5 c, display panels 2 comprises active array substrate 20, the electrode base board 21 shown in Fig. 5 a and is arranged at liquid crystal layer therebetween 22.
Liquid crystal layer 22 comprises a plurality of liquid crystal molecules and a plurality of ion, and wherein, liquid crystal molecule has an initial voltage and a saturation voltage, and a predetermined ratio of ion is positioned at non-display area NA.
Electrode base board 21 comprises substrate 210, masking structure 212, chromatic filter layer 211, protective seam 213 and common electrode 214.Wherein, masking structure 212 and chromatic filter layer 211 all are arranged in the substrate 210.Chromatic filter layer 211 is arranged between substrate 210 and the common electrode 214, and crested structure 212 is separated.On the other hand, chromatic filter layer 211 the edge can utilize masking structure 212 shadings, to avoid display panels 2 when the display frame, produce the problem of light leak.Common electrode 214 is pressed in order to receive energising altogether, wherein, boosting voltage and common electric voltage difference absolute value less than liquid crystal molecule starting potential.For example, boosting voltage and common electric voltage difference absolute value can be less than or equal to 1 volt, also can be 3 volts to 20 volts.
Auxiliary electrode 2022 by active array substrate 20, can make in the liquid crystal layer 22, the liquid crystal molecule that corresponds to pixel region A and non-display area NA has different toppling directions, so ion 120 can be limited in the non-display area NA, so picture picture displayed inequality or ghost problem just can be enhanced.
Second embodiment
Fig. 6 a, Fig. 6 b, Fig. 6 c are respectively the top view of the active array substrate 30 of the second embodiment of the present invention, the top view of display panels 3 and the sectional view of display panels 3.More specifically, Fig. 6 c describes along the sectional view of the profile line VI-VI ' of Fig. 6 b.In addition, for convenience of description, dot structure of the only clear demonstration of Fig. 6 a and Fig. 6 b.
Active array substrate 30 comprise a substrate 300, multi-strip scanning line 302, auxiliary electrode 3022, down capacitance electrode 3021, insulation course 305, many data lines 301, active members 303, go up capacitance electrode 3011, dielectric layer 306 and a plurality of pixel electrode 304.
Sweep trace 302, auxiliary electrode 3022 and following capacitance electrode 3021 all are formed in the substrate 300.Insulation course 305 whole substrate 300, sweep trace 302, auxiliary electrode 3022 and the following capacitance electrodes 3021 of covering.Data line 301 is formed on the insulation course 305.
Active member 303 is formed in the substrate 300, and each active member 203 correspond to sweep trace 202 one of them, data line 201 one of them, and electrically connect with corresponding scanning line 302 and data line 301.Particularly, active member 303 has that grid 303G is connected with sweep trace 302, source electrode 303S and data line 301 are connected, drain 303D and channel layer 303C between grid 303G and source electrode 303S/ drain electrode 303D.Present embodiment active member 303 be example with the bottom-gate amorphous silicon film transistor, certainly, have in the affiliated technical field and know that usually the knowledgeable also can use in top grid polycrystalline silicon thin film transistor (TFT) and the appropriate change active member other relative positions relations in the structure and present embodiment.Also promptly, active member structure be not be used for limiting the present invention interest field.
Last capacitance electrode 3011 is positioned on the insulation course 305 and corresponding capacitance electrode 3021 down.Dielectric layer 306 covers said elements substantially comprehensively, and has contact hole H1 and expose drain electrode 303D, and has contact hole H2 and expose capacitance electrode 3011.Pixel electrode 304 is arranged on the dielectric layer 306, and electrically connects by this contact hole H1 and this drain electrode 303D, and passes through this contact hole H2 and should go up capacitance electrode 3011 electric connections.
Second embodiment and first embodiment different being in, auxiliary electrode 3022 and sweep trace 302 and following capacitance electrode 3021 formation one earlier simultaneously conductive layer in advance, patterning forms again, shown in Fig. 6 a.Auxiliary electrode 3022 electrically connects with following capacitance electrode 3021, so auxiliary electrode 3022 is identical with the current potential of following capacitance electrode 3021.Be positioned between two pixels auxiliary electrode 3022 be shaped as H word shape.In other embodiment, auxiliary electrode shape can be strip, H word shape with and make up one of them, in other words, can in order to reach the present invention purpose auxiliary electrode structure all can use, its shape is not in order to limit interest field of the present invention.Auxiliary electrode 3022 and following capacitance electrode 3021 are in order to receive a capacitance voltage, and wherein, capacitance voltage is-30 volts to 30 volts, and preferable then is-10 volts to 25 volts.
Please refer to Fig. 6 c, display panels 3 comprises active array substrate 30, the electrode base board 31 shown in Fig. 6 a and is arranged at liquid crystal layer therebetween 32.
Liquid crystal layer 32 comprises a plurality of liquid crystal molecules and a plurality of ion, and wherein, liquid crystal molecule has an initial voltage and a saturation voltage, and a predetermined ratio of ion is positioned at non-display area NA.
The structure of electrode base board 31 is identical with electrode base board 21 among first embodiment, does not repeat them here.Common electrode 314 is pressed in order to receive energising altogether.The starting potential of the absolute value liquid crystal molecule of the difference of boosting voltage and common electric voltage.For example, the absolute value of the difference of boosting voltage and common electric voltage can be less than or equal to 1 volt, also can be 3 volts to 20 volts.
Auxiliary electrode 3022 by active array substrate 30, can make the liquid crystal molecule that corresponds to pixel region A and non-display area NA in the liquid crystal layer 32 have different toppling directions, so ion 120 can be limited in the non-display area NA, so picture picture displayed inequality or ghost problem just can be enhanced.
The 3rd embodiment
Fig. 7 a, Fig. 7 b, Fig. 7 c are respectively the top view of the active array substrate 40 of the third embodiment of the present invention, the top view of display panels 4 and the sectional view of display panels 4.More specifically, Fig. 7 c describes along the sectional view of the profile line VII-VII ' of Fig. 7 b.In addition, for convenience of description, dot structure of the only clear demonstration of Fig. 7 a and Fig. 7 b.
Active array substrate 40 comprise a substrate 400, multi-strip scanning line 402,402 ', auxiliary electrode 4022, down capacitance electrode 4021, insulation course 405, many data lines 401, active member 403,403 ', go up capacitance electrode 4011, dielectric layer 406 and a plurality of pixel electrode 404.Sweep trace 402,402 ', auxiliary electrode 4022 and down capacitance electrode 4021 all be formed in the substrate 400.Insulation course 405 is whole to cover substrates 400, sweep trace 402,402 ', auxiliary electrode 4022 and capacitance electrode 4021 down.Data line 401 is formed on the insulation course 405.
Active member 403,403 ' is formed in the substrate 400, and each active member 403 correspond to sweep trace 402,402 ' one of them, data line 401 one of them, and with corresponding scanning line 402,402 ' and data line 401 electrically connect.Particularly, active member 403 has that grid 403G is connected with sweep trace 402, source electrode 403S and data line 401 are connected, drain 403D and channel layer 403C between grid 403G and source electrode 403S/ drain electrode 403D.The active member 403 of present embodiment is an example with the bottom-gate amorphous silicon film transistor, certainly, have in the affiliated technical field and know that usually the knowledgeable also can use in top grid polycrystalline silicon thin film transistor (TFT) and the appropriate change active member other relative positions relations in the structure and present embodiment.Promptly, the structure of active member is not to be used for limiting interest field of the present invention yet.
Last capacitance electrode 4011 is connected with drain electrode 403D and forms storage capacitors with following capacitance electrode 4021.Dielectric layer 406 covers said elements substantially comprehensively and has a contact hole H and exposes drain electrode 403D.Pixel electrode 404 is arranged on the dielectric layer 406 and by contact hole H and drain electrode 403D and electrically connects.
The 3rd embodiment and first embodiment different being in, auxiliary electrode 4022 and sweep trace 402,402 ' and following capacitance electrode 4021 formation one earlier simultaneously conductive layer in advance, patterning forms again.What need pay special attention to is, corresponding this pixel auxiliary electrode 4022 electrically connect with sweep trace 402 ' and do not electrically connect with sweep trace 402, that is to say, auxiliary electrode 4022 can be (upper level) sweep trace 402 ' extended structure, so auxiliary electrode 4022 is identical with the current potential of sweep trace 402 '.For example, sweep trace 402 ' receives scan voltage, and scanning voltage is-10 volts to 30 volts, and preferable then is-8 volts to 28 volts, thus auxiliary electrode 4022 receptions boosting voltage just be-10 volts to 30 volts, preferable then is-8 volts to 28 volts.
Be positioned between two pixels auxiliary electrode 4022 be shaped as a H word shape, other embodiment auxiliary electrode shape also can be a strip and a H word shape one of them or its combination.In other words, viewable design and demand change auxiliary electrode shape, can in order to reach the present invention purpose auxiliary electrode structure all can use, do not limit to.
Please refer to Fig. 7 c, display panels 4 comprises active array substrate 40, the electrode base board 41 shown in Fig. 7 a and is arranged at liquid crystal layer therebetween 42.
Liquid crystal layer 42 comprises a plurality of liquid crystal molecules and a plurality of ion, and wherein, liquid crystal molecule has an initial voltage and a saturation voltage, and a predetermined ratio of ion is positioned at non-display area NA.
The structure of electrode base board 41 is roughly identical with electrode base board 21 among first embodiment, does not repeat them here.Common electrode 414 receives energising altogether and presses, and wherein, the absolute value of the difference of boosting voltage and common electric voltage is less than the starting potential of liquid crystal molecule.For example, the absolute value of the difference of boosting voltage and common electric voltage is less than or equal to 1 volt, also can be 3 volts to 20 volts.
Auxiliary electrode 4022 by active array substrate 40, can make in the liquid crystal layer 42, respective pixel district A has different toppling directions with the interior liquid crystal molecule of non-display area NA, so ion 120 can be limited in the non-display area NA, so picture picture displayed inequality or ghost problem just can be enhanced.
The 4th embodiment
Fig. 8 a, Fig. 8 b, Fig. 8 c are respectively the top view of the electrode base board 51 of the fourth embodiment of the present invention, the top view of display panels 5 and the sectional view of display panels 5.More specifically, Fig. 8 c describes along the sectional view of the profile line VIII-VIII ' of Fig. 8 b.In addition, for convenience of description, dot structure of the only clear demonstration of Fig. 8 a and Fig. 8 b.
Active array substrate 50 comprise a substrate 500, multi-strip scanning line 502, down capacitance electrode 5021, insulation course 505, many data lines 501, active members 503, go up capacitance electrode 5011, dielectric layer 506 and a plurality of pixel electrode 504.Sweep trace 502 reaches down, and capacitance electrode 5021 all is formed in the substrate 500.Insulation course 505 whole substrate 500, sweep trace 502 and the following capacitance electrodes 5021 of covering.Data line 501 is formed on the insulation course 505.
Active member 503 is formed in the substrate 500, and each active member 203 correspond to sweep trace 202 one of them, data line 201 one of them, and electrically connect with corresponding scanning line 502 and data line 501.Particularly, active member 503 has that grid 503G is connected with sweep trace 502, source electrode 503S and data line 501 are connected, drain 503D and channel layer 503C between grid 503G and source electrode 503S/ drain electrode 503D.The active member 503 of present embodiment is an example with the bottom-gate amorphous silicon film transistor, certainly, have in the affiliated technical field and know that usually the knowledgeable also can use in top grid polycrystalline silicon thin film transistor (TFT) and the appropriate change active member other relative positions relations in the structure and present embodiment.The structure of active member is not to be used for limiting interest field of the present invention.
Last capacitance electrode 5011 is arranged on the insulation course 505, and corresponding capacitance electrode 5021 down.Last capacitance electrode 5011 is connected with drain electrode 503D and forms storage capacitors with following capacitance electrode 5021.Dielectric layer 506 covers said elements substantially comprehensively and has contact hole H and exposes drain electrode 503D.Pixel electrode 504 is arranged on the dielectric layer 506, and electrically connects by contact hole H and drain electrode 503D.
Electrode base board 51 comprises substrate 510, masking structure 512, chromatic filter layer 511, protective seam 513 and common electrode 514.Masking structure 512 is arranged in the substrate 510.Chromatic filter layer 511 is arranged between substrate 210 and the common electrode 214, and crested structure 512 is separated.On the other hand, the edge of chromatic filter layer 511 can utilize masking structure 512 shadings, to avoid display panels 5 when the display frame, produces the problem of light leak.In addition, the substrate 510 of electrode base board 51 has a plurality of pixel regions, and each pixel region has a pixel wide and a length in pixels.
What must pay special attention to is, common electrode 514 is at corresponding masking structure 512 or the position of data line 501 has slit 5140, and wherein the width d of each slit 5140 is 1/20 times to 1/5 times of pixel wide, and preferable then is 1/10 times to 1/8 times.The width d of slit 5140 can be equal to or greater than the width of data line 501.The length L of slit 5140 can equal, less than or greater than length in pixels.
In other words, in non-display area NA,, just can have influence on the toppling direction of liquid crystal molecule in liquid crystal layer 52 respective pixel district A and the non-display area NA as long as common electrode 514 has slit or hollow structure.The shape of slit 5140 can be a ring-type, a strip, a U word shape and a ㄇ word shape one of them or its combination.The position of slit 5140 also can be corresponding to sweep trace 502 tops, and in other words, the position of slit 5140 promptly is positioned at interest field of the present invention as long as correspondence or part correspond to non-display area NA.In addition, common electrode 514 receives energising altogether and presses, and this common electric voltage is 0 volt to 12 volts, and preferable then is 3 volts to 9 volts.
By slit 5140 corresponding to non-display area NA, can make liquid crystal layer 52 respective pixel district A have different toppling directions with the interior liquid crystal molecule of non-display area NA, so ion 120 can be limited in the non-display area NA, so picture picture displayed inequality or ghost problem just can be enhanced.
The 5th embodiment
Fig. 9 a, Fig. 9 b, Fig. 9 c are respectively the top view of the electrode base board 61 of the fifth embodiment of the present invention, the top view of display panels 6 and the sectional view of display panels 6.Particularly, Fig. 9 c describes along the sectional view of the profile line IX-IX ' of Fig. 9 b.For convenience of description, dot structure of the only clear demonstration of Fig. 9 a and Fig. 9 b.
Active array substrate 60 comprise a substrate 600, multi-strip scanning line 602, down capacitance electrode 6021, insulation course 605, many data lines 601, active members 603, go up capacitance electrode 6011, dielectric layer 606 and a plurality of pixel electrode 604.Sweep trace 602 and capacitance electrode 6021 all are formed in the substrate 600.Insulation course 605 integral body cover substrates 600, sweep trace 602, following capacitance electrode 6021 and cover voltage connection gasket 6020.Data line 601 is formed on the insulation course 605.
Active member 603 is formed in the substrate 600, and each active member 203 correspond to sweep trace 202 one of them, data line 201 one of them, and electrically connect with corresponding scanning line 602 and data line 601.Particularly, active member 603 has that grid 603G is connected with sweep trace 602, source electrode 603S and data line 601 are connected, drain 603D and channel layer 603C between grid 603G and source electrode 603S/ drain electrode 603D.The active member 603 of present embodiment is an example with the bottom-gate amorphous silicon film transistor, certainly, have in the affiliated technical field and know that usually the knowledgeable also can use in top grid polycrystalline silicon thin film transistor (TFT) and the appropriate change active member other relative positions relations in the structure and present embodiment.Promptly, the structure of active member is not to be used for limiting interest field of the present invention yet.
Last capacitance electrode 6011 is positioned on the insulation course 605 and corresponding capacitance electrode 6021 down, and last capacitance electrode 6011 is connected with drain electrode 603D and forms storage capacitors with following capacitance electrode 6021.Dielectric layer 606 covers said elements substantially comprehensively and has contact hole H and exposes drain electrode 603D.Pixel electrode 604 is positioned on this dielectric layer 606 and by contact hole H and drain electrode 603D and electrically connects.
Electrode base board 61 comprises substrate 610, masking structure 612a, 612b, protective seam 613 and common electrode 614.Masking structure 612a, 612b are arranged in the substrate 610.Chromatic filter layer 611 is arranged between substrate 610 and the common electrode 614, and crested structure 612a, 612b separate.On the other hand, the edge of chromatic filter layer 611 can utilize masking structure 612a, 612b shading, to avoid display panels 6 when the display frame, produces the problem of light leak.In addition, the substrate 610 of electrode base board 61 has a plurality of pixel regions, and each pixel region has a pixel wide and a length in pixels.
What must pay special attention to is that shown in Fig. 9 c, the common electrode 614 that corresponds to masking structure 612b has slit 6140 masking structure 612b is come out.It is a plurality of blocks that masking structure is separated common electrode 614.Cover voltage connection gasket 6020 and receive external voltage, external voltage is sent to masking structure 612a and 612b via the web member 620 between active array substrate 60 and electrode base board 61, make these masking structures voltage be-30 volts to 30 volts.Understanding be can know by Fig. 9 c, voltage connection gasket 6020, web member 620 and masking structure 612a covered for electrically connecting.
Yet, it is described to provide voltage to be not limited to present embodiment to the mode of masking structure 612a, 612b, also can only utilize the voltage connection gasket to be set on electrode base board 61 or voltage source provides voltage to masking structure 612a, 612b, so just web member 620 need be set.The material of these masking structures 612a, 612b comprises metal and other opaque conductive materials one of them or its combination, and metal comprises chromium, evanohm and other opaque conducting metals one of them or its combination.
These masking structures 612a, 612b length be length in pixels 1/20 times to 1 times, width be pixel wide 1/20 times to 1 times and thickness be 0.01 micron to 5 microns.In addition, for example, common electrode 614 voltage and masking structure 612a, 612b voltage difference absolute value be 2 volts and 20 volts.
By masking structure 612a, 612b corresponding to non-display area NA, because of masking structure 612a, 612b have voltage, so in liquid crystal layer 62 respective pixel district A and the non-display area NA different pressure reduction is arranged, respective pixel district A has different toppling directions with the interior liquid crystal molecule of non-display area NA, so ion 120 can be limited in the non-display area NA, so picture picture displayed inequality or ghost problem just can be enhanced.
The 6th embodiment
Figure 10 a, Figure 10 b, Figure 10 c are respectively the top view of the active array substrate 70 of the sixth embodiment of the present invention, the top view of display panels 7 and the sectional view of display panels 7.Particularly, Figure 10 c describes along the sectional view of the profile line X-X ' of Figure 10 b.For convenience of description, dot structure of the only clear demonstration of Figure 10 a and Figure 10 b.
Active array substrate 70 comprises a substrate 700, multi-strip scanning line 702, auxiliary electrode 7040, time capacitance electrode 7021, insulation course 705, many data lines 701, active member 703, last capacitance electrode 7011, dielectric layer 706, a plurality of pixel electrode 704 and boosting voltage connection gaskets 7020.Sweep trace 702, auxiliary electrode 7040 and following capacitance electrode 7021 all are formed in the substrate 700. Auxiliary electrode 7040 and 704 while of pixel electrode patterning.Insulation course 705 whole substrate 700, sweep trace 702 and the following capacitance electrodes 7021 of covering.Data line 701 is formed on the insulation course 705.
Active member 703 is formed in the substrate 700, and each active member 203 correspond to sweep trace 202 one of them, data line 201 one of them, and electrically connect with corresponding scanning line 702 and data line 701.Active member 703 has that grid 703G is connected with sweep trace 702, source electrode 703S and data line 701 are connected, drain 703D and channel layer 703C between grid 703G and source electrode 703S/ drain electrode 703D.Active member 703 is an example with the bottom-gate amorphous silicon film transistor, certainly, have in the affiliated technical field and know that usually the knowledgeable also can use in top grid polycrystalline silicon thin film transistor (TFT) and the appropriate change active member other relative positions relations in the structure and present embodiment.Also promptly, active member structure be not be used for limiting the present invention interest field.
Last capacitance electrode 7011 is connected with drain electrode 703D and forms storage capacitors with following capacitance electrode 7021.Dielectric layer 706 covers said elements substantially comprehensively and has a contact hole H and exposes drain electrode 703D.Pixel electrode 704 is positioned on the dielectric layer 706 and by contact hole H and drain electrode 703D and electrically connects.Boosting voltage connection gasket 7020 can with sweep trace 702, grid 703G and/or down capacitance electrode 7021 form for same layer patternization, boosting voltage connection gasket 7020 receives the boosting voltage that outsides provide.
The structure of electrode base board 71 is roughly identical with electrode base board 21 among first embodiment, does not repeat them here.Common electrode 714 receives energising altogether and presses, and for example, the absolute value of the difference of boosting voltage and common electric voltage can be less than or equal to 1 volt, also can be 3 volts to 20 volts.
Please referring again to Figure 10 a, auxiliary electrode 7040 be shaped as a ring-type, but other embodiment also auxiliary electrode can be designed to U word shape and ㄇ word shape one of them, corresponding basically non-display area NA.What must pay special attention to is, auxiliary electrode 7040 electrically connects with boosting voltage connection gasket 7020 by contact hole H ', so auxiliary electrode 7040 reception boosting voltages, wherein boosting voltage is-30 volts to 30 volts, and preferable then is-10 volts to 25 volts.
Auxiliary electrode 7022 by active array substrate 70, can make liquid crystal layer 72 respective pixel district A have different toppling directions with the interior liquid crystal molecule of non-display area NA, so ion 120 can be limited in the non-display area NA, so picture picture displayed inequality or ghost problem just can be enhanced.
The 7th embodiment
Figure 11 a to Figure 11 c is respectively the top view of the active array substrate 80 of the seventh embodiment of the present invention, the top view of display panels 8 and the sectional view of display panels 8.Particularly, Figure 11 c describes along the sectional view of the profile line XI-XI ' of Figure 11 b.For convenience of description, dot structure of the only clear demonstration of Figure 11 a and Figure 11 b.
Active array substrate 80 comprise a substrate 800, multi-strip scanning line 802, auxiliary electrode 8040, down capacitance electrode 8021, insulation course 805, many data lines 801, active members 803, go up capacitance electrode 8011, dielectric layer 806 and a plurality of pixel electrode 804.Sweep trace 802, auxiliary electrode 8040 reach down, and capacitance electrode 8021 all is formed in the substrate 800.Auxiliary electrode 8040 and pixel electrode 804 be patterning and be same one deck simultaneously.Insulation course 805 whole substrate 800, sweep trace 802 and the following capacitance electrodes 8021 of covering.Data line 801 is formed on the insulation course 805.
Active member 803 is formed in the substrate 800, and each active member 203 correspond to sweep trace 202 one of them, data line 201 one of them, and electrically connect with corresponding scanning line 802 and data line 801.Active member 803 has that grid 803G is connected with sweep trace 802, source electrode 803S and data line 801 are connected, drain 803D and channel layer 803C between grid 803G and source electrode 803S/ drain electrode 803D.The active member 803 of present embodiment is an example with the bottom-gate amorphous silicon film transistor, certainly, have in the affiliated technical field and know that usually the knowledgeable also can use in top grid polycrystalline silicon thin film transistor (TFT) and the appropriate change active member other relative positions relations in the structure and present embodiment.Promptly, the structure of active member is not to be used for limiting interest field of the present invention yet.
Last capacitance electrode 8011 is connected with drain electrode 803D and forms storage capacitors with following capacitance electrode 8021.Dielectric layer 806 covers said elements substantially comprehensively and has a contact hole H and exposes drain electrode 803D.Pixel electrode 804 is positioned on the dielectric layer 806 and by contact hole H and drain electrode 703D and electrically connects.
The structure of electrode base board 81 is roughly identical with electrode base board 21 among first embodiment, does not repeat them here.Common electrode 814 receives energising altogether and presses, and for example, the absolute value of the difference of this boosting voltage and this common electric voltage can be less than or equal to 1 volt, also can be 3 volts to 20 volts.
Please referring again to Figure 11 a, auxiliary electrode 8040 be shaped as a ring-type, but other embodiment auxiliary electrode can be designed to U word shape and ㄇ word shape one of them, corresponding basically non-display area NA.What must pay special attention to is, different with the 6th embodiment, auxiliary electrode 8040 electrically connects with following capacitance electrode 8021 by contact hole H ', so auxiliary electrode 7040 receive capacitance electrodes 8021 down capacitance voltage with as be auxiliary electrode 7040 boosting voltage, wherein capacitance voltage is-30 volts to 30 volts, so boosting voltage is-30 volts to 30 volts.
Auxiliary electrode 8022 by active array substrate 80, can make the liquid crystal molecule of liquid crystal layer 82 respective pixel district A and non-display area NA have different toppling directions, so ion 120 can be limited in the non-display area NA, so picture picture displayed inequality or ghost problem just can be enhanced.
The 8th embodiment
Figure 12 a, Figure 12 b, Figure 12 c are respectively the top view of the active array substrate 90 of the eighth embodiment of the present invention, the top view of display panels 9 and the sectional view of display panels 9.Particularly, Figure 12 c describes along the sectional view of the profile line XII-XII ' of Figure 12 b.For convenience of description, dot structure of the only clear demonstration of Figure 12 a and Figure 12 b.
Active array substrate 90 comprise substrate 900, multi-strip scanning line 902a, 902b, auxiliary electrode 9040, down capacitance electrode 9021, insulation course 905, many data lines 901, active members 903, go up capacitance electrode 9011, dielectric layer 906 and a plurality of pixel electrode 904. Sweep trace 902a, 902b are formed in the substrate 800, and be all sweep trace 902a the upper level sweep trace.Auxiliary electrode 9040 and pixel electrode 904 be patterning and be same one deck simultaneously, and is formed in the substrate 900.Following capacitance electrode 9021 is formed in the substrate 900.Insulation course 905 whole substrate 900, sweep trace 902a, sweep trace 902b and the following capacitance electrodes 9021 of covering.Data line 901 is formed on the insulation course 905.
Active member 903 is formed in the substrate 900, and each active member 203 correspond to sweep trace 202 one of them, data line 201 one of them, and electrically connect with corresponding scanning line 902a and data line 901.Active member 903 has that grid 903G is connected with sweep trace 902, source electrode 903S and data line 901 are connected, drain 903D and channel layer 903C between grid 903G and source electrode 903S/ drain electrode 903D.Present embodiment active member 903 be example with the bottom-gate amorphous silicon film transistor, certainly, have in the affiliated technical field and know that usually the knowledgeable also can use in top grid polycrystalline silicon thin film transistor (TFT) and the appropriate change active member other relative positions relations in the structure and present embodiment.Also promptly, active member structure be not be used for limiting the present invention interest field.
Last capacitance electrode 9011 is connected with drain electrode 903D and forms storage capacitors with following capacitance electrode 9021.Dielectric layer 906 covers said elements substantially comprehensively and has a contact hole H and exposes drain electrode 903D.Pixel electrode 904 is positioned on this dielectric layer 906 and by this contact hole H and this drain electrode 903D and electrically connects.
The structure of electrode base board 91 is roughly identical with electrode base board 21 among first embodiment, does not repeat them here.Common electrode 914 receives energising altogether and presses, and for example, the absolute value of the difference of this boosting voltage and this common electric voltage can be less than or equal to 1 volt, also can be 3 volts to 20 volts.
Please referring again to Figure 12 a, auxiliary electrode 9040 be shaped as a ㄇ word shape, but other embodiment viewable design and demand with auxiliary electrode be designed to U word shape and ring-type one of them, corresponding basically non-display area NA.What must pay special attention to is, different with the 7th embodiment, auxiliary electrode 9040 electrically connects by contact hole H ' and sweep trace 902b, so auxiliary electrode 9040 received scanline 902b scanning voltage with as be auxiliary electrode 9040 boosting voltage, wherein, scanning voltage is-10 volts to 30 volts, so boosting voltage is-10 volts to 30 volts.Sweep trace 902b be sweep trace 902a the upper level sweep trace, so because the mistiming relation, the voltage that auxiliary electrode 9040 and sweep trace 902a receive, can't be identical at identical time point, so by corresponding to non-display area NA auxiliary electrode 9040, because of auxiliary electrode 9040 has boosting voltage, so in liquid crystal layer 92 respective pixel district A and the non-display area NA different pressure reduction is arranged, respective pixel district A and non-display area NA liquid crystal molecule have different toppling directions, so ion 120 can be limited in the non-display area NA, thus the picture demonstration picture inequality or ghost problem just can be enhanced.
In sum, the present invention is mainly providing a kind of active array substrate, electrode base board and display panels, arrangement mode in order to the liquid crystal molecule in the control liquid crystal layer, make the particle in the liquid crystal layer be limited in the specific region, non-display area for example, avoid pixel region that too much particle is arranged, influence the optical characteristics of the liquid crystal molecule that is positioned at pixel region in the liquid crystal layer, to reach the purpose of avoiding picture inequality or ghost problem.
Though the present invention discloses as above with preferred embodiment; right its is not in order to limit the present invention; have in the technical field under any and know the knowledgeable usually; without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention is as the criterion when looking the claim person of defining.

Claims (6)

1. a display panels is characterized in that, this display panels comprises: an active array substrate, an electrode base board and a liquid crystal layer,
A wherein said active array substrate comprises:
One substrate;
The multi-strip scanning line is arranged in the described substrate;
Many data lines are vertical with described sweep trace;
A plurality of pixel electrodes;
A plurality of active members, each described active member correspond to described sweep trace one of them, described data line one of them and described pixel electrode one of them, each described active member electrically connects to define a pixel region and a non-display area with corresponding described sweep trace, data line and pixel electrode respectively; And
At least one auxiliary electrode is arranged in the described substrate, and is positioned at described non-display area, and at least one described auxiliary electrode is in order to receive a boosting voltage, and wherein this boosting voltage is-30 volts to 30 volts;
One electrode base board comprises:
One substrate;
One common electrode is arranged in the substrate of described electrode base board, presses in order to receive energising altogether;
Wherein said liquid crystal layer is arranged between described active array substrate and the described electrode base board, comprises: a plurality of liquid crystal molecules, have an initial voltage and a saturation voltage, and a plurality of ion;
The absolute value of the difference of wherein said boosting voltage and common electric voltage is less than the starting potential of liquid crystal molecule, in described liquid crystal layer, the liquid crystal molecule that corresponds to pixel region and non-pixel region has different toppling directions, so that described ion is limited in the non-display area.
2. display panels as claimed in claim 1, it is characterized in that, at least one described auxiliary electrode and described pixel electrode are insulated from each other and be arranged at same one deck, at least one described auxiliary electrode be shaped as a ring-type, a strip, a U word shape and a ㄇ word shape one of them, described active array substrate also comprises a capacitance electrode, be arranged in the described substrate, described capacitance electrode is in order to receive a capacitance voltage, and wherein this capacitance voltage is-30 volts to 30 volts.
3. display panels as claimed in claim 1 is characterized in that, this active array substrate also comprises:
One capacitance electrode is arranged in the described substrate, and wherein this capacitance electrode and described at least one auxiliary electrode electrically connect.
4. display panels as claimed in claim 1 is characterized in that, this active array substrate also comprises:
One capacitance electrode is arranged in the described substrate, and wherein this capacitance electrode and described at least one auxiliary electrode are insulated from each other and be arranged at same one deck.
5. display panels as claimed in claim 1 is characterized in that, described at least one auxiliary electrode and one of them electric connection of described sweep trace.
6. display panels as claimed in claim 1 is characterized in that, described at least one auxiliary electrode and described sweep trace are insulated from each other, and is arranged at same one deck.
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