CN101252515A - On-chip network chip - Google Patents
On-chip network chip Download PDFInfo
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- CN101252515A CN101252515A CNA2008100661352A CN200810066135A CN101252515A CN 101252515 A CN101252515 A CN 101252515A CN A2008100661352 A CNA2008100661352 A CN A2008100661352A CN 200810066135 A CN200810066135 A CN 200810066135A CN 101252515 A CN101252515 A CN 101252515A
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Abstract
The invention discloses a network-on-chip chip. At least two layers are arranged in the interior of a chip; at least a processing unit and an interconnection node are arranged in each layer; the network-on-chip chip also includes an interlayer bus whose both ends are connected with the interconnection node respectively; the processing unit is connected with the interconnection node; the processing units in the layers are communicated with each other through the interconnection node and the interlay bus. The network-on-chip chip can reduce the number of connecting lines and length between the processing units in great quantity, reduce the interference between the connecting lines and the interface applied to the connecting lines by other signals and guarantee the signal integrity between the processing units and the high efficiency of communication. The network-on-chip chip proposes the multi-layer structure of the chip creatively so that the chip area is reduced; the cost of the chip is reduced and the implementation of the network-on-chip chip is easier.
Description
Technical field
The present invention relates to a kind of on-chip network chip (Network On Chip is called for short NOC).
Background technology
Along with the fast development of microelectric technique, earth-shaking variation has also taken place in chip design.From application-specific integrated circuit (ASIC) (Application Specific Integrated Circuit, be called for short ASIC) to SOC (system on a chip) (System On Chip, be called for short SOC), arrive NOC in recent years again, the integrated level of chip is more and more higher, single chip not only can be realized the function of a mini system, and can realize the function of complication system.The increase of single-chip disposal ability also has benefited from the variation of chip body system structure except being subjected to the microelectronic process engineering Influence and Development.ASIC mainly lays particular emphasis on functions of modules, and SOC has developed into the architectural framework based on STD bus.But along with increasing of functional process unit, more and more difficult based on the SOC design of bus, subject matter is the communication capacity deficiency of bus architecture, has been unable to catch up with the demand of system developments such as communication in the present age, multimedia.NOC uses for reference computer networking technology, on single chip, construct a whole network, each processing unit is coupled together, in conjunction with the parallel or stream treatment method of different processing units, and give full play to the parallel communications function of network, the data-handling capacity of chip is obtained significantly promote.
Now, microelectric technique has entered the deep-submicron epoch, just develops towards nanometer technology.Can predict, the integrated level of following chip and operating frequency also can continue to improve, and based on network NOC chip can not make an exception.Existing NOC chip all adopts the surface silicon technology, each circuit module plane distribution.That is: be distributed with a lot of processors in a plane, each processor carries out communication by the network connectivity in this plane.Has only a planar network in the existing NOC chip.But growth along with network connectivity in the NOC chip, and increase shortening of the signal wavelength bring because of operating frequency, the physical model of chip internal line more and more is similar to antenna, not only can disturb the signal on other line, the also as easy as rolling off a log interference that is subjected to other signal, the integrality of signal will become a challenge.
Summary of the invention
The present invention is exactly in order to overcome above deficiency, to have proposed a kind of less on-chip network chip that disturbs.
Technical problem of the present invention is solved by following technical scheme: a kind of on-chip network chip, be provided with at least two layers at a chip internal, be provided with at least one processing unit and an interconnecting nodes in every layer, described on-chip network chip also comprises the interlayer bus, described interlayer bus two ends link to each other with interconnecting nodes respectively, described processing unit links to each other with interconnecting nodes, carries out communication by interconnecting nodes and interlayer bus between each layer processing unit.
Preferably, processing unit and interconnecting nodes in every layer have at least two respectively, link to each other with interconnecting nodes by a layer internal bus between each processing unit, and be continuous by layer internal bus between each interconnecting nodes.
Described interconnecting nodes is switch or router.
Described interlayer bus is one-way transmission bus or transmitted in both directions bus.
The beneficial effect that the present invention is compared with the prior art is: the present invention is provided with multilayer at chip internal, and makes the processing unit communication mutually of each layer by the interlayer bus, thereby can constitute the network-on-chip structure of a huge three-dimensional.On-chip network chip of the present invention can reduce wiring quantity and the length between processing unit in a large number, reduces the interference between line, reduces the interference of other signal to line, guarantees the integrality of the signal between processing unit, the communication efficiency height.On-chip network chip of the present invention has creatively proposed the structure of multilayer in the chip, more can reduce chip area, reduces the cost of chip, and implement also more easy.
Description of drawings
Fig. 1 is the structural representation of the specific embodiment of the invention one;
Fig. 2 is the structural representation of the specific embodiment of the invention two.
Embodiment
Also in conjunction with the accompanying drawings the present invention is described in further details below by concrete execution mode.
Embodiment one
As shown in Figure 1, a kind of on-chip network chip is provided with the ground floor 1 and the second layer 2 at chip internal, and the ground floor 1 and the second layer 2 are represented two physical layers (i.e. two circuit layers) of chip respectively.Be provided with first processing unit 14 and first interconnecting nodes 13 in the ground floor 1, also be provided with second processing unit 24 and second interconnecting nodes 23 in the second layer 2, described on-chip network chip also comprises interlayer bus 6.Interlayer bus 6 two ends link to each other with second interconnecting nodes 23 with first interconnecting nodes 13 respectively, and first processing unit 14 links to each other with first interconnecting nodes 13, and second processing unit 24 links to each other with second interconnecting nodes 23.24 of first processing unit 14 and second processing units pass through first interconnecting nodes 13, interlayer bus 6 and 23 communications of second interconnecting nodes.Described first interconnecting nodes 13 and second interconnecting nodes 23 can be controlled the communication of 24 of first processing unit 14 and second processing units together, as: to signal carry out that packet filtering, packet forward, priority are selected, multiplexing, encryption, compression etc.
Described first processing unit 14 has at least two, and 14 of each first processing units pass through ground floor internal bus 15 and link to each other with first interconnecting nodes 13, the communication that described first interconnecting nodes 13 is gone back 14 of each first processing units of may command.Described first interconnecting nodes 13 also has at least two, and 13 of each first interconnecting nodes are continuous by ground floor internal bus 15.Described first processing unit 14, ground floor internal bus 15 and first interconnecting nodes 13 have been formed a two-dimensional network jointly.This two-dimensional network can be made by surperficial integrated technique.Described second processing unit 24 also has at least two, and 24 of each second processing units pass through second layer internal bus 25 and link to each other with second interconnecting nodes 23, the communication that described second interconnecting nodes 13 is gone back 24 of each second processing units of may command.Described second interconnecting nodes 23 also has at least two, and 23 of each second interconnecting nodes are continuous by second layer internal bus 25.Described second processing unit 24, second layer internal bus 25 and second interconnecting nodes 23 have been formed a two-dimensional network jointly.Described first interconnecting nodes 13 and second interconnecting nodes 23 can be switch or router.
Described interlayer bus 6 is one-way transmission bus or transmitted in both directions bus.An interlayer bus 6 is set between two interconnecting nodes to get final product.Interlayer bus 6 is passed through certain thickness chip layer, and the interconnection node on two different layers is coupled together.Can generate interlayer bus 6 by three-dimensional integrated technique.The actual trend of interlayer bus 6 is decided according to three-dimensional integrated technique.
Described first processing unit 14, second processing unit 24 can be isomorphisms, also can be isomeries, can be hardware modules, also can be processor cores.
On-chip network chip of the present invention adopts three-dimensional integrated technology, planar network in the existing NOC chip is become three-dimensional net structure, processing unit can the different level of vertical distribution in chip in, network connectivity in the on-chip network chip so of the present invention (the interlayer bus and the layer internal bus and) will significantly reduce, length also can correspondingly shorten.The interior number of plies of the amplitude that reduces and chip is directly proportional.
Embodiment two
As shown in Figure 2, the difference of this embodiment and embodiment one is: the on-chip network chip of this embodiment, be provided with three physical layers (that is: three circuit layers) at chip internal, and be respectively ground floor, the second layer and the 3rd layer.Be provided with first interconnecting nodes 13 in the described ground floor, be provided with in the described second layer in 23, the three layers of second interconnecting nodes and be provided with the 3rd interconnecting nodes 33.First interconnecting nodes 13 is connected with second interconnecting nodes 23 by bus 6a between ground floor, and is connected with interior a plurality of second interconnecting nodes 23 of the second layer 2.First interconnecting nodes 13 also is connected with the 3rd interconnecting nodes 33 by bus 6b between the second layer.Connecting the interlayer bus of single interconnecting nodes can be more than one the tunnel, that is to say that single interconnecting nodes can be connected with a plurality of interconnecting nodes of different layers, also can be connected with the interconnecting nodes on a plurality of different layers.But the interlayer bus that belongs between two interconnecting nodes of different layers has only one the tunnel.This road interlayer bus can one-way transmission, also can transmitted in both directions; The bus of one tunnel transmitted in both directions can be constructed by the bus of two-way one-way transmission.
Above content be in conjunction with concrete preferred implementation to further describing that the present invention did, can not assert that concrete enforcement of the present invention is confined to these explanations.As: on-chip network chip of the present invention obviously can also have four layers, five layers ....For the general technical staff of the technical field of the invention, without departing from the inventive concept of the premise, can also make some simple deduction or replace, all should be considered as belonging to protection scope of the present invention.
Claims (4)
1. on-chip network chip, it is characterized in that: be provided with at least two layers at a chip internal, be provided with at least one processing unit and an interconnecting nodes in every layer, described on-chip network chip also comprises the interlayer bus, described interlayer bus two ends link to each other with interconnecting nodes respectively, described processing unit links to each other with interconnecting nodes, carries out communication by interconnecting nodes and interlayer bus between each layer processing unit.
2. on-chip network chip according to claim 1, it is characterized in that: processing unit in every layer and interconnecting nodes have at least two respectively, link to each other with interconnecting nodes by layer internal bus between each processing unit, link to each other by layer internal bus between each interconnecting nodes.
3. on-chip network chip according to claim 1 and 2 is characterized in that: described interconnecting nodes is switch or router.
4. on-chip network chip according to claim 1 and 2 is characterized in that: described interlayer bus is one-way transmission bus or transmitted in both directions bus.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA2008100661352A CN101252515A (en) | 2008-03-21 | 2008-03-21 | On-chip network chip |
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| Application Number | Priority Date | Filing Date | Title |
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| CNA2008100661352A CN101252515A (en) | 2008-03-21 | 2008-03-21 | On-chip network chip |
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| CN101252515A true CN101252515A (en) | 2008-08-27 |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101483614B (en) * | 2008-10-20 | 2011-07-27 | 电子科技大学 | Method for constructing network on three-dimensional chip |
| CN101388834B (en) * | 2008-10-20 | 2012-05-30 | 电子科技大学 | Method for constructing network on three-dimensional chip |
| CN104243330A (en) * | 2014-10-10 | 2014-12-24 | 南京大学 | Low-density vertical interconnection oriented three-dimensional on-chip network router |
| CN107317773A (en) * | 2017-07-03 | 2017-11-03 | 辽宁科技大学 | A kind of network-on-chip communication interface and communication means |
| CN107451072A (en) * | 2016-05-30 | 2017-12-08 | 三星电子株式会社 | Computing system and its operating method with instant encryption device |
| CN112311701A (en) * | 2019-07-29 | 2021-02-02 | 奥塔索克技术有限公司 | Analog broadcasting in network on chip |
-
2008
- 2008-03-21 CN CNA2008100661352A patent/CN101252515A/en active Pending
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101483614B (en) * | 2008-10-20 | 2011-07-27 | 电子科技大学 | Method for constructing network on three-dimensional chip |
| CN101388834B (en) * | 2008-10-20 | 2012-05-30 | 电子科技大学 | Method for constructing network on three-dimensional chip |
| CN104243330A (en) * | 2014-10-10 | 2014-12-24 | 南京大学 | Low-density vertical interconnection oriented three-dimensional on-chip network router |
| CN107451072A (en) * | 2016-05-30 | 2017-12-08 | 三星电子株式会社 | Computing system and its operating method with instant encryption device |
| CN107317773A (en) * | 2017-07-03 | 2017-11-03 | 辽宁科技大学 | A kind of network-on-chip communication interface and communication means |
| CN107317773B (en) * | 2017-07-03 | 2020-03-27 | 辽宁科技大学 | On-chip network communication interface and communication method |
| CN112311701A (en) * | 2019-07-29 | 2021-02-02 | 奥塔索克技术有限公司 | Analog broadcasting in network on chip |
| CN112311701B (en) * | 2019-07-29 | 2024-03-19 | 西门子工业软件有限公司 | Analog broadcasting in a network on chip |
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Open date: 20080827 |