CN101252127A - De-coupling capacitance circuit - Google Patents
De-coupling capacitance circuit Download PDFInfo
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Abstract
A decoupling capacitor circuit comprises a plurality of deep trench capacitors serially connected with one another and a plurality of push-pull circuits. The decoupling capacitor circuit utilizes the push-pull circuits to control the step voltage of each deep trench capacitor, so as to ensure that the step voltage cannot be affected by the defect (leakage current) of the deep trench capacitors or the bias of parasitic elements.
Description
Technical field
The invention relates to a kind of de-coupling capacitance circuit, particularly about a kind of high pressure resistant de-coupling capacitance circuit of realizing with deep-channel capacitor.
Background technology
Science and technology makes rapid progress, constantly progressive, people require also more and more higher for the integrated level of crystal grain (die), function etc.The power supply (power) of general crystal grain is that the decoupling capacitance (power de-coupling capacitor) that adopts gate oxidation electric capacity (gate oxide capacitor) to be used as power supply uses.But, therefore do not conformed with the requirement of high integration now because gate oxidation electric capacity can occupy bigger chip area (die area).
Summary of the invention
At the problems referred to above, a purpose of the present invention is providing a kind of de-coupling capacitance circuit, and can reduce the occupied too much chip area of gate oxidation electric capacity.
One embodiment of the invention provide a kind of de-coupling capacitance circuit.This de-coupling capacitance circuit includes the deep-channel capacitor of a plurality of series connection.Each deep-channel capacitor comprises at least one deep-channel capacitor born of the same parents (cell).Wherein, the junction of per two deep-channel capacitors forms a node, and each node is to be biased in the predeterminated voltage scope.The de-coupling capacitance circuit of this design is applied in the crystal grain, then can utilize a plurality of deep-channel capacitors on average to share high voltage, and promote the voltage endurance capability of whole deep-channel capacitor, solve problem that prior art gate oxidation electric capacity occupies big chip area, with the problem of the withstand voltage deficiency of single deep-channel capacitor.
Another embodiment of the present invention provides a kind of de-coupling capacitance circuit.This de-coupling capacitance circuit includes N deep-channel capacitor, one group of voltage divider and N-1 push-pull circuit of series connection mutually, and wherein N is the positive integer greater than 1.The serial connection place of per two deep-channel capacitors forms N-1 node altogether.Voltage divider is in order to produce the individual reference voltage of 2 (N-1).And N-1 push-pull circuit optionally adjusted the magnitude of voltage of this N-1 node according to this 2 (N-1) individual reference voltage, and the magnitude of voltage of using this N-1 node is controlled in the preset range.Design according to this equates the cross-pressure that makes each deep-channel capacitor of series connection or becomes a preset ratio, is not influenced by contingent parasitic antenna of deep-channel capacitor or electric capacity defective (leakage current).The design of this circuit can solve prior art, electric capacity problem of withstand voltage equally, and further solves the electric capacity cross-pressure change problem that deep-channel capacitor may be caused because of parasitic antenna or electric capacity defective.
Description of drawings
Figure 1A shows the schematic diagram of the de-coupling capacitance circuit of one embodiment of the invention;
Figure 1B shows the oscillogram of the de-coupling capacitance circuit of Figure 1A;
Fig. 1 C shows that the de-coupling capacitance circuit of Figure 1A is subjected to another oscillogram of parasitic bipolar transistor effects;
Fig. 1 D shows the section of structure of the de-coupling capacitance circuit of Figure 1A;
Fig. 1 E shows the equivalent circuit diagram of the parasitic transistor of Figure 1A de-coupling capacitance circuit;
Fig. 2 A shows the schematic diagram of the de-coupling capacitance circuit of one embodiment of the invention;
The oscillogram of the de-coupling capacitance circuit of Fig. 2 B displayed map 2A;
The equivalent circuit diagram of the parasitic transistor of Fig. 3 A demonstration Figure 1A, 2A de-coupling capacitance circuit and the resistance of simulated defect;
Fig. 3 B shows the oscillogram of the de-coupling capacitance circuit of 3A, 1A, 2A figure;
Fig. 4 is presented at the oscillogram that simulates under three kinds of specific settings.
Description of reference numerals:
10,20-de-coupling capacitance circuit; C10, C20, C30, C11, C21, C31-deep-channel capacitor; PP1, PP2-push-pull circuit; OP1, OP2-operational amplifier; T1, T2, T3, P1, N1-transistor; Rf, R1, R2, R3, Δ R-resistance; The div-voltage divider.
Embodiment
Present deep-channel capacitor (Deep Trench capacitor, DT capacitor) is in the memory cell (cell) that is applied to dynamic random access memory (DRAM), and the area of deep-channel capacitor is little, capacity is big.For example, in the processing procedure of a certain 0.11 micron dynamic random access memory, under same area, the capacitance size of deep-channel capacitor when layout can reach 56 times of general thick gate oxidation electric capacity, 37 times more than of general thin gate oxidation electric capacity, therefore, if can adopt deep-channel capacitor as decoupling capacitance, promptly replace gate oxidation electric capacity and use, then can reduce the occupied whole chip area of gate oxidation electric capacity in large quantities and the integrated level of raising crystal grain.
Because the memory cell of dynamic random access memory is the application that belongs to low voltage range, so that the thickness of most of deep-channel capacitors is designed is very thin, so its voltage that can bear very low.And if deep-channel capacitor is applied in power supply high voltage range such as (Power) when using as decoupling capacitance, it just can be because of can't bearing high voltage, and produce the problem that reliability (reliability) reduces.
Can't bear high-tension problem in order to solve deep-channel capacitor, provide a kind of N of including a high pressure resistant de-coupling capacitance circuit of the deep-channel capacitor of series connection mutually according to one embodiment of the invention, wherein N is the positive integer greater than 1.This de-coupling capacitance circuit utilizes the series connection of N deep-channel capacitor on average to share voltage, makes the withstand voltage raising of whole de-coupling capacitance circuit.Illustrate, shown in Figure 1A, an end of the de-coupling capacitance circuit 10 of one embodiment of the invention connects one first voltage level (high voltage level) HV, and the other end connects one second voltage level (low-voltage position standard or ground connection position standard) VSS.This de-coupling capacitance circuit 10 comprises one first deep-channel capacitor C10, one second deep-channel capacitor C20 and one the 3rd deep-channel capacitor C30.Each deep-channel capacitor C10, C20, C30 all include first end and second end.First end of the first deep-channel capacitor C10 connects the first voltage level HV, first end of its second end series connection (connections) second deep-channel capacitor C20, with formation node N10; First end of second end of second deep-channel capacitor C20 series connection (connections) the 3rd deep-channel capacitor C30, with formation node N20, and second end of the 3rd deep-channel capacitor C30 connects the second voltage level VSS.In this circuit, the predeterminated voltage V (N10) of node N10 and N20=2 * V (N20), promptly the cross-pressure on each deep-channel capacitor C10, C20, the C30 equates.
Be noted that, total N deep-channel capacitor of connecting mutually in another embodiment, then first end of N deep-channel capacitor is second end that connects the N-1 deep-channel capacitor, and second end of N deep-channel capacitor is to connect the second voltage level VSS.And wherein, above-mentioned each deep-channel capacitor is parallel with one another and constitute by a plurality of deep-channel capacitor born of the same parents.Certainly, if withstand voltage (tolerance) ability of single deep-channel capacitor born of the same parents of future development is enough strong, also may adopt single deep-channel capacitor born of the same parents to constitute this deep-channel capacitor.
Please refer to Figure 1A, suppose that the first voltage level HV equals 3.6V, the second voltage level VSS equals 0V.And hypothesis is applied to the voltage endurance capability of single deep-channel capacitor of DRAM memory cell only for 1.5V.Then as can be known, the dielectric (dielectric) of single deep-channel capacitor of script also can't bear the high voltage of 3.6V.And if the characteristic of each deep-channel capacitor C10, C20 of the de-coupling capacitance circuit 10 of one embodiment of the invention, C30 is all identical, C10=C20=C30=1250pF and voltage endurance capability also are 1.5V.Then with after three deep-channel capacitor C10, C20, the C30 series connection, under the normal condition, each deep-channel capacitor will on average be shared voltage 1.2V.Therefore, de-coupling capacitance circuit 10 of the present invention promptly can be applicable under the high voltage 3.6V, and the withstand voltage effect of whole deep-channel capacitor is improved, and then deep-channel capacitor can be applied in high voltage range and replace gate oxidation electric capacity, use as decoupling capacitance.So, can solve the problem that existing gate oxidation electric capacity occupies excessive chip area.
Under normal circumstances, three deep-channel capacitor C10, C20 of Figure 1A de-coupling capacitance circuit 10, the cross-pressure on the C30 should equate, are equal to 1.2V, and promptly node voltage V (N20) equals 1.2V, V (N10) and equals 2.4V, shown in Figure 1B.But because the deep-channel capacitor of each DRAM is made up of the deep-channel capacitor born of the same parents of many units, and some deep-channel capacitor born of the same parents can produce defective (defect) or because parasitic antenna in its processing procedure, causing leaking (leakage) electric current flows through and the cross-pressure on three deep-channel capacitor C10, C20, the C30 is dissimilated, for example the cross-pressure of capacitor C 10 becomes and equals that 2.25V, C20 become 0.9V, C30 becomes 0.45V, be that node voltage V (N20) equals 0.45V, V (N10) and equals 1.35V, shown in Fig. 1 C.Hence one can see that, and therefore the cross-pressure of deep-channel capacitor C10 too high (surpassing 1.2V) will burn.
The below origin cause of formation of unequal cross-pressure of above-mentioned three deep-channel capacitors of explanation and the settling mode of one embodiment of the invention.
Fig. 1 D is the section of structure that shows Figure 1A de-coupling capacitance circuit 10; This profile shows the series system of three deep-channel capacitor C10, C20, C30.And the structure of each deep-channel capacitor C10, C20, C30 is a prior art, no longer repeats to give unnecessary details.
Please also refer to Figure 1A, 1D, reach 1E; Fig. 1 E shows that deep-channel capacitor C10, C20, C30 divide the equivalent circuit diagram of other parasitic bipolar transistor (bipolar transistor) T1, T2, T3; By 1E figure as can be known, parasitic transistor T1, T2, T3 are the PNP transistor, respectively by P substrate (P-substrate), N well (N-Well), and embedded P well (Buried P-Well) formed.These parasitic bipolar transistor T1, T2, T3 cause the reason that the deep-channel capacitor leakage current produces, cross-pressure changes.As known in the figure, electric current I 1=2 * I0, and electric current I 2=I1+ (I1+I0)=2 * I0+3 * I0=5 * I0.Therefore, the cross-pressure on deep-channel capacitor C10, C20, the C30 is than V (C10): V (C20): V (C30)=I2: I1: I0=5: 2: 1.So, at HV=3.6V, under the situation of VSS=0, to cause the voltage of node N10 and N20 to offset downward (shift) near the current potential of ground connection (ground), V (C10)=2.25V, V (C20)=0.9V, V (C30)=0.45V, be V (N10)=1.35V, V (N20)=0.45V and then deep-channel capacitor (C10) is damaged because of cross-pressure is excessive, shown in Fig. 1 C.
For the contingent cross-pressure variation issue of the deep-channel capacitor that solves series connection, the invention provides the de-coupling capacitance circuit of another embodiment, it is to utilize active member to control the cross-pressure of each deep-channel capacitor of (adjustment) series connection, each cross-pressure is fixed in the default voltage range, shown in Fig. 2 A.This de-coupling capacitance circuit includes deep-channel capacitor, a N-1 push-pull circuit (push-pullcircuit) of the individual mutual series connection of N (N is a positive integer, and greater than 1) and comprises N resistance R 1～RN and one group of voltage divider of N-1 differential resistance Δ R (or can be described as voltage divider (divider)).Wherein, the serial connection place of per two deep-channel capacitors forms a common N-1 node; And this group voltage divider is in order to producing the individual reference voltage of 2 (N-1), and this N-1 push-pull circuit is optionally adjusted the magnitude of voltage of this N-1 node to default voltage range according to this 2 (N-1) individual reference voltage.
Be noted that the one group voltage divider div of de-coupling capacitance circuit 20 for comprising three deep-channel capacitor C11, C21, C31, two push-pull circuit PP1, PP2 and comprising three resistance R 1, R2, R3 and two differential resistance Δ R of example among this figure.And for the purpose of simplifying the description, be the equal and opposite in direction R1=R2=R3 of three resistance of hypothesis in the present embodiment.Certainly, the size of resistance R 1, R2, R3 also can become a preset ratio in another embodiment, and promptly it can change size according to demand.
First end of the first deep-channel capacitor C11 of the deep-channel capacitor of those series connection connects first voltage level (high voltage level) HV, and its second end forms a node N11 with first end series connection (connection) of the second deep-channel capacitor C21, and the magnitude of voltage of this node N11 is to be biased in one first predeterminated voltage V (N11); Second end of the second deep-channel capacitor C21 forms a node N21 with first end series connection (connection) of the 3rd deep-channel capacitor C31, and the magnitude of voltage of this node N21 is to be biased in one second predeterminated voltage V (N21).And second end of the 3rd deep-channel capacitor C31 connects second voltage level (low-voltage position standard or ground connection position standard) VSS.In the present embodiment, the position standard of predeterminated voltage should be V (N11)=2 * V (N21), and promptly the cross-pressure on each deep-channel capacitor C11, C21, the C31 equates.And among another embodiment, become a preset ratio as if resistance R 1, R2, R3, then predeterminated voltage V (N11), V (N21) also become corresponding ratio.
The end of push-pull circuit PP1 connects resistance R 1 is connected resistance R 2 and differential resistance Δ R with an end, the end of differential resistance Δ R the other end, its other end connected node N11.And push-pull circuit PP1 is when the voltage level change to take place at node N11, and it is accurate optionally the voltage of this node N11 to be adjusted to the position that approximates the first predeterminated voltage V (N11) according to the size of this variation.And the end of push-pull circuit PP2 connects resistance R 2 is connected resistance R 3 and this another differential resistance Δ R with an end, the end of another differential resistance Δ R the other end, its other end connected node N21.And push-pull circuit PP2 is when the voltage level change to take place at node N21, and it is accurate optionally the voltage of this node N21 to be adjusted to the position that approximates the second predeterminated voltage V (N21) according to the size of this variation.Wherein, each push-pull circuit PP1, PP2 all include a discharge cell (or a reduction voltage circuit) and a charhing unit (or a booster circuit).This discharge cell includes one first comparing unit and one first switch.Charhing unit includes one second comparing unit and a second switch.
Next be simplified illustration, only discuss with push-pull circuit PP1.
First comparing unit of this discharge cell (reduction voltage circuit) is to implement with operational amplifier OP1.The reverse input end of operational amplifier OP1 receives the first reference voltage Vr1, be Vr1=[(R2+R3+2 Δ R)/(R1+R2+R3+2 Δ R)] * HV, and the voltage on its non-inverting input receiving node N11, and the magnitude of voltage on this first reference voltage Vr1 and the node N11 relatively is to produce one first compare result signal Ru1.This first switch is to implement with transistor N1, its collector terminal connected node N11, source terminal connect the second voltage level VSS, and the gate terminal of this transistor N1 receives this compare result signal Ru1, and come optionally this node N11 to be discharged according to the first compare result signal Ru1, to reduce the magnitude of voltage of this node N11.
And second comparing unit of this charhing unit (booster circuit) is to implement with operational amplifier OP2, its reverse input end receives the second reference voltage Vr2, be Vr2=[(R2+R3+ Δ R)/(R1+R2+R3+2 Δ R)] * HV, and the voltage on its non-inverting input receiving node N11, and compare the magnitude of voltage on the second reference voltage Vr2 and the node N11, to produce one second compare result signal Ru2.Moreover, second switch is to implement with transistor P1, its source terminal connects the first voltage level HV, collector terminal connected node N11, and the gate terminal of transistor P1 receives the second compare result signal Ru2, and come optionally this node N11 to be charged according to the second compare result signal Ru2, to promote the magnitude of voltage of this node.Thus, magnitude of voltage on the node N11 will stop in [(R2+R3+2 Δ R)/(R1+R2+R3+2 Δ R)] * HV and [(R2+R3+ Δ R)/(R1+R2+R3+2 Δ R)] * HV interval because of the control of push-pull circuit PP1, and the magnitude of voltage that can reach this node N11 is controlled at the interior effect of a selectable scope that approximates predeterminated voltage V (N11).
In voltage divider div, resistance R 1 is to be placed between the discharge cell (or reduction voltage circuit) of the first voltage level HV and push-pull circuit PP1; Resistance R 2 is between the charhing unit (or booster circuit) of the discharge cell (or reduction voltage circuit) that is placed in push-pull circuit PP2 and push-pull circuit PP1, when de-coupling capacitance circuit has only two deep-channel capacitors, when promptly comprising a push-pull circuit PP1, resistance R 2 is to be placed between the charhing unit (or booster circuit) of the second voltage level VSS and push-pull circuit PP1.And this differential resistance Δ R is between the discharge cell (or reduction voltage circuit) and charhing unit (or booster circuit) that is placed in its corresponding push-pull circuit.By this, voltage divider div can produce the above-mentioned first reference voltage Vr1 in an end of resistance R 1, and can produce the above-mentioned second reference voltage Vr2 in an end of resistance R 2.
Moreover, the reverse input end of the end of differential resistance Δ R concatenation operation simultaneously amplifier OP1 and an end of resistance R 1; The reverse input end of the other end of differential resistance Δ R concatenation operation simultaneously amplifier OP2 and an end of resistance R 2.This differential resistance Δ R is in order to default bias amount V (Δ R)=[Δ R/ (R1+R2+R3+2 Δ R)] * HV to be provided, and its resistance value is less than resistance R 1, R2 or R3.Be noted that for convenience of description, the size of the differential resistance Δ R among the push-pull amplifier PP1 of present embodiment and the PP2 is to be made as to equate; And push-pull amplifier PP1 also can be made as unequal with differential resistance Δ R size among the PP2 or becomes a preset ratio among another embodiment.
Illustrate the function mode of de-coupling capacitance circuit 20 of the present invention, and be simplified illustration, below only discuss with node N11.The size property of supposing HV=3.6V, VSS=0V, deep-channel capacitor C11, C21, C31 is all identical, R1=R2=R3 and V (Δ R)=0.01V (are reference voltage Vr1=2.405V, Vr2=2.395V).By Fig. 2 A as can be known, under the normal condition, predeterminated voltage V (N11)=2.4V of node N11, and the voltage range of its selection is 2.405V～2.395V.And produce defective and when causing leakage current to flow through deep-channel capacitor C11, voltage V (N11) change on the node N11 for example is increased to 2.6V by predeterminated voltage 2.4V as above-mentioned deep-channel capacitor C11.This moment discharge cell operational amplifier OP1 just comparison reference voltage Vr1=2.405V and voltage V (N11)=2.6V, and obtain a compare result signal Ru1.Because voltage V (N11) is higher, therefore transistor N1 will come its passage of conducting (on) according to compare result signal Ru1, the voltage level that makes electric current flow to the second voltage level VSS, result node N11 just descends, and just stops up to being discharged to V (N11)=Vr1=2.405V.Certainly, Ci Shi transistor P1 is subjected to operational amplifier OP2 control to be in (off) state that opens circuit.
On the other hand, when node voltage V (N11) change, for example be reduced to 1.35V by default voltage 2.4V because of the leakage current of parasitic bipolar transistor.This moment charhing unit just voltage V (the N11)=1.35V on comparison reference voltage Vr2=2.395V and the node N11 of operational amplifier OP2, and obtain a compare result signal Ru2.Because voltage Vr2 is higher, therefore transistor P1 will come its passage of conducting (on) according to compare result signal Ru2, make electric current flow to node N11 and then its voltage level be improved, just stop up to charging to V (N11)=Vr2=2.395V to node N11 charging by the first voltage level HV.Certainly, Ci Shi transistor N1 is subjected to operational amplifier OP1 control to be in (off) state that opens circuit.
According to above-mentioned explanation as can be known, when de-coupling capacitance circuit 20 of the present invention can be subjected to deep-channel capacitor defective or parasitic transistor and influences change at the voltage of node N11 or N21, voltage V (N11) or V (N21) with change is adjusted in the scope of predeterminated voltage [(R2+R3+ Δ R)/(R1+R2+R3+2 Δ R)] * HV ± V (Δ R)/2 or [R3/ (R1+R2+R3+2 Δ R)] * HV ± V (Δ R)/2 respectively, wherein, V (Δ R)=[Δ R/ (R1+R2+R3+2 Δ R)] * HV.
Be noted that when V (Δ R) designs very hour, it is accurate that push-pull circuit PP1 or PP2 can accurately be fixed on the voltage on node N11 and the N21 position of predeterminated voltage, and solve the problem that deep-channel capacitor defective or parasitic transistor produce leakage current fully.
Therefore, the de-coupling capacitance circuit 20 of this embodiment of the present invention can not be subjected to the parasitic transistor influence, can be with the cross-pressure size fixing (for example being 1.2V) of its deep-channel capacitor C11, C21, C31, the voltage that is node N11, N21 is separately fixed at predeterminated voltage V (N11)=2.4V, V (N21)=1.2V, and can be as being subjected to the parasitic transistor influence as predeterminated voltage V (N10), the V (N20) of de-coupling capacitance circuit 10 and being offset to 1.35V and 0.45V respectively, shown in Fig. 2 B.
Moreover, please also refer to Figure 1A, 2A, 3A, 3B; In practice design, also may in the deep-channel capacitor C31 of the deep-channel capacitor C30 of Figure 1A or Fig. 2 A, produce defective.This defective can one be simulated with capacitor C 30 or C31 parallel resistor Rf=200K Ω, as shown in Figure 3A.Please refer to Fig. 3 B, by finding to have under the situation of defective among this figure at deep-channel capacitor C30 and C31, the node voltage V (N10) of Figure 1A de-coupling capacitance circuit 10 and V (N20) will be toward second voltage level VSS skews, and V (N10) approximates 1.2V, and V (N20) approximates 0V; But the node voltage V (N11) of the de-coupling capacitance circuit 20 of Fig. 2 A and V (N21) but can be unaffected because of the control of push-pull circuit PP1 and PP2, still remain on V (N11) and equal 2.4V, and it is accurate that V (N21) approximates the position of 1.2V.In addition, also can find that node voltage V (N10) does not remain on the centre of the first voltage level HV and node voltage V (N20), it is because the parasitic transistor of deep-channel capacitor makes the electric current I 2 among Fig. 3 A become the twice of convergence electric current I 1, and causes the skew of node voltage V (N10).Therefore, the cross-pressure on the capacitor C 10 will become the twice of capacitor C 20 because hypothesis flow through the electric current I f of defective (resistance R _ f) will be much larger than electric current I 0.
Fig. 4 is presented at the oscillogram that simulates under three kinds of specific settings; These three kinds of settings are respectively: one, do not use de-coupling capacitance circuit in crystal grain fully; Two, in crystal grain, use de-coupling capacitance circuit 10 (C10=C20=C30=1250pF) to be used as decoupling capacitance; Three, in crystal grain, use de-coupling capacitance circuit 20 (C11=C21=C31=1250pF) to be used as decoupling capacitance.Noting in this example, is that the deep-channel capacitor of hypothesis de-coupling capacitance circuit 10 and 20 all has parasitic bipolar transistor effect (leakage current flows through).Under first kind of setting, discovery is had one inductance L=6nH string around (series-wound) externally between power vd D=3.6V and the internal electric source HV, and the current drain that causes an about 200mA takes place at time 5ns during to 35ns.This analog result is shown among Fig. 4, presses (overshoot voltage) and weak radio to press (undershoot voltage) will be much larger than the waveform HV that includes decoupling capacitance by the radio of crossing that can find not have decoupling capacitance waveform HV ' among this figure.In addition, under second and three setting, the HV waveform that can find two kinds of settings does not almost have difference, but the node voltage V (N10) of de-coupling capacitance circuit 10 and V (N20) can be offset to 1.35V and 0.45V by the influence of the leakage current of deep-channel capacitor, cause the cross-pressure of some deep-channel capacitor excessive; And the node voltage V (N11) of de-coupling capacitance circuit 20 can remain on respectively on predeterminated voltage 2.4V and the 1.2V because of the control of push-pull circuit PP with V (N21), and then the cross-pressure on the deep-channel capacitor is remained in its tolerable scope.
In sum, the de-coupling capacitance circuit 10 of one embodiment of the invention is applied in the crystal grain as decoupling capacitance, can solve problem that prior art gate oxidation electric capacity occupies big chip area, with the problem of the withstand voltage deficiency of deep-channel capacitor.And the de-coupling capacitance circuit 20 of another embodiment can solve equally prior art, with the electric capacity problem of withstand voltage, and further solve the problem of the electric capacity cross-pressure change that deep-channel capacitor may be caused because of parasitic bipolar transistor effect or electric capacity defective.
The above description of this invention is illustrative, and nonrestrictive, and those skilled in the art is understood, and can carry out many modifications, variation or equivalence to it within spirit that claim limits and scope, but they will fall in the protection range of invention all.
Claims (19)
1. a de-coupling capacitance circuit is characterized in that, includes:
The deep-channel capacitor of a plurality of series connection, each this deep-channel capacitor comprises at least one deep-channel capacitor born of the same parents;
Wherein, the junction of per two these deep-channel capacitors forms a node, and each this node is to be biased in the predeterminated voltage scope.
2. de-coupling capacitance circuit according to claim 1 is characterized in that, an end of this de-coupling capacitance circuit connects one first voltage level, and the other end connects one second voltage level.
3. de-coupling capacitance circuit according to claim 1 is characterized in that, each deep-channel capacitor comprises a plurality of deep-channel capacitor born of the same parents parallel with one another.
4. a de-coupling capacitance circuit is characterized in that, includes:
N deep-channel capacitor of connecting mutually, each this deep-channel capacitor is to be made of at least one deep-channel capacitor born of the same parents, and N is the positive integer greater than 1;
Wherein, each this deep-channel capacitor includes first end and second end, and first end of first deep-channel capacitor connects one first voltage level, and second end connects first end of second deep-channel capacitor; First end of N deep-channel capacitor connects second end of N-1 deep-channel capacitor, and second end of N deep-channel capacitor connects one second voltage level.
5. de-coupling capacitance circuit according to claim 4 is characterized in that the junction of per two deep-channel capacitors forms a node, and this node is to be biased in the predeterminated voltage scope.
6. de-coupling capacitance circuit according to claim 4 is characterized in that, this deep-channel capacitor comprises a plurality of deep-channel capacitor born of the same parents parallel with one another.
7. a de-coupling capacitance circuit is characterized in that, includes:
The deep-channel capacitor of a plurality of series connection, these a plurality of deep-channel capacitors comprise one first deep-channel capacitor and one second deep-channel capacitor that is connected in a node;
Voltage divider is in order to produce one group of reference voltage; And
Push-pull circuit is optionally adjusted according to this group reference voltage in magnitude of voltage to a preset range of this node.
8. de-coupling capacitance circuit according to claim 7 is characterized in that, this group reference voltage comprises one first reference voltage and one second reference voltage, and wherein this push-pull circuit comprises:
One discharge cell according to the magnitude of voltage of this first reference voltage and this node, optionally discharges to this node; And
One charhing unit according to the magnitude of voltage of this second reference voltage and this node, optionally charges to this node.
9. de-coupling capacitance circuit according to claim 8 is characterized in that, this discharge cell comprises:
One first comparing unit receives the magnitude of voltage of this first reference voltage and this node, to produce one first compare result signal; And
One first switch optionally reduces the magnitude of voltage of this node according to this first compare result signal.
10. de-coupling capacitance circuit according to claim 8 is characterized in that, this charhing unit comprises:
One second comparing unit receives the magnitude of voltage of this second reference voltage and this node, to produce one second compare result signal; And
One second switch optionally promotes the magnitude of voltage of this node according to this second compare result signal.
11. de-coupling capacitance circuit according to claim 7 is characterized in that, each deep-channel capacitor comprises deep-channel capacitor born of the same parents at least.
12. de-coupling capacitance circuit according to claim 7 is characterized in that, an end of this de-coupling capacitance circuit connects one first voltage level, and the other end connects one second voltage level.
13. a de-coupling capacitance circuit is characterized in that, includes:
N deep-channel capacitor of connecting mutually, wherein N is the positive integer greater than 1, and the serial connection place of per two deep-channel capacitors connects formation N-1 node altogether;
One component depressor is in order to produce the individual reference voltage of 2 (N-1); And
N-1 push-pull circuit, this N-1 push-pull circuit are optionally adjusted the magnitude of voltage of this N-1 node according to this 2 (N-1) individual reference voltage.
14. de-coupling capacitance circuit according to claim 13 is characterized in that, the cross-pressure of each deep-channel capacitor equates.
15. de-coupling capacitance circuit according to claim 13 is characterized in that, the deep-channel capacitor of this N series connection comprises one first deep-channel capacitor and one second deep-channel capacitor, and this first deep-channel capacitor becomes a ratio with the cross-pressure of this second deep-channel capacitor.
16. de-coupling capacitance circuit according to claim 13, it is characterized in that, this N-1 push-pull circuit comprises the corresponding first node of one first push-pull circuit, and this 2 (N-1) individual reference voltage comprises one first reference voltage and one second reference voltage, and this first push-pull circuit comprises:
One reduction voltage circuit according to the magnitude of voltage of this first reference voltage and this first node, optionally reduces the magnitude of voltage of this first node; And
One booster circuit according to the magnitude of voltage of this second reference voltage and this first node, optionally promotes the magnitude of voltage of this first node.
17. de-coupling capacitance circuit according to claim 16 is characterized in that, an end of this de-coupling capacitance circuit connects one first voltage level, and the other end connects one second voltage level.
18. de-coupling capacitance circuit according to claim 17 is characterized in that, this component depressor comprises:
One first resistance is placed between this first voltage level and this reduction voltage circuit;
One second resistance is placed between this second voltage level and this booster circuit; And
One differential resistance is placed between this reduction voltage circuit and this booster circuit;
By this, this component depressor produces this first reference voltage in an end of this first resistance, and produces this second reference voltage in an end of this second resistance.
19. de-coupling capacitance circuit according to claim 13 is characterized in that, each this deep-channel capacitor comprises a plurality of deep-channel capacitor born of the same parents in parallel.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2008100827466A CN101252127B (en) | 2008-03-05 | 2008-03-05 | De-coupling capacitance circuit |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2008100827466A CN101252127B (en) | 2008-03-05 | 2008-03-05 | De-coupling capacitance circuit |
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| CN101252127A true CN101252127A (en) | 2008-08-27 |
| CN101252127B CN101252127B (en) | 2010-07-07 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101677101B (en) * | 2008-09-17 | 2012-12-12 | 台湾积体电路制造股份有限公司 | Integrated circuit with decoupling capacity |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1014547A3 (en) * | 1998-12-21 | 2000-11-15 | Fairchild Semiconductor Corporation | Low-current charge pump system |
| US6570434B1 (en) * | 2000-09-15 | 2003-05-27 | Infineon Technologies Ag | Method to improve charge pump reliability, efficiency and size |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101677101B (en) * | 2008-09-17 | 2012-12-12 | 台湾积体电路制造股份有限公司 | Integrated circuit with decoupling capacity |
| US8436408B2 (en) | 2008-09-17 | 2013-05-07 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device with decoupling capacitor design |
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| Publication number | Publication date |
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| CN101252127B (en) | 2010-07-07 |
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