CN101247130A - Code modulation method and apparatus based on low-density parity check code - Google Patents

Code modulation method and apparatus based on low-density parity check code Download PDF

Info

Publication number
CN101247130A
CN101247130A CNA2007100840451A CN200710084045A CN101247130A CN 101247130 A CN101247130 A CN 101247130A CN A2007100840451 A CNA2007100840451 A CN A2007100840451A CN 200710084045 A CN200710084045 A CN 200710084045A CN 101247130 A CN101247130 A CN 101247130A
Authority
CN
China
Prior art keywords
bit
coded
variable node
classification results
classified
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CNA2007100840451A
Other languages
Chinese (zh)
Inventor
江浩
徐�明
西尾昭彦
栗谦一
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to CNA2007100840451A priority Critical patent/CN101247130A/en
Priority to PCT/JP2008/000208 priority patent/WO2008099600A1/en
Publication of CN101247130A publication Critical patent/CN101247130A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1148—Structural properties of the code parity-check or generator matrix
    • H03M13/116—Quasi-cyclic LDPC [QC-LDPC] codes, i.e. the parity-check matrix being composed of permutation or circulant sub-matrices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1148—Structural properties of the code parity-check or generator matrix
    • H03M13/118—Parity check matrix structured for simplifying encoding, e.g. by having a triangular or an approximate triangular structure
    • H03M13/1185—Parity check matrix structured for simplifying encoding, e.g. by having a triangular or an approximate triangular structure wherein the parity-check matrix comprises a part with a double-diagonal
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1148—Structural properties of the code parity-check or generator matrix
    • H03M13/118—Parity check matrix structured for simplifying encoding, e.g. by having a triangular or an approximate triangular structure
    • H03M13/1185—Parity check matrix structured for simplifying encoding, e.g. by having a triangular or an approximate triangular structure wherein the parity-check matrix comprises a part with a double-diagonal
    • H03M13/1188—Parity check matrix structured for simplifying encoding, e.g. by having a triangular or an approximate triangular structure wherein the parity-check matrix comprises a part with a double-diagonal wherein in the part with the double-diagonal at least one column has an odd column weight equal or greater than three
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/25—Error detection or forward error correction by signal space coding, i.e. adding redundancy in the signal constellation, e.g. Trellis Coded Modulation [TCM]
    • H03M13/255—Error detection or forward error correction by signal space coding, i.e. adding redundancy in the signal constellation, e.g. Trellis Coded Modulation [TCM] with Low Density Parity Check [LDPC] codes

Abstract

A method for mapping an encoded bit of low density parity code to the high-order modulated star map comprises the following procedures: searching for the arrangement of the stopping set which is composed of variate node and has magnitude for x in the Tanner chart, and sorting the encoding bit according to whether the variate node can form the stopping set with magnitude for x; judging whether the sorting result can satisfy the request of the modulating system to the sorting result; when the sorting result does not satisfy the request of the modulating system to the sorting result, progressive-increasing the value of x for 1, and sorting the encoding bit according to whether the variate node can form the stopping set with magnitude for x until the time when the sorting result satisfies the system requirement; and mapping the bit with better error correcting capability to the position of the bit with inferior protecting power in the constellation points, and mapping the bit with inferior error correcting capability to the position of the bit with better protecting power. The invention also discloses a method for sorting the encoding bit with the number of the ring which is formed according to the variate node.

Description

Code modulating method and device based on low density parity check code
Technical field
The present invention relates to a kind of code modulating method and device, particularly, relate to mapping method and the device of a kind of LDPC coded-bit, can realize coded modulation effective and rapidly to high-order modulation constellation figure based on low density parity check code (LDPC sign indicating number).
Background technology
Low density parity check code (Low Density Parity-Check Code, LDPC Code) is a kind of strong methods for forward error correction coding that rediscovers over past ten years.Under the long code structural environment, the LDPC sign indicating number has approached shannon limit, thereby is considered to effective substitute technology of Turbo code, probably is used to next generation mobile communication and deep space communication.Gallager has proposed this notion (referring to the R.G.Gallager thesis for the doctorate: Low Density Parity Check Codes.MIT, Cambridge, Mass., September 1962) in 1962.
The LDPC sign indicating number is based on a kind of sign indicating number of parity matrix definition, and it has following characteristic: every row comprise 1 of very little fixed number j (j＞=1), and every row comprises very little fixed number k (1 of k＞j).Gallager proves: the typical minimum range of these code words is linear increasing with the increase of code length, and under the BSC channel, the typical probability of decoding error is index with code length and reduces.The thesis for the doctorate of Gallager gives the building method of LDPC sign indicating number, iterative decoding algorithm and performance evaluation thereof.Because computer level development at that time is limited, hardware is realized difficulty, so the LDPC sign indicating number is forgotten for a long time.
Up to nineteen ninety-five, Mackay and Neal have rediscovered the LDPC sign indicating number and have compared with Turbo code same excellent in performance is arranged, and under the long situation of long code, also surpassed Turbo code (referring to article " Near Shannon limit performance of lowdensity parity check codes " the .Electronics Letters of D.J.C.MacKay and R.M.Neal, 32 (18): 1645-1646, August1996.Reprinted Electronics Letters, vol 33, no 6,13th March 1997, p.457-458.).Therefore, the LDPC sign indicating number becomes new research focus, obtains everybody extensive concern.
At present, the research to the LDPC sign indicating number mainly concentrates on following direction.The first, consider the structure of LDPC sign indicating number on non-GF (2), the encoded question on polynary territory just, as GF (4), GF (8) etc.People such as Mackay and Davey has done a lot of explorations and trial in this respect (referring to thesis for the doctorate " Error-correction using Low-Density Parity-CheckCode " the Gonville and Caius College of Matthew C.Davey, Cambridge, 1999), and obtained good achievement.Check matrix on the polynary territory of structure can make performance be greatly improved meticulously.The second, the LDPC sign indicating number that Gallager proposes, the column weight of its check matrix and row are heavily fixed, and this is commonly called the LDPC sign indicating number (perhaps Gallager sign indicating number) of rule.Luby, Mitzenmacher, Shokrollahi and Spielman at first propose to construct irregular binary LDPC sign indicating number (referring to Michael G.Luby, Michael Mitzenmacher, M.Amin Shokrollahi, the article of delivering with Daniel A.Spielman that is entitled as " Improved Low-Density Parity-Check Codes UsingIrregular Graphs ", IEEE TRANSACTIONS ON INFORMATION THEORY, VOL.47, NO.2, FEBRUARY 2001:pp585-598).Luby proposed in 1998, loosened the restriction to ranks weight, constructed irregular LDPC sign indicating number, that is, the weight of every row (every row) is inequality.Result of study shows that with respect to initial Gallager sign indicating number, the performance of irregular LDPC codes has also had very big raising.This two research directions optimum organization constantly at present is to seek the abnormal LDPC code on the more excellent non-GF (2) of performance.
Massey has at first proposed chnnel coding and has modulated the thought that combines and consider, this processing mode is called as coded modulation scheme.Along with Ungerboeck has proposed convolution code and Trellis-coded modulation (Trellis codedmodulation) scheme that combines of modulation and since having obtained considerable coded modulation gain in the eighties in last century in early days, coded modulation has become a kind of effective means of improving communication system performance, and is applied in a plurality of communication standards.
In the planisphere of high order modulation, each bit in the represented bit sequence of each constellation point has embodied different protective capabilities.Fig. 1 shows the schematic diagram of different protective capabilities of the bit sequence representative of 16QAM constellation point.
The ability of each the bit antagonism channel effect during as shown in Figure 1, the pairing bit of constellation point is represented also is not quite similar.For example, in 16QAM planisphere shown in Figure 1, each constellation point can be expressed as the bit sequence that 4 bits constitute, i.e. (b 0b 1b 2b 3).Wherein bit is to (b 0b 1) be used to determine the quadrant at constellation point place, and bit is to (b 2b 3) then be used for distinguishing four different constellation point of same quadrant.Therefore, in the bit sequence of same constellation point representative, bit is to (b 0b 1) protective capability, that is, and the antagonism channel fading ability, be higher than another bit to (b 2b 3) protective capability.Therefore, can be divided into two classes to 4 bits of each 16QAM symbol representative with different protective capabilities.Correspondingly, for 2 2nThe qam constellation figure of point, the bit sequence of each constellation point representative can be divided into the n class according to its protective capability.
Simultaneously, the coded-bit in the LDPC code word also has the characteristic of incoordinate error protection, that is, each coded-bit in its code word also has different from antimierophonic ability.Corresponding to 2 2nThe planisphere of QAM, all coded-bits in the LDPC code word need be divided into the n class with same number of bits, to satisfy code modulated needs.Based on above-mentioned 2 points, how effectively each coded-bit with different error correcting capabilities in the LDPC code word to be mapped to the method for the bit position in the bit sequence of constellation point with different protective capabilities, caused chnnel coding researcher's extensive concern.
At present a kind of classification mode that proposes is based on that the column weight amount (column degree) of each coded-bit in the parity matrix of LDPC chnnel coding carries out.The article that is entitled as " Bit-Reliability Mapping in LDPC-Coded Modulation Systems " that Yan Li and William E.Ryan deliver is (referring to IEEE Communications Letters, VOL.9, NO.1, Jan 20051), and Rahnavard, N.; And Fekri, F.; The article of delivering that is entitled as " Unequal error protection using low-density parity-check codes " is (referring to International Symposium on Information Theory 2004.Proceedings.27June-2July 2004Page (s): 449).Fig. 2 shows defined capable weight of LDPC code check matrix and column weight amount.In Fig. 2, in the matrix in certain row or certain row number of non-" 0 " element represent the weight of corresponding row or column.As shown in Figure 2, the column weight amount of the 1st to 12 row is followed successively by " 3,3,3,3,2,2,2,2,1,1,1,1 ".According to Yan Li and the disclosed content of William E.Ryan, think that the pairing coded-bit of the big row of column weight amount has better error correcting capability, thereby should be mapped to the relatively poor bit position of protective capability in the bit sequence of constellation point representative.Though this method implements very simple and directly perceived, but it is unsatisfactory to the classifying quality of the little LDPC sign indicating number of column weight amount difference, if satisfy the requirement of respective coding modulation, can only select some coded-bits to put into respective classified at random under a lot of situations, lack accuracy.
In addition, this method only can be applied to the abnormal LDPC code that each column weight amount that is listed as is not quite similar in the parity matrix, and can not be applied to identical regular LDPC sign indicating number of column weight amount of each row in the check matrix.In addition, for the LDPC sign indicating number that column weight amount in the parity matrix is more or less the same, for example, one 6 * 24 rank, the code check in IEEE 802.16 standards that provide as Fig. 4 is the basic matrix of 3/4 LDPC sign indicating number, and each element in the matrix is all represented the submatrix on a z * z rank.According to the difference of the size of z, utilize same basic matrix can obtain identical and the LDPC sign indicating number that code length is different of a group code rate.Wherein element " 1 " is represented the full null matrix on a z * z rank; The row that other element is then represented z * z rank unit matrix according to { p (f, i, j) } represented value cyclic shift after resulting submatrix.The value of z is corresponding to the spreading factor z that defines in the standard f, f ∈ [0,18].Element in the matrix " 0 " is represented the unit matrix without cyclic shift, and the value of other cyclic shift { p (f, i, j) } then by corresponding spreading factor z fCalculate 0 with non-" 0 " and " 1 " element in the matrix by following expression (1):
For above-mentioned LDPC sign indicating number, utilize and can not classify to each bit in the LDPC code word effectively, thereby finish the effective mapping of coded-bit to modulation symbol based on the method for column weight amount, therefore have significant limitation.
Summary of the invention
The purpose of this invention is to provide a kind of method and apparatus that the LDPC coded-bit is mapped to high-order modulation constellation figure.Method and apparatus of the present invention is classified according to the error correcting capability of LDPC code word, these coded-bits are mapped to the particular bit position in the bit sequence of constellation point representative according to sorting result, thereby obtain bigger coded modulation gain, and can realize coded modulation effective and rapidly.
According to an aspect of the present invention, provide a kind of coded-bit of low density parity check code to be mapped to the method for high-order modulation constellation figure, comprise step: the coded-bit of low density parity check code is classified according to first kind of classification mode; Judge whether classification results satisfies the requirement of system to the coded-bit classification; When classification results does not meet the demands, use second classification mode described classification results is further classified; The bit that error correcting capability is strong is mapped to the bit position of protective capability difference in the constellation point and the bit of error correcting capability difference is mapped to the strong bit position of protective capability in the constellation point.
According to another aspect of the present invention, provide a kind of coded-bit of low density parity check code to be mapped to the method for high-order modulation constellation figure, comprise step: in Tanner figure, search the distribution that stops to collect that the size that is made of variable node is x, whether can constitute the stop collection of size according to variable node, coded-bit is classified for x; Judge whether classification results satisfies the requirement of modulating system to described classification results; When classification results does not satisfy modulating system to the requiring of described classification results, the value of x is increased progressively 1, whether can constitute the stop collection of size according to variable node for x, coded-bit is classified, satisfy system requirements up to classification results; Be mapped to the bit position of protective capability difference in the constellation point and the bit of error correcting capability difference is mapped to the strong bit position of protective capability in the constellation point with the bit that error correcting capability is strong.
According to a further aspect of the invention, provide a kind of coded-bit of low density parity check code to be mapped to the method for high-order modulation constellation figure, comprise step: searching the length that is made of variable node in Tanner figure is the quantity of the ring of y, whether can constitute the ring that length is y according to variable node, coded-bit is classified; Judge whether classification results satisfies the requirement of modulating system to described classification results; When classification results does not satisfy modulating system to the requiring of described classification results, the value of y is increased progressively 1, whether can constitute the ring that length is y according to variable node, coded-bit is classified, satisfy system requirements up to classification results; Be mapped to the bit position of protective capability difference in the constellation point and the bit of error correcting capability difference is mapped to the strong bit position of protective capability in the constellation point with the bit that error correcting capability is strong.
According to a further aspect of the invention, provide a kind of coded-bit of low density parity check code to be mapped to the method for high-order modulation constellation figure, comprise step: the column weight amount according to variable node is classified to all coded-bits; Judge whether classification results satisfies the requirement of modulating system to described classification results; When classification results does not satisfy modulating system to the requiring of described classification results, in Tanner figure, search the distribution that stops to collect that the size that is made of variable node is x, whether can constitute the stop collection of size according to variable node for x, coded-bit is classified; Judgement stops to collect the classification results that obtains and whether satisfies the requirement of modulating system to described classification results according to variable node; When according to the stopping to collect the classification results that obtains and do not satisfy modulating system of variable node to the requiring of described classification results, the value of x is increased progressively 1, whether can constitute the stop collection of size according to variable node, coded-bit is classified, satisfy system requirements up to classification results for x; Be mapped to the bit position of protective capability difference in the constellation point and the bit of error correcting capability difference is mapped to the strong bit position of protective capability in the constellation point with the bit that error correcting capability is strong.
According to a further aspect of the invention, provide a kind of coded-bit of low density parity check code to be mapped to the method for high-order modulation constellation figure, comprise step: the column weight amount according to variable node is classified to all coded-bits; Judge whether classification results satisfies the requirement of modulating system to described classification results; When classification results did not satisfy modulating system to the requiring of described classification results, searching the length that is made of variable node in Tanner figure was the quantity of the ring of y, whether can constitute the ring that length is y according to variable node, and coded-bit is classified; Whether the classification results that judgement obtains according to the ring that variable node constituted satisfies the requirement of modulating system to described classification results; When the classification results that obtains according to the ring that variable node constituted does not satisfy modulating system to the requiring of described classification results, the value of y is increased progressively 1, whether can constitute the ring that length is y according to variable node, coded-bit is classified, satisfy system requirements up to classification results; Be mapped to the bit position of protective capability difference in the constellation point and the bit of error correcting capability difference is mapped to the strong bit position of protective capability in the constellation point with the bit that error correcting capability is strong.
According to a further aspect of the invention, provide a kind of coded-bit of low density parity check code to be mapped to the method for high-order modulation constellation figure, comprise step: the column weight amount according to variable node is classified to all coded-bits; Judge whether classification results satisfies the requirement of modulating system to described classification results; When classification results did not satisfy modulating system to the requiring of described classification results, searching the length that is made of variable node in Tanner figure was the quantity of the ring of y, whether can constitute the ring that length is y according to variable node, and coded-bit is classified; Whether the classification results that judgement obtains according to the ring that variable node constituted satisfies the requirement of modulating system to described classification results; When the classification results that obtains according to the ring that variable node constituted does not satisfy modulating system to the requiring of described classification results, in Tanner figure, search the distribution that stops to collect that the size that is made of variable node is x, whether can constitute the stop collection of size according to variable node, coded-bit is classified for x; Judgement stops to collect the classification results that obtains and whether satisfies the requirement of modulating system to described classification results according to variable node; When according to the stopping to collect the classification results that obtains and do not satisfy modulating system of variable node to the requiring of described classification results, the value of x is increased progressively 1, whether can constitute the stop collection of size according to variable node, coded-bit is classified, satisfy system requirements up to classification results for x; Be mapped to the bit position of protective capability difference in the constellation point and the bit of error correcting capability difference is mapped to the strong bit position of protective capability in the constellation point with the bit that error correcting capability is strong.
According to a further aspect of the invention, provide a kind of coded-bit of low density parity check code to be mapped to the method for high-order modulation constellation figure, comprise step: searching the length that is made of variable node in Tanner figure is the quantity of the ring of y, whether can constitute the ring that length is y according to variable node, coded-bit is classified; Whether the classification results that judgement obtains according to the ring that variable node constituted satisfies the requirement of modulating system to described classification results; When the classification results that obtains according to the ring that variable node constituted does not satisfy modulating system to the requiring of described classification results, in Tanner figure, search the distribution that stops to collect that the size that is made of variable node is x, whether can constitute the stop collection of size according to variable node, coded-bit is classified for x; Judgement stops to collect the classification results that obtains and whether satisfies the requirement of modulating system to described classification results according to variable node; When according to the stopping to collect the classification results that obtains and do not satisfy modulating system of variable node to the requiring of described classification results, the value of x is increased progressively 1, whether can constitute the stop collection of size according to variable node, coded-bit is classified, satisfy system requirements up to classification results for x; Be mapped to the bit position of protective capability difference in the constellation point and the bit of error correcting capability difference is mapped to the strong bit position of protective capability in the constellation point with the bit that error correcting capability is strong.
According to a further aspect of the invention, provide a kind of coded-bit of low density parity check code to be mapped to the code modulation system of high-order modulation constellation figure, comprise step: the bit classification device is used for according to the predtermined category pattern coded-bit of the low density parity check code of input being classified; At least one interleaver is used for the coded-bit of bit grader classification is carried out Bit Interleave; Serial/parallel converter offers modulator after being used for the coded-bit after interweaving is divided into two-way; And modulator, be used for the two-way coded-bit that described serial/parallel converter provides is mapped to respectively the corresponding bits position of constellation point.
According to a further aspect of the invention, provide a kind of coded-bit of low density parity check code to be mapped to the code modulation system of high-order modulation constellation figure, comprise step: the first bit classification device is used for the coded-bit of low density parity check code of input is classified to coded-bit by first classification mode of variable node; The second bit classification device is used for classifying according to second classification mode according to the coded-bit of described first classification mode classification again; At least one interleaver is used for the coded-bit of described second bit classification device classification is carried out Bit Interleave; Serial/parallel converter offers modulator after being used for the coded-bit after interweaving is divided into two-way; And modulator, be used for the two-way coded-bit that described serial/parallel converter provides is mapped to respectively the corresponding bits position of constellation point.
According to the present invention, introduced length (length ofcircle) or it stops the sorting criterion that collection (stopping set) distributes based on the pairing ring of each coded-bit, thereby each coded-bit in the LDPC code word can be divided into corresponding a few class, satisfy code modulated requirement.Realize code modulated method with column weight amount only according to each coded-bit, method proposed by the invention not only can improve the reasonability of bit mapping, can also be applied to all identical regular LDPC coding of column weight amount, thereby may use the system of LDPC sign indicating number to have important practical value the mobile communication in future and deep space communication etc.
Description of drawings
By below in conjunction with description of drawings the preferred embodiments of the present invention, will make above-mentioned and other purpose of the present invention, feature and advantage clearer, wherein:
Fig. 1 shows the schematic diagram that the bit sequence of 16QAM constellation point has different protective capabilities;
Fig. 2 shows the schematic diagram of defined capable weight of LDPC code check matrix and column weight amount;
Fig. 3 shows the schematic diagram of the Tanner figure of LDPC coding;
Fig. 4 is according to being the schematic diagram of the parity matrix of 3/4 LDPC sign indicating number as the code check of one of alternative in prior art IEEE 802.16 standards;
Fig. 5 is the schematic diagram of the ring among the pairing Tanner figure of LDPC sign indicating number;
Fig. 6 is the schematic diagram that stops collection (stopping set) among the pairing Tanner figure of LDPC sign indicating number;
Fig. 7 shows according to the embodiment of the invention and adopts two kinds of classification modes to carry out the flow chart of coded-bit classification;
Fig. 8 shows the schematic diagram of the flow process that method that according to embodiment of the invention utilization stops to collect distribution classifies to coded-bit;
Fig. 9 shows the flow chart of the flow process that method that according to embodiment of the invention utilization stops to collect distribution classifies to coded-bit;
Figure 10 shows the schematic diagram of coded-bit being classified according to the length of embodiment of the invention utilization ring;
Figure 11 shows the flow chart of the flow process of coded-bit being classified according to the length of embodiment of the invention utilization ring;
Figure 12 shows the schematic diagram that utilizes column weight amount and stopping to collect to distribute the method that combines that coded-bit is classified according to the embodiment of the invention;
Figure 13 shows the flow chart that utilizes column weight amount and stopping to collect to distribute the flow process that the method that combines classifies to coded-bit according to the embodiment of the invention;
Figure 14 shows the schematic diagram that the method for utilizing the length of column weight amount and ring to combine according to the embodiment of the invention is classified to coded-bit;
Figure 15 shows the flow chart that utilizes the flow process that method that the length of column weight amount and ring combines classifies to coded-bit according to the embodiment of the invention;
Figure 16 shows the block diagram according to the 16QAM LDPC code modulation system of the embodiment of the invention; With
Figure 17 shows the block diagram of 16QAM LDPC code modulation system in accordance with another embodiment of the present invention.
Embodiment
With reference to the accompanying drawings embodiments of the invention are described in detail, having omitted in the description process is unnecessary details and function for the present invention, obscures to prevent that the understanding of the present invention from causing.
In order to understand the present invention, the Tanner figure of LDPC coding is described below in conjunction with Fig. 3.
Fig. 3 shows the Tanner figure of the LDPC coding corresponding with the row and column of LDPC code check matrix shown in Figure 2.As shown in Figure 3, each linear code can be expressed as a Tanner figure and (be also referred to as bipartite graph, bipartite graph), be designated as G={V ∪ C, E}, wherein gather the set that the V representative is made up of variable node (variable node), each variable node is then corresponding to the corresponding coded-bit that is listed as in the LDPC code word; Set C represents the set of check-node (check node), and each check-node is corresponding to each check equations.In other words, corresponding to going accordingly in the LDPC code word matrix).When the pairing coded-bit of the variable node among the Tanner figure has participated in the check equations of certain check-node representative (, in the column vector of the pairing check matrix of this coded-bit with the corresponding row of check-node on element be not 0), for example, the element of the 2nd, 5,9 row in the row of the 5th in the row and column of LDPC code check matrix shown in Figure 2 is not " 0 ".Therefore, can use limit (edge) will check node 5 to be connected respectively with variable node 2,5,9.In addition, the number on the limit that will link to each other with each node is called the degree (degree) of this node.So each is listed as pairing coded-bit and can be expressed as variable node (variable node) among the Tanner figure in the parity matrix of LDPC sign indicating number, the pairing parity check equation of each row is then represented by check-node (check node) in the parity matrix, as shown in Figure 3.At present, the research of LDPC coded-bit performance is based on mainly above-mentioned Tanner figure carries out, to explain the error-correcting performance of LDPC coding.
Fig. 5 shows the definition schematic diagram that encircles among the pairing Tanner figure of LDPC sign indicating number.Length is that the ring of v is to get back to the loop that this node constitutes from a certain node again through some limits in Tanner figure, comprises the closed path on v bar limit, and wherein every paths is unduplicated, and the quantity on the limit that is comprised is exactly the length of ring.As shown in Figure 5, wherein encircle 2 expressions from variable node 5, through the closed path (shown in the thick black line among Fig. 5) of checking node and variable node to get back to variable node 5, the length of this ring is 6.The length value of becate is called girth (enclosing length) among the Tanner figure.For the defined Tanner of the parity matrix of LDPC figure, length is that 4 ring is the shortest ring of length that exists.Present widespread consensus is the iterative decoding performance that the existence of becate can influence the LDPC coding, and influences the convergence of iterative decoding process, thereby will avoid in the construction process of LDPC sign indicating number as far as possible.Therefore the minimum length of each variable node ring that can constitute has determined the influence of this variable node to the LDPC iterative decoding algorithm.In other words, the minimum length of the ring that certain variable node can constitute is more little, and then its error correcting capability is just weak more, in other words, avoid length is 4 ring as far as possible, and will make the length of ring big as far as possible when the structure ring, and then can utilize this characteristic that all variable nodes are classified.
Can make G={V ∪ C, E} is a pairing Tanner figure of LDPC sign indicating number.For any v ∈ V and c ∈ C, can make d (v) and d (c) represent the degree (degree) of variable node v and check-node c respectively.Make that U is the set that variable node constituted, and U ⊆ V , The subclass that promptly belongs to the entire variable node, | U| is the set element number that U comprised, that is, and the gesture of set.If certain set is to stop collection, all check-nodes are connected to the limit number of this set and will unify to calculate together.For certain given check-node c ∈ C, can make d U(c) expression is connected to the limit number of set U by check-node c, and is called check-node c by the set degree (induced degree) that U drew.Set U is called as and stops collection (stopping set), and and if only if does not only exist the check-node that links to each other with set U by a limit, promptly each check-node all pass through 0 or more than or equal to 2 limits with gather U and be communicated with, shown in 6.For the set that variable node 1,2,3 constitutes, it is zero or more than or equal to 2 requirement that check- node 1,2,3 satisfies coupled limit number, the set that unit check-node 4 and variable node 1,2,3 constitute be connected to 1, do not satisfy above-mentioned requirements.Therefore, variable node 1,2,3 do not constitute stop the collection.In addition, check-node 4 is connected with variable node 5, and check-node 6 is not connected with variable node 1,2,3,5.Therefore, variable node 1,2,3,5 constituted stop the collection.Equally, as shown in Figure 6, variable node 5,8,9 has constituted another and has stopped collection.
The LDPC minimum value that among the pairing Tanner figure all stop to collect the element number that is comprised of encoding is called stop distance (stopping distance).According to present result of study, stop distance can estimate effectively that LDPC is coded in the upper bound of bit error rate (the BER:Bit Error Rate) performance in the BEC channel (Binary Erasure Channel), and performance under the BEC channel and the performance under AWGN (additive white Gaussian noise) channel have very strong correlation simultaneously.
By to the length (lengthof the cycle) of each coded-bit in the LDPC code word according to the ring of its formation; or the collection (stopping set) that stops that it constituted distributes; or the criterion that above-mentioned two kinds of criterions and column weight amount (column degree) combine formation sorts; each coded-bit in the LDPC code word can be divided in the bit sequence of high-order modulation constellation point and the corresponding several classes of bit protection level, thereby finish each coded-bit in the LDPC code word to the mapping of the bit sequence of planisphere.
Coded modulation is the technology that generally adopts at present in the communications field; it finishes the process of the later bit of chnnel coding to the modulation symbol mapping; be used for utilizing the difference of the protective capability of each bit in the bit sequence of planisphere representative, selectively the LDPC coded-bit be mapped in the bit sequence on the high-order modulation constellation figure and have on the bit position of different protective capabilities.In other words, the coded-bit with better error correcting capability is mapped to the relatively poor bit position of protective capability in the bit sequence of constellation point representative, thereby can utilize the code modulated potential of LDPC more fully.
The present invention is the above-mentioned characteristic according to coded-bit, promptly, according to the minimum length of ring and/or the distribution that stops to collect, obtain the error correcting capability of each coded-bit in the LDPC sequences of code bits, and each coded-bit is classified, thereby determine the mapping position of each coded-bit according to error correcting capability.
According to the present invention, based on the coded-bit of LDPC code word rule and adopt different classification modes that coded-bit is classified whether.
Can classify to the coded-bit of abnormal LDPC code word based on following five kinds of modes:
(1) according to the distribution that stops to collect that each coded-bit constituted coded-bit is sorted and classify;
(2) according to the length of the ring that each coded-bit constituted coded-bit is sorted and classify;
(3) according to the pairing column weight amount of each coded-bit and the distribution that stops to collect that constituted coded-bit is sorted and classify;
(4) according to the length of pairing column weight amount of each coded-bit and the ring that constituted coded-bit is sorted and classify;
(5) simultaneously according to the pairing column weight amount of each coded-bit, the length of the ring that is constituted and the distribution that stops to collect that is constituted are sorted to it and are classified.
Wherein above-mentioned (1) and (2) mode sorts to coded-bit based on the new length based on distribution that stops to collect and ring that proposes of the present invention respectively and classifies.In addition, divide time-like, above-mentioned (1) and (2) mode can be made up with the mode that adopts the column weight amount and classify at the coded-bit that can not be met requirement to the mode that adopts traditional column weight amount.In addition, also can utilize the column weight amount, the combination of these three kinds of modes of length of distribution that stops to collect and ring is sorted to coded-bit and is classified.
In addition, for the classification mode of the coded-bit of regular LDPC code word, because the pairing column weight amount of its each coded-bit is identical,, therefore can classify to the coded-bit of regular LDPC code word based on following three kinds of modes so can't utilize column weight amount mode to classify:
(1) according to the distribution that stops to collect that each coded-bit constituted coded-bit is sorted and classify;
(2) according to the minimum length of the ring that each coded-bit constituted coded-bit is sorted and classify;
(3) coded-bit is sorted simultaneously and classify according to the length of the ring that each coded-bit constituted and the distribution that stops to collect that constituted.
According to the present invention, can be with any mode of being used for abnormal LDPC code and regular LDPC sign indicating number as first kind of classification mode, and with alternate manner as second and/or the third classification mode make up.
Fig. 7 shows the flow chart that adopts the dual mode combination that coded-bit is classified.At first, at step S701, the bit stream of input original coding.Then, in step 702, coded-bit is classified according to first kind of classification mode.Next, at step S703, judge whether classification results satisfies the requirement of system to the coded-bit classification.If judge that in step S703 judges that classification results meets the demands, and then finishes assorting process.If judge that in step S704 judges that classification results does not meet the demands, and then uses second classification mode previous classification results is further classified.
Be that 3/4 abnormal LDPC is encoded to example as the code check of one of alternative in IEEE 802.16 standards that provide with Fig. 4 below, illustrate how coded-bit is sorted, the LDPC code word is mapped to the process of the code modulation system of 16QAM modulation system to the requirement of bit classification thereby satisfy.
Fig. 8 shows to utilize and stops to collect the schematic diagram that location mode is classified to coded-bit.At first, determine that the stop distance (stopping distance) that this LDPC encodes is 2.As can be seen, can constitute the variable node that stops to collect with stop distance is { v from the coded-bit matrix that Fig. 4 provides 2, v 4, { v 5, v 10, { v 6, v 7, { v 9, v 14, { v 15, v 16, the 2nd rower in Fig. 8 is " Y ", with this represent these ten variable nodes can constitute size be 2 stop the collection; In addition, these variable nodes all can only constitute a size be 2 stop the collection, accordingly the 3rd the row represent with " 1 ".Have 10 bits and be selected this moment, can't satisfy the requirement of selecting 12 bits, so also need to continue coded-bit is classified.
After this, determining to constitute size is 3 the variable node that stops to collect.Show that by calculating it is 3 the collection that stops that all variable nodes can constitute size, the size that each variable node constituted is that 3 the number that stops to collect is respectively { 27,24,26,24,24,21,21,26,22,24,25,25,29,22,20,20,26,30,16,12,10,9,12,12} (arranging by left-to-right order) according to the 1st to the 28th coded-bit.According to the size of its formation is 3 the number that stops to collect, and 18 bits of residue except 10 bits having selected in these 28 coded-bits are sorted and can get
v 22＜v 21＜(v 20＝v 23＝v 24)＜v 19＜(v 11＝v 12)＜(v 3＝v 8＝v 17)＜v 1＜v 13＜v 18
Stop to collect many more because variable node can constitute, its mistake that may occur then can cause in the soft information exchanging process that more stops to collect in iterative decoding process makes mistakes, so can see variable node { v from top ordering 13, v 18More responsive to channel and The noise, so itself and select 10 bits together are included in second class.Last classification results can be expressed as:
The first kind: { v 1, v 3, v 8, v 11, v 12, v 17, v 19, v 20, v 21, v 22, v 23, v 24;
Second class: { v 2, v 4, v 5, v 6, v 7, v 9, v 10, v 13, v 14, v 15, v 16, v 18.
As mentioned above, the bit in the first kind has stronger error correcting capability, so should be mapped to the relatively poor (b of protective capability in the 16QAM constellation point 2b 3) bit position; Bit in second class has relatively poor error correcting capability, so should be mapped to the stronger (b of protective capability in the 16QAM constellation point 0b 1) bit position, to improve it to antimierophonic ability.
Fig. 9 shows the abnormal LDPC coded-bit is used the mode (1) that provides previously, i.e. flow chart of each coded-bit of abnormal LDPC code being classified according to the distribution that stops to collect that each coded-bit constituted.At first, at step S901, the bit stream of input original coding.Then, in step 902, searching size and be the distribution that stops to collect of x in corresponding Tanner figure, initial value that can x is set to the stop distance of the Tanner figure of this LDPC sign indicating number correspondence.After this, at step S903, whether can constitute the stop collection of size for x according to variable node, perhaps the size of its formation is that the number that stops to collect of x is classified.Next, judge at step S904 whether classification results satisfies the requirement of system to classification results.If the judged result of step S904 then finishes this processing procedure for certainly, if the judged result of step S904 is for negating, then the value of x is increased progressively 1 at step S905, and return step S902, and continue repeated execution of steps S902 to S904, satisfy system requirements up to classification results.
The process of classifying according to the length of the ring that each coded-bit constituted is described below according to another embodiment of the invention.Be that 3/4 abnormal LDPC is encoded to example as the code check of one of alternative in IEEE 802.16 standards that provide with Fig. 4 still, illustrate how coded-bit is sorted, the LDPC code word is mapped to the process of the code modulation system of 16QAM modulation system to the requirement of bit classification thereby satisfy.
Figure 10 shows the schematic diagram that the length of the ring that utilizes coded-bit is classified to coded-bit.At first, determine that the minimum length (being girth) of the ring of this LDPC coding is 4, as can be seen from Figure 10, the variable node that can constitute length and be 4 ring is { v 2, v 4, v 5, v 6, v 7, v 9, v 10, v 14, v 15, v 16, v 20, v 21, v 22(Figure 10 is designated as " Y ").This moment, totally 13 bits were selected, and the number of bits of selecting is greater than the requirement of needed 12 bits of system.Therefore, need to continue coded-bit is classified, to select the coded-bit of 12 second classes.
After this, determine that length that above-mentioned these variable nodes can constitute is the number of 4 ring.Can obtain by calculating, the length that above-mentioned 13 variable nodes constituted be 4 ring number for 3,5,2,2,3,3,4,3,2,1,2,3,2} (position according to coded-bit is arranged by left-to-right row).Because the variable node becate that can constitute is many more, its mistake that may occur can cause in iterative decoding process that more soft information exchanging process do not restrain.And variable node v 16Only can constitute 1 length and be 4 ring,, belong in the first kind so it has stronger error correcting capability than other 12 variable nodes.The classification results that obtains at last is:
The first kind: { v 1, v 3, v 8, v 11, v 12, v 13, v 16, v 17, v 18, v 19, v 23, v 24;
Second class: { v 2, v 4, v 5, v 6, v 7, v 9, v 10, v 14, v 15, v 20, v 21, v 22.
Bit in the first kind has stronger error correcting capability, so should be mapped to the relatively poor (b of protective capability in the 16QAM constellation point 2b 3) bit position; Bit in second class has relatively poor error correcting capability, so should be mapped to the stronger (b of protective capability in the 16QAM constellation point 0b 1) bit position, to improve it to antimierophonic ability.
Figure 11 shows the abnormal LDPC coded-bit is used the mode (2) that provides previously, i.e. flow chart of each coded-bit of abnormal LDPC code being classified according to the length of the ring that each coded-bit constituted.At first, at step S1101, the bit stream of input original coding.Then, at step S1102, search length is the ring of y in corresponding Tanner figure.Initial value that can y is set to girth (the enclosing length) value of the Tanner figure of this LDPC sign indicating number correspondence.After this, at step S1103, whether can constitute the ring that length is y according to variable node, perhaps the length of its formation is that the number of the ring of y is classified.Next, judge at step S1104 whether classification results satisfies the requirement of system to classification results.If the judged result of step S1104 then finishes this processing procedure for certainly, if the judged result of step S1104 is for negating, then the value of y is increased progressively 1 at step S1105, and return step S1102, and continue repeated execution of steps S1102 to S1104, satisfy system requirements up to classification results.
Figure 12 illustrates the schematic diagram that the method for utilizing column weight amount and stopping to collect the distribution combination is classified to coded-bit, be that 3/4 abnormal LDPC is encoded to example as the code check of one of alternative in IEEE 802.16 standards that provide with Fig. 4 still, illustrate how coded-bit is sorted, the LDPC code word is mapped to the process of the code modulation system of 16QAM modulation system to the requirement of bit classification thereby satisfy.
At first, according to the pairing column weight amount of each variable node all coded-bits temporarily are divided into two classes.Because the corresponding column weight amount of all systematic bits (the 1st to 18 row) is 4, thereby has stronger error correcting capability; And the column weight amount of check bit (the 19th to 24 row) is 3 or 2, so its error correcting capability is relatively poor.Therefore, all systematic bits are included into the first kind (comprising 18 coded-bits), and all check digit are included into second class (comprising 6 bits).So just need choose 6 systematic bits from the first kind puts into second class and could satisfy the code modulated requirement of 16QAM.
The stop distance (stopping distance) of determining this LDPC coding is 2, and can constitute the variable node that stops to collect with stop distance is { v 2, v 4, { v 5, v 10, { v 6, v 7, { v 9, v 14, { v 15, v 16, this moment, totally 10 bits were selected (the 3rd rower is " Y " among Figure 12), can't satisfy the quantity of 12 bits of system requirements, so need to continue coded-bit is classified.
Next, determining to constitute size is 3 the variable node that stops to collect.Show that by calculating it is 3 the collection that stops that all variable nodes can constitute size, the size that each variable node constituted is that 3 the number that stops to collect is { 27,24,26,24,24,21,21,26,22,24,25,25,29,22,20,20,26,30,16,12,10,9,12,12} (arranging by left-to-right order) according to the 1st to the 28th coded-bit.According to the size of its formation is 3 the number that stops to collect, and 10 bits having selected are sorted and can get
(v 15＝v 16)＜(v 6＝v 7)＜(v 9＝v 14)＜(v 4＝v 5＝v 2＝v 10)
Stop to collect many more because variable node can constitute, its mistake that may occur then can cause in the soft information exchanging process that more stops to collect in iterative decoding process makes mistakes, so variable node { v 2, v 4, v 5, v 9, v 10, v 14More responsive to channel and The noise, promptly its error correcting capability is inferior to variable node { v 6, v 7, v 15, v 16, so it is included in second class.Last classification results is:
The first kind: { v 1, v 3, v 6, v 7, v 8, v 11, v 12, v 13, v 15, v 16, v 17, v 18}
Second class: { v 2, v 4, v 5, v 9, v 10, v 14, v 19, v 20, v 21, v 22, v 23, v 24.
Bit in the first kind has stronger error correcting capability, so should be mapped to the relatively poor (b of protective capability in the 16QAM constellation point 2b 3) bit position; Bit in second class has relatively poor error correcting capability, so should be mapped to the stronger (b of protective capability in the 16QAM constellation point 0b 1) bit position, to improve it to antimierophonic ability.Figure 12 has provided the detailed maps of above-mentioned assorting process.
Figure 13 shows the abnormal LDPC coded-bit is used the mode (3) provide previously, i.e. flow chart of each coded-bit of abnormal LDPC code being classified according to the column weight amount of each coded-bit and the length that stops to collect that constituted.At first, at step S1301, the bit stream of input original coding.Then, in step 1302, coded-bit is classified according to column weight amount mode.After this, at step S1303, judge whether classification results satisfies the requirement of system to classification results.If the judged result at step S1303 is certainly, then finish this assorting process.If for negating, flow process then proceeds to step S1304 in the judged result of step S1303, in corresponding Tanner figure, to search size and be the distribution that stops to collect of x, initial value that can x is set to the stop distance of the Tanner figure of this LDPC sign indicating number correspondence.After this, at step S1305, whether can constitute the stop collection of size for x according to variable node, perhaps the size of its formation is the number that stops to collect of x, and promptly all stop to collect the minimum value of institute's containing element number, classify.Next, at step S1306, judge whether classification results satisfies the requirement of system to classification results.If the judged result of step S1306 then finishes this processing procedure for certainly, if the judged result of step S1306 is for negating, then the value of x is increased progressively 1 at step S1307, and return step S1304, and continue repeated execution of steps S1304 to S1306, satisfy system requirements up to classification results.
Figure 14 illustrates the schematic diagram that method that the length of utilizing column weight amount and the ring that constituted combines is classified to coded-bit, be that 3/4 abnormal LDPC is encoded to example as the code check of one of alternative in IEEE 802.16 standards that provide with Fig. 4 still, illustrate how coded-bit is sorted, the LDPC code word is mapped to the process of the code modulation system of 16QAM modulation system to the requirement of bit classification thereby satisfy.
At first, according to the pairing column weight amount of each variable node all coded-bits temporarily are divided into two classes.Because the corresponding column weight amount of all systematic bits (the 1st to 18 row) is 4, thereby has stronger error correcting capability; And the column weight amount of check bit (the 19th to 24 row) is 3 or 2, so its error correcting capability is relatively poor.Therefore, all systematic bits are divided into the first kind (comprising 18 coded-bits), all check digit are divided into second class (comprising 6 bits), so just need choose 6 systematic bits and put into second class and could satisfy the code modulated requirement of 16QAM from the first kind.
After this, determine among the corresponding Tanner figure of this LDPC coding that the length of becate is 4, i.e. girth (enclosing length) value, the variable node that can constitute length in above-mentioned 18 systematic bits having selected and be 4 ring is { v 2, v 4, v 5, v 6, v 7, v 9, v 10, v 14, v 15, v 16, this moment, totally 10 bits were selected, and can't satisfy the requirement of system to classification, needed to continue coded-bit is classified.
Therefore, need to determine that length that above-mentioned these variable nodes can constitute is the number of 4 ring.By calculating, the length that above-mentioned 10 variable nodes constituted be 4 ring number for 3,5,2,2,3,3,4,3,2,1} (position according to coded-bit is arranged by left-to-right order).Because the variable node becate that can constitute is many more, its mistake that may occur can cause in iterative decoding process that more soft information exchanging process do not restrain.Because variable node { v 5, v 6, v 15, v 16To constitute length be that the number of 4 ring is less than other node in above-mentioned 10 variable nodes, so { v 5, v 6, v 15, v 16Than { v 2, v 4, v 7, v 9, v 10, v 14Have stronger error correcting capability, therefore with coded-bit { v 5, v 6, v 15, v 16Be included into the first kind.Last classification results is:
The first kind: { v 1, v 3, v 5, v 6, v 8, v 11, v 12, v 13, v 15, v 16, v 17, v 18}
Second class: { v 2, v 4, v 7, v 9, v 10, v 14, v 19, v 20, v 21, v 22, v 23, v 24.
Bit in the first kind has stronger error correcting capability, should be mapped to the relatively poor (b of protective capability in the 16QAM constellation point 2b 3) bit position; Bit in second class has relatively poor error correcting capability, should be mapped to the stronger (b of protective capability in the 16QAM constellation point 0b 1) bit position, to improve it to antimierophonic ability.
Figure 15 shows the abnormal LDPC coded-bit is used the mode (4) provide previously, i.e. flow chart of each coded-bit of abnormal LDPC code being classified according to the length of the column weight amount of each coded-bit and the ring that constituted.At first, at step S1501, the bit stream of input original coding.Then, in step 1502, coded-bit is classified according to column weight amount mode.After this, at step S1503, judge whether classification results satisfies the requirement of system to classification results.If the judged result at step S1503 is certainly, then finish this assorting process.If for negating, flow process then proceeds to step S1504 in the judged result of step S1503, search length is the ring of y in corresponding Tanner figure, and initial value that wherein can y is set to girth (the enclosing length) value of the Tanner figure of this LDPC sign indicating number correspondence.After this, at step S1505, whether can constitute the ring that length is y according to variable node, perhaps the length of its formation is that the number of the ring of y is classified.Next, at step S1506, judge whether classification results satisfies the requirement of system to classification results.If the judged result of step S1506 then finishes this processing procedure for certainly, if the judged result of step S1506 is for negating, then the value of y is increased progressively 1 at step S1507, and return step S1504, and continue repeated execution of steps S1504 to S1506, satisfy system requirements up to classification results.
Be noted that the present invention also can be applied to regular LDPC coded-bit is classified.In this case, the pairing column weight amount of its each coded-bit is identical, so can't utilize column weight amount mode to classify.Therefore can adopt the mode that do not relate to the column weight amount in the method that the abnormal LDPC coded-bit is classified classifying to the coded-bit of regular LDPC code word.For simplicity, detailed process can be with reference to top Fig. 7, Fig. 9, the process of Figure 11.
Figure 16 shows the block diagram according to the 16QAM LDPC code modulation system of the embodiment of the invention.The LDPC code modulation system of this embodiment comprises LDPC encoder 1601, bit classification device 1602, interleaver 1603A, 1603B, serial/parallel converter 1604A, 1604B and modulator 1605.
The operation of LDPC code modulation system is described below in conjunction with Figure 16.LDPC encoder 1601 produces the LDPC coded-bit, and the coded-bit that produces is offered bit classification device 1602.Bit classification device 1602 is divided into two classes according to the aforesaid mode that stops to collect the length of the mode of distribution or the ring that coded-bit constituted with all bits in the LDPC code word.It is the second relatively poor class coded-bit of stronger first kind coded-bit of error correcting capability and error correcting capability.Respectively this two classes coded-bit is offered interleaver 1603A respectively, 1603B carries out Bit Interleave.Because in the represented bit sequence of constellation point; the different bit positions of same bit centering have identical protective capability; therefore the coded-bit in the same class can pass through serial/parallel converter 1604A after interweaving; 1604B offers modulator 1605 after being divided into two-way, thereby is mapped to the corresponding bits position of constellation point.The higher coded-bit of error correcting capability just is mapped to the lower bit of protective capability to (b like this 2b 3); And the lower coded-bit of error correcting capability just is mapped to the stronger bit of protective capability to (b 0b 1).
Figure 17 shows the block diagram of 16QAM LDPC code modulation system in accordance with another embodiment of the present invention.The LDPC code modulation system of this embodiment comprises LDPC encoder 1701, the first bit classification devices 1702, the second bit classification devices 1703, interleaver 1704A, 1704B, serial/parallel converter 1705A, 1705B and modulator 1706.
The difference of this embodiment and previous embodiment is, adopts two bit classification devices, utilizes the classification mode of combination that coded-bit is classified.The operation of LDPC code modulation system is described below in conjunction with Figure 17.LDPC encoder 1701 produces the LDPC coded-bit, and the coded-bit that produces is offered the first bit classification device 1702.The first bit classification device 1702 can be classified to coded-bit according to the column weight amount of each coded-bit.Be noted that the first bit classification device is not limited to according to the column weight amount coded-bit be classified, also can stop to collect or the ring that constituted is classified to coded-bit according to variable node constituted.Coded-bit through first bit classification is provided for the second bit classification device 1703.The second bit classification device 1703 is according to the aforesaid mode that stops to collect the length of the mode of distribution or the ring that coded-bit constituted, or alternate manner is divided into two classes with all bits in the LDPC code word.It is the second relatively poor class coded-bit of stronger first kind coded-bit of error correcting capability and error correcting capability.Respectively this two classes coded-bit is offered interleaver 1704A respectively, 1704B carries out Bit Interleave.Because in the represented bit sequence of constellation point; the different bit positions of same bit centering have identical protective capability; therefore the coded-bit in the same class can pass through serial/parallel converter 1705A after interweaving; 1705B offers modulator 1706 after being divided into two-way, thereby is mapped to the corresponding bits position of constellation point.The higher coded-bit of error correcting capability just is mapped to the lower bit of protective capability to (b like this 2b 3); And the lower coded-bit of error correcting capability just is mapped to the stronger bit of protective capability to (b 0b 1).
According to the present invention, introduced length (length ofcircle) or it stops the sorting criterion that collection (stopping set) distributes based on the pairing ring of each coded-bit, thereby each coded-bit in the LDPC code word can be divided into corresponding a few class, satisfy code modulated requirement.Realize code modulated method with column weight amount only according to each coded-bit, method proposed by the invention not only can improve the reasonability of bit mapping, can also be applied to all identical regular LDPC coding of column weight amount, thereby may use the system of LDPC sign indicating number to have important practical value the mobile communication in future and deep space communication etc.
So far invention has been described in conjunction with the preferred embodiments.It should be appreciated by those skilled in the art that under the situation that does not break away from the spirit and scope of the present invention, can carry out various other change, replacement and interpolations.Therefore, scope of the present invention should not be understood that to be limited to above-mentioned specific embodiment, and should be limited by claims.

Claims (34)

1. the coded-bit of a low density parity check code is mapped to the method for high-order modulation constellation figure, comprises step:
According to first kind of classification mode the coded-bit of low density parity check code is classified;
Judge whether classification results satisfies the requirement of system to the coded-bit classification;
When classification results does not meet the demands, use second classification mode described classification results is further classified;
The bit that error correcting capability is strong is mapped to the bit position of protective capability difference in the constellation point and the bit of error correcting capability difference is mapped to the strong bit position of protective capability in the constellation point.
2. method according to claim 1 is wherein strong according to the classify error correcting capability of the coded-bit that obtains of second kind of classification mode according to the classify coded-bit beguine that obtains of described first kind of classification mode.
3. the coded-bit of a low density parity check code is mapped to the method for high-order modulation constellation figure, comprises step:
In Tanner figure, search the distribution that stops to collect that the size that is made of variable node is x, whether can constitute the stop collection of size, coded-bit is classified for x according to variable node;
Judge whether classification results satisfies the requirement of modulating system to described classification results;
When classification results does not satisfy modulating system to the requiring of described classification results, the value of x is increased progressively 1, whether can constitute the stop collection of size according to variable node for x, coded-bit is classified, satisfy system requirements up to classification results; With
The bit that error correcting capability is strong is mapped to the bit position of protective capability difference in the constellation point and the bit of error correcting capability difference is mapped to the strong bit position of protective capability in the constellation point.
4. method according to claim 3, wherein the initial value of x is set to the stop distance of the Tanner figure of this low density parity check code correspondence.
5. method according to claim 3 comprises that further the size that constitutes according to variable node is the number that stops to collect of x, and coded-bit is classified.
6. method according to claim 3, comprise that further the size that constitutes according to each variable node is the step that the number that stops to collect of x sorts to coded-bit, wherein according to the number that stops to collect that variable node constituted from many to few order, select the bit of the coded-bit of predetermined quantity as the error correcting capability difference.
7. the coded-bit of a low density parity check code is mapped to the method for high-order modulation constellation figure, comprises step:
Searching the length that is made of variable node in Tanner figure is the quantity of the ring of y, whether can constitute the ring that length is y according to variable node, and coded-bit is classified;
Judge whether classification results satisfies the requirement of modulating system to described classification results;
When classification results does not satisfy modulating system to the requiring of described classification results, the value of y is increased progressively 1, whether can constitute the ring that length is y according to variable node, coded-bit is classified, satisfy system requirements up to classification results; With
The bit that error correcting capability is strong is mapped to the bit position of protective capability difference in the constellation point and the bit of error correcting capability difference is mapped to the strong bit position of protective capability in the constellation point.
8. method according to claim 7, wherein the initial value of y be set to this low density parity check code correspondence Tanner figure enclose long (girth) value.
9. method according to claim 7 comprises that further the length that constitutes according to variable node is the number of the ring of y, and coded-bit is classified.
10. method according to claim 7, comprise that further the length that constitutes according to each variable node is the step that the number of the ring of y sorts to coded-bit, wherein according to the number order from less to more of the ring that variable node constituted, the coded-bit of selecting predetermined quantity is as the strong bit of error correcting capability.
11. the coded-bit of a low density parity check code is mapped to the method for high-order modulation constellation figure, comprises step:
Column weight amount according to variable node is classified to all coded-bits;
Judge whether classification results satisfies the requirement of modulating system to described classification results;
When classification results does not satisfy modulating system to the requiring of described classification results, in Tanner figure, search the distribution that stops to collect that the size that is made of variable node is x, whether can constitute the stop collection of size according to variable node for x, coded-bit is classified;
Judgement stops to collect the classification results that obtains and whether satisfies the requirement of modulating system to described classification results according to variable node;
When according to the stopping to collect the classification results that obtains and do not satisfy modulating system of variable node to the requiring of described classification results, the value of x is increased progressively 1, whether can constitute the stop collection of size according to variable node, coded-bit is classified, satisfy system requirements up to classification results for x; With
The bit that error correcting capability is strong is mapped to the bit position of protective capability difference in the constellation point and the bit of error correcting capability difference is mapped to the strong bit position of protective capability in the constellation point.
12. method according to claim 11, wherein the initial value of x is set to the stop distance of the Tanner figure of this low density parity check code correspondence.
13. method according to claim 11 comprises that further the size that constitutes according to variable node is the number that stops to collect of x, and coded-bit is classified.
14. method according to claim 11, comprise that further the size that constitutes according to each variable node is the step that the number that stops to collect of x sorts to coded-bit, wherein according to the number that stops to collect that variable node constituted from many to few order, select the bit of the coded-bit of predetermined quantity as the error correcting capability difference.
15. the coded-bit of a low density parity check code is mapped to the method for high-order modulation constellation figure, comprises step:
Column weight amount according to variable node is classified to all coded-bits;
Judge whether classification results satisfies the requirement of modulating system to described classification results;
When classification results did not satisfy modulating system to the requiring of described classification results, searching the length that is made of variable node in Tanner figure was the quantity of the ring of y, whether can constitute the ring that length is y according to variable node, and coded-bit is classified;
Whether the classification results that judgement obtains according to the ring that variable node constituted satisfies the requirement of modulating system to described classification results;
When the classification results that obtains according to the ring that variable node constituted does not satisfy modulating system to the requiring of described classification results, the value of y is increased progressively 1, whether can constitute the ring that length is y according to variable node, coded-bit is classified, satisfy system requirements up to classification results; With
The bit that error correcting capability is strong is mapped to the bit position of protective capability difference in the constellation point and the bit of error correcting capability difference is mapped to the strong bit position of protective capability in the constellation point.
16. method according to claim 15, wherein the initial value of y be set to this low density parity check code correspondence Tanner figure enclose long (girth) value.
17. method according to claim 15 comprises that further the length that constitutes according to variable node is the number of the ring of y, and coded-bit is classified.
18. method according to claim 15, comprise that further the length that constitutes according to each variable node is the step that the number of the ring of y sorts to coded-bit, wherein according to the number order from less to more of the ring that variable node constituted, the coded-bit of selecting predetermined quantity is as the strong bit of error correcting capability.
19. the coded-bit of a low density parity check code is mapped to the method for high-order modulation constellation figure, comprises step:
Column weight amount according to variable node is classified to all coded-bits;
Judge whether classification results satisfies the requirement of modulating system to described classification results;
When classification results did not satisfy modulating system to the requiring of described classification results, searching the length that is made of variable node in Tanner figure was the quantity of the ring of y, whether can constitute the ring that length is y according to variable node, and coded-bit is classified;
Whether the classification results that judgement obtains according to the ring that variable node constituted satisfies the requirement of modulating system to described classification results;
When the classification results that obtains according to the ring that variable node constituted does not satisfy modulating system to the requiring of described classification results, in Tanner figure, search the distribution that stops to collect that the size that is made of variable node is x, whether can constitute the stop collection of size according to variable node, coded-bit is classified for x;
Judgement stops to collect the classification results that obtains and whether satisfies the requirement of modulating system to described classification results according to variable node;
When according to the stopping to collect the classification results that obtains and do not satisfy modulating system of variable node to the requiring of described classification results, the value of x is increased progressively 1, whether can constitute the stop collection of size according to variable node, coded-bit is classified, satisfy system requirements up to classification results for x; With
The bit that error correcting capability is strong is mapped to the bit position of protective capability difference in the constellation point and the bit of error correcting capability difference is mapped to the strong bit position of protective capability in the constellation point.
20. method according to claim 19, further comprise when the classification results that obtains according to the ring that variable node constituted does not satisfy modulating system to the requiring of described classification results, the value of y is increased progressively 1, whether can constitute the ring that length is y according to variable node, coded-bit is classified, satisfy system requirements up to classification results.
21. the coded-bit of a low density parity check code is mapped to the method for high-order modulation constellation figure, comprises step:
Searching the length that is made of variable node in Tanner figure is the quantity of the ring of y, whether can constitute the ring that length is y according to variable node, and coded-bit is classified;
Whether the classification results that judgement obtains according to the ring that variable node constituted satisfies the requirement of modulating system to described classification results;
When the classification results that obtains according to the ring that variable node constituted does not satisfy modulating system to the requiring of described classification results, in Tanner figure, search the distribution that stops to collect that the size that is made of variable node is x, whether can constitute the stop collection of size according to variable node, coded-bit is classified for x;
Judgement stops to collect the classification results that obtains and whether satisfies the requirement of modulating system to described classification results according to variable node;
When according to the stopping to collect the classification results that obtains and do not satisfy modulating system of variable node to the requiring of described classification results, the value of x is increased progressively 1, whether can constitute the stop collection of size according to variable node, coded-bit is classified, satisfy system requirements up to classification results for x; With
The bit that error correcting capability is strong is mapped to the bit position of protective capability difference in the constellation point and the bit of error correcting capability difference is mapped to the strong bit position of protective capability in the constellation point.
22. method according to claim 21, further comprise when the classification results that obtains according to the ring that variable node constituted does not satisfy modulating system to the requiring of described classification results, the value of y is increased progressively 1, whether can constitute the ring that length is y according to variable node, coded-bit is classified, satisfy system requirements up to classification results.
23. the coded-bit of a low density parity check code is mapped to the code modulation system of high-order modulation constellation figure, comprises step:
The bit classification device is used for according to the predtermined category pattern coded-bit of the low density parity check code of input being classified;
At least one interleaver is used for the coded-bit of bit grader classification is carried out Bit Interleave
Serial/parallel converter offers modulator after being used for the coded-bit after interweaving is divided into two-way; With
Modulator is used for the two-way coded-bit that described serial/parallel converter provides is mapped to respectively the corresponding bits position of constellation point.
24. system according to claim 23, whether wherein said bit classification device can constitute the stop collection of size for x according to variable node, and coded-bit is classified.
25. system according to claim 23, wherein said bit classification device is the number that stops to collect of x according to the size that variable node constitutes, and coded-bit is classified.
26. system according to claim 23, whether wherein said bit classification device can constitute the ring that length is y according to variable node, and coded-bit is classified.
27. system according to claim 23, it is the number of the ring of y that wherein said bit classification device constitutes length according to variable node, and coded-bit is classified.
28. system according to claim 23; wherein said modulator is according to the classification results of described coded-bit; it is right that the coded-bit that error correcting capability is high is mapped to the low bit of protective capability, and it is right that the coded-bit that error correcting capability is low is mapped to the bit that protective capability is stronger in the modulation constellation points.
29. the coded-bit of a low density parity check code is mapped to the code modulation system of high-order modulation constellation figure, comprises step:
The first bit classification device is used for the coded-bit of low density parity check code of input is classified to coded-bit by first classification mode of variable node;
The second bit classification device is used for classifying according to second classification mode according to the coded-bit of described first classification mode classification again;
At least one interleaver is used for the coded-bit of described second bit classification device classification is carried out Bit Interleave;
Serial/parallel converter offers modulator after being used for the coded-bit after interweaving is divided into two-way; With
Modulator is used for the two-way coded-bit that described serial/parallel converter provides is mapped to respectively the corresponding bits position of constellation point.
30. system according to claim 29, whether the wherein said second bit classification device can constitute the stop collection of size for x according to variable node, and coded-bit is classified.
31. system according to claim 29, the wherein said second bit classification device is the number that stops to collect of x according to the size that variable node constitutes, and coded-bit is classified.
32. system according to claim 29, whether the wherein said second bit classification device can constitute the ring that length is y according to variable node, and coded-bit is classified.
33. system according to claim 29, it is the number of the ring of y that the wherein said second bit classification device constitutes length according to variable node, and coded-bit is classified.
34. system according to claim 29; wherein said modulator is according to the classification results of described coded-bit; it is right that the coded-bit that error correcting capability is strong is mapped to the low bit of protective capability, and it is right that the coded-bit of error correcting capability difference is mapped to the stronger bit of protective capability.
CNA2007100840451A 2007-02-12 2007-02-12 Code modulation method and apparatus based on low-density parity check code Pending CN101247130A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CNA2007100840451A CN101247130A (en) 2007-02-12 2007-02-12 Code modulation method and apparatus based on low-density parity check code
PCT/JP2008/000208 WO2008099600A1 (en) 2007-02-12 2008-02-12 Encoding modulation method and encoding modulation system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CNA2007100840451A CN101247130A (en) 2007-02-12 2007-02-12 Code modulation method and apparatus based on low-density parity check code

Publications (1)

Publication Number Publication Date
CN101247130A true CN101247130A (en) 2008-08-20

Family

ID=39689848

Family Applications (1)

Application Number Title Priority Date Filing Date
CNA2007100840451A Pending CN101247130A (en) 2007-02-12 2007-02-12 Code modulation method and apparatus based on low-density parity check code

Country Status (2)

Country Link
CN (1) CN101247130A (en)
WO (1) WO2008099600A1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102349257A (en) * 2009-01-14 2012-02-08 汤姆森特许公司 Method and apparatus for demultiplexer design for multli-edge type ldpc coded modulation

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102388539B (en) * 2010-02-10 2015-04-01 松下电器产业株式会社 Transmitter apparatus, receiver apparatus, transmission method and reception method

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1737133B1 (en) * 2005-06-21 2009-12-23 Samsung Electronics Co., Ltd. Apparatus and method for transmitting/receiving data in a multi-antenna communication system using a structured low density parity check (LDPC) code

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102349257A (en) * 2009-01-14 2012-02-08 汤姆森特许公司 Method and apparatus for demultiplexer design for multli-edge type ldpc coded modulation
CN102349257B (en) * 2009-01-14 2015-02-25 汤姆森特许公司 Method and apparatus for demultiplexer design for multli-edge type Low Density Parity Check coded modulation

Also Published As

Publication number Publication date
WO2008099600A1 (en) 2008-08-21

Similar Documents

Publication Publication Date Title
Mahdavifar et al. Performance limits and practical decoding of interleaved Reed-Solomon polar concatenated codes
US8176383B2 (en) Method of constructing low density parity check code, method of decoding the same and transmission system for the same
Skachek Recursive code construction for random networks
Zeh et al. Optimal linear and cyclic locally repairable codes over small fields
Valenti et al. Constellation shaping for bit-interleaved LDPC coded APSK
CN101867379B (en) Cyclic redundancy check-assisted convolutional code decoding method
CN107919874B (en) Syndrome computation basic check node processing unit, method and computer program
Babar et al. Polar codes and their quantum-domain counterparts
KR101895164B1 (en) Methods and devices for error correcting codes decoding
CN107979445B (en) Syndrome decoding based on basic check nodes using pre-ordered inputs
Miloslavskaya et al. Design of binary polar codes with arbitrary kernel
Pfister et al. Symmetric product codes
CN103731157B (en) The combined structure method of Quasi-cyclic Low-density Parity-check Codes
Nóbrega et al. Multishot codes for network coding: Bounds and a multilevel construction
Zhu et al. Fast list decoders for polarization‐adjusted convolutional (PAC) codes
Yang et al. Design and optimization of protograph LDPC-coded multipulse PPM systems over Poisson channels
Kurtas et al. System perspectives for the application of structured LDPC codes to data storage devices
Panem et al. Polynomials in error detection and correction in data communication system
Xu et al. Distance spectrum and optimized design of concatenated polar codes
CN101247130A (en) Code modulation method and apparatus based on low-density parity check code
Lv et al. New constructions of binary MDS array codes and locally repairable array codes
Bitouzé et al. Error correcting coding for a nonsymmetric ternary channel
Zhang et al. Girth-10 LDPC codes based on 3-D cyclic lattices
Gaurihar et al. Design and implementation of ldpc codes and turbo codes using fpga
Shi et al. Two piggybacking codes with flexible sub-packetization to achieve lower repair bandwidth

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C02 Deemed withdrawal of patent application after publication (patent law 2001)
WD01 Invention patent application deemed withdrawn after publication

Open date: 20080820